Abstract: A pulse generation circuit and stagger pulse generation circuit are provided. The pulse generation circuit includes: an oscillation circuit that receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment circuit that receives the first oscillation signal and a magnification selection signal and outputs a second oscillation signal, the period of the second oscillation signal is a period of the first oscillation signal or a period of an oscillation adjustment signal, and the second oscillation signal is selected according to the magnification selection signal; and a pulse conversion circuit that receives the second oscillation signal and outputs a pulse signal, the pulse of the pulse signal is generated according to the rising or falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.

Abstract: An electrical unit may include a current controller including an electrical regulator, a control circuit connected to a first input of the electrical regulator, a timer connected to a second input of the electrical regulator, and/or a turn-off circuit including a turn-off switch. The current controller may be configured to provide a first output signal in a first mode and a second output signal in a second mode. The current controller may be configured to transition from the first mode to the second mode based on a timer output of the timer. An electrical system may include an electrical unit and or a switch connected to the electrical unit. The switch may include a coil. The electrical unit may be configured to provide the first output signal to the coil in the first mode and provide the second output signal to the coil in the second mode.

Abstract: A signal output circuit and a circuit for outputting a delayed signal are provided. The signal output circuit includes: a first control subcircuit, configured to receive a first pulse signal and an input signal and output a first adjustment signal, a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal; a second control subcircuit configured to receive a second pulse signal and the input signal and output a second adjustment signal; and the signal output subcircuit is configured to receive the first adjustment signal and the second adjustment signal, and output a delayed output signal, a rising edge of the delayed output signal is generated according to the first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated according to the second preset edge of the second adjustment signal.

Abstract: A transmitter of the present disclosure includes: an output terminal; a driver that performs transition of a voltage of the output terminal among a plurality of voltages; and a controller that controls the driver to cause transition start timing in one voltage transition in voltage transition among the plurality of voltages to be later than transition start timing in another voltage transition.

Abstract: Debug time stamp counters in a computing device may be synchronized based on signals indicating awakening of a component of the computing device from a sleep state. A count from a global counter in a first component may be loaded into a replica global counter in a second component. The count from the global counter may be loaded into a first debug time stamp counter in the first component in response to a first preload signal indicating awakening of the first component from a sleep state or in response to a second preload signal indicating awakening of the second component from a sleep state. The count from the replica global counter may be loaded into a second debug time stamp counter in the second component in response to the second preload signal.

Abstract: A light emitting diode driving apparatus includes a first light emitting diode driving unit and a second light emitting diode driving unit. The first light emitting diode driving unit includes a plurality of first light emitting diode driving subunits in series. The second light emitting diode driving unit includes a plurality of second light emitting diode driving subunits in series. The first light emitting diode driving unit and the second light emitting diode driving unit are electrically connected in parallel to receive a direct current power. A light signal is transmitted between the first light emitting diode driving unit and the second light emitting diode driving unit in series.

Abstract: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a calibrated drive impedance when an “on” output is to be generated, and the pull-up network is configured to produce a calibrated drive impedance when an “off” output is to be generated. In termination mode, the pull-up network and the pull-down network are configured to produce a calibrated pull-up resistance and pull-down resistance respectively such that together, they form a split termination.

Abstract: A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a detector. The variable impedance element has an impedance between first and second switch terminals that is determined by a signal on a control terminal, the ferroelectric capacitor being connected between the control terminal and the first switch terminal. A reset signal coupled to the control terminal causes the ferroelectric capacitor to be polarized in the first polarization state. The count port is configured to receive pulses to be counted, the count port being connected to the first switch terminal by a conductive load. The detector generates a count complete signal if a potential on the first terminal exceeds a threshold value while the count port is receiving one of the pulses.

Abstract: A delay measuring circuit includes a first trigger-signal generating unit that, when a value of a signal input to a circuit under test, changes, generates a first trigger signal. The delay measuring circuit includes a second trigger-signal generating unit that, when a value of a signal output from the circuit under test changes, generates a second trigger signal. The delay measuring circuit includes a delay unit that includes a plurality of delay elements connected in series. The delay measuring circuit includes a delay information retaining unit that individually captures and retains the first trigger signal output from each of the delay elements included in the delay unit between when the first trigger signal is generated by the first trigger-signal generating unit and when the second trigger signal is generated by the second trigger-signal generating unit.

Abstract: A synchronization circuit that synchronizes received data, includes: a determiner for determining whether or not data with a phase of a internal clock can be stably captured by the synchronization circuit, when the synchronization circuit accepts the data received from another device connected to the synchronization circuit with the phase of the internal clock of the synchronization circuit; a first flip-flop circuit accepting the data and the internal clock, capturing the data with the phase of the internal clock and synchronizing the data, when the determiner determines that the synchronization circuit can stably capture the data; a second flip-flop accepting the data and an inverted internal clock that has a phase obtained by inverting the phase of the internal clock, capturing the data with the phase of the inverted internal clock, and synchronizing the data, when the determiner determines that the synchronization circuit can not stably capture the data.

Abstract: Systems and methods disclosed herein may be useful for use in landing identification. In this regard, a method is provided comprising receiving pulse information over a first time period, wherein the pulse information is indicative of an angular distance traveled by a first wheel, comparing the pulse information to a threshold value, and determining a likelihood of a landing event based upon the comparison. In various embodiments, a system is provided comprising a monstable multivibrator in electrical communication with a metal-oxide-semiconductor field-effect transistor (MOSFET), a resistor-capacitor network in electrical communication with the MOSFET, and a comparator that receives a voltage from the resistor-capacitor network and a reference voltage.

Abstract: A hysteresis receiver containing two inverters and a logic controller. The inverters are implemented with threshold voltages equaling Vil and Vih, which together define the hysteresis window. The inverters receive the input signal and generate a respective inverted value. The logic controller propagates as output one of the two inverted values if the two inverted values are equal, and a prior value (corresponding to a previous sample) if the two inverted values are not equal. A receiver circuit with a hysteresis window defined by Vil and Vih, is obtained as a result.

Abstract: This invention relates to monostable and astable multivibrators in which the pulse width or frequency stability, respectively is increased by reducing the effect of the comparator input offset voltage. The reduction is accomplished by alternately reversing the input connections to the comparator.

Abstract: A P-ECU controls an actuator which drives a shift control mechanism. An encoder signal acquisition unit acquires signals output from an encoder which detects a rotational angle of the actuator. A counter calculates a count value from the output signals of the encoder. An energization control unit controls energization to the actuator. A first phase-matching unit uses the Z-phase signal of the encoder to match the count value with energized phases so as to find a correspondence therebetween and a second phase-matching unit matches the count value with energized phases to find a correspondence therebetween without using the Z-phase signal of the encoder. If the first phase-matching unit detects an abnormality of the encoder, the second phase-matching unit subsequently performs phase matching.

Abstract: A method and system is provided for clock/data recovery for self-clocked high speed interconnects. A data signal is received and then equalized. The equalized data signal then provides the trigger to separate “ones” and “zeros” one-shots. The equalized Manchester data signal is also integrated, compared with a threshold value to determine the negative and positive peaks of the data signal. Then after the appropriate peak is determined, a mid-bit signal is sent as input to a set-reset flip-flop which thereby outputs an asynchronous recovered non-return to zero signal. This asynchronous recovered non-return to zero signal then provides an enable input to the “ones” one-shot and the complementary asynchronous recovered non-return to zero signal provides an enable input to the “zeros” one-shot. The “ones” one-shot outputs a “ones” clock signal and the “zeros” one-shot outputs a “zeros” clock signal. These two signals are verified and a recovered clock out signal is provided.

Abstract: An oscillator to generate a low phase-noise reference signal at an oscillation frequency includes a frequency generator to generate the reference signal responsive to a control signal, and a delay element made of a high-temperature superconductor material. The delay element time-delays the reference signal and provides a low phase-noise time-delayed reference signal when cooled to a cryogenic temperature. The oscillator includes a phase detector to generate the control signal from a phase difference between the time-delayed reference signal and a phase-shifted reference signal. The delay element may comprise a coplanar waveguide having a length between 500 and 1000 meters arranged randomly on a substrate having a diameter of between five and thirteen centimeters. The delay element may provide a delay ranging from five to fifteen microseconds. The coplanar waveguide may be comprised of Yttrium-Barium-Copper Oxide disposed on either a Lanthanum-Aluminum Oxide or a Magnesium Oxide substrate.

Abstract: A static latch can be converted to a dynamic latch by closing a pair of switches. When the switches are open, a first pair of back-to-back transistors serves as the static latch. When the switches are closed, a second pair of back-to-back transistors is connected to the first pair so the two pairs acting together serve as a dynamic latch.

Abstract: The present invention provides a mechanism for combining programming signals to provide an output signal, the properties of which depend only on selected properties of the programming signals. An embodiment of the invention includes first and second edge-to-pulse converters. The first edge-to-pulse converter generates an intermediate signal having a width determined by received initiation and termination signals. The second edge-to-pulse converter generates an output signal, responsive to the intermediate signal and the termination signal. The output signal has a width determined by a first edge of the initiation signal and a first edge of the termination signal.

Abstract: A circuit includes a second switching unit, a first switching unit that is connected to and selectively actuates the second switching unit, and a capacitive voltage divider including first, second and third capacitances connected in series. The first and second switching units are connected respectively to first and second junctions between the first and second and the second and third capacitances respectively. An associated method involves applying a supply voltage to the voltage divider so as to charge the first and second junctions, discharging the first junction through the first switching unit, which, dependent on the voltage of the first junction, selectively actuates the second switching unit to supply an additional charging current to the second junction. A time-limited signal such as a power-on reset signal is tapped from the first or second switching unit or from the second junction. Thereafter, the circuit draws no further current.

Abstract: The on-time of a pulse signal is controlled by comparing a ramp signal to an input signal that is dynamically selected from two signals. A first operating mode is active when a clock signal is in a first logic state, where the pulse signal is reset. A second operating mode is initiated when the clock signal changes from the first logic state to a second logic state. During the second operating mode, the ramp signal is compared to the first signal. A third operating mode is initiated when the ramp signal exceeds the first signal during the second operating mode. During the third operating mode, the pulse signal is set and the ramp signal is compared to the second signal. The pulse signal is reset when the when the ramp signal exceeds the second signal in the third operating mode such that the on-time of the pulse signal is controlled.

Abstract: A pulse generation circuit delivers an output pulse whose width is tailored to the load. The pulse generation circuit comprises the following components. A drive circuit has an input coupled to receive a clock signal and an output coupled to drive a load. A comparator has an input coupled to the output of the drive circuit. Another input of the comparator is supplied by a reference voltage. A feedback circuit comprises logic gates and is coupled between the output of the comparator and the input of the drive circuit. The feedback circuit terminates a pulse output from the drive circuit when the pulse voltage output from the drive circuit exceeds the reference voltage. The reference voltage is higher than a voltage required to trigger the logic gates and a voltage required to drive the load. This ensures that the load is driven adequately over a wide range of load currents and capacitances.

Abstract: The present invention relates a monostable circuit adapted to provide a delay having a length inversely proportional to an input signal, characterized by comprising generating means (21, 22) adapted to generate a signal proportionally to an input signal (Vin) and to a corrective factor (35), comparing means (23) adapted to compare the value of said signal with a prefixed value range (Imin, Imax) and correcting means (24) adapted to correct said corrective factor (35) in the case that the value of said signal is out of said prefixed value range (Imin, Imax).

Abstract: A circuit for providing a minimum wake-up time, in which a monostable circuit generates the WAKE-UP signal for a time at least as long as a minimum time established by the monostable circuit. The circuit is structured to extend the WAKE-UP signal for a time necessary to equal the minimum time that is established by the monostable circuit and to disable the WAKE-UP signal at the end of the variation of the input signal of the device being controlled.

Abstract: A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit.

Abstract: In the process for converting a frequency signal to a DC voltage according to the invention a first and a second output voltage signal (UA1, UA2) are generated from the frequency signal. Each of the output voltage signals is a sequence of rectangular pulses the pulse sequence frequency of which is equal to a frequency f of the frequency signal. These are converted with a first and a second lowpass filter to a first DC voltage signal and a second DC voltage signal, respectively, with the second DC voltage signal being used to influence the pulse width T0 of the rectangular pulses of at least the first output voltage signal. This makes it possible to build a simple frequency-to-voltage converter using cost-effective standard monoflops in which a largely linear correlation between frequency f of the frequency signal and the magnitude of the first DC voltage signal is realized in a simple manner.

Abstract: The present invention provides a mechanism for combining programming signals to provide an output signal, the properties of which depend only on selected properties of the programming signals. An embodiment of the invention includes first and second edge-to-pulse converters. The first edge-to-pulse converter generates an intermediate signal having a width determined by received initiation and termination signals. The second edge-to-pulse converter generates an output signal, responsive to the intermediate signal and the termination signal. The output signal has a width determined by a first edge of the initiation signal and a first edge of the termination signal.

Abstract: The object of the present invention is to provide the telemetering apparatus, which telemeters electric power, gas, and waterworks, for telemetering via a telephone network with an exchange, wherein the telemetering apparatus responds to the normal polarity inversion, the slow polarity inversion, and calling bell signal applied to the communication line therebetween upon starting or releasing of use of the communication line. To attain the above object, the telemetering appears according to the present invention comprises detection means for detecting a rising edge or falling edge of those polarity inversions and signal characterized thereby with reference to the respective predetermined voltage and the respective predetermined period, thus distinguishing one of these polarity inversions and signal from the others.

Abstract: Method and device for reducing the time constant of a system having a conductor connected thereto by connecting an impedance between the conductor and a potential as the voltage on said conductor exceeds a preselected value.

Abstract: A circuit for enabling a servo to perform an automatic system recovery and a method therefor, involves the provision of a timer and associated circuit in the servo˜such that the servo system can transmit a system normal signal to the timer at predetermined intervals. Once the servo system is abnormally terminated, resulting in an interruption of the transmission of the normal signal, the timer is triggered to generate a reset signal for restarting the servo so as to complete the reset process of the system.

Abstract: CMOS integrated circuitry responsive to a clock source having an approximately 50% duty cycle includes a one shot having an input terminal connected to be responsive to the clock wave source. The one shot derives a pulse train in response to cycles of the clock. Each pulse in the pulse train has a duration substantially less than one-half cycle of the clock wave, is initiated in response to and during a clock wave transition, and persists for a period after the transition has been completed. Latches respond to plural data signals and the pulse train so each latch is activated to be responsive to its associated data signal only during the pulses.

Abstract: A time domain filter circuit is provided with a switch for prohibiting inputting for the time between a change of an input signal and discharging a capacitor to 0, prior to a monostable multivibrator, so that a change of the next input signal is not accepted for a fixed time period since the input signal has been inverted. The time domain filter circuit detects a change of an input signal relative to an output signal, and detects a predetermined fixed time period based on the timing of the change by the monostable multivibrator using a charging time constant of the capacitor, so that an output signal level is changed so as to correspond to the input signal after the predetermined fixed time period elapses.

Abstract: The object of this invention are bistable, monostable and astable multivibrator in which the switching transition level is stable and relatively independent of ambient temperature. This reduction is accomplished by using an auto-zero amplifier system with an input offset voltage of substantially zero volts.

Abstract: A pulse generating device generates an output pulse by controlling the amplitude of a triangular wave at a constant level by use of an AGC circuit and wave-shaping the triangular wave when the triangular wave is generated by triggering a monostable multivibrator circuit by an input pulse, driving an integrating circuit having substantially the constant charging/discharging ratio by an output of the monostable multivibrator circuit, and controlling a current source which supplies a current to the integrating circuit according to an output of comparison between the integrated output and a reference voltage.

Abstract: A motor control circuit controls operation of a motor for making or breaking one or more pairs of contacts of a power switching device such as a circuit breaker. The motor control circuit includes a logic circuit responsive to a control input signal and an enable signal for producing an active signal state when both the control signal and the enable signal are present, and for producing an inactive logic signal state when either of the control signal and the enable signal is not present. A switching control signal producing circuit is responsive to said active state of the logic signal for producing a switching control signal for operating the motor for a predetermined time interval sufficient to perform one of opening and closing of the one or more pairs of contacts.

Abstract: An output driver circuit including a first path from an output pad to ground through a first switch, and a second path from the output pad to ground through series-connected second and third switches. The first switch is directly connected to a pull-down signal source, and one of the second and third switches is connected to the pull-down signal source through a one-shot circuit. In a pull-up state, the first and second switches are opened, and the one-shot circuit generates a stabilized output signal which closes the third switch. When the output driver circuit switches to a pull-down state, the first switch is closed, thereby connecting the output pad to ground via the first path. The signal change also closes the second switch. In addition, due to a propagation delay of the second signal through the one-shot circuit, the third switch initially remains closed, thereby also connecting the output pad to ground via the second path.

Abstract: According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by utilizing either a pull-up or pull-down transistor to pull the input of the circuit to a state that minimizes power consumption during periods in which the circuit is inactive. By tying the circuit input high or low during inactivity, node toggling is reduced or eliminated in that circuit. In the preferred embodiment, the inputs to the circuit all pulled after a time of inactivity which is proportional to the leakage current of the leakiest transistor in the circuit. By timing the input pulling proportional to the leakage current, the power consumption is minimized without excessive power loss caused by the pulling itself.

Abstract: A byte accessible memory interface circuit using a reduced set of memory control signals. The present invention includes an interface circuit having a reduced set of memory control signals for performing word length reads and writes to an external memory module containing a plurality of integrated circuit (IC) memory chips. The interface circuit contains a respective multiplexer and a respective register circuit for each byte of the word length data. The multiplexers select a byte of data from either an on-chip data bus or from a bus carrying data read from the external memory module. To perform a full length word write, the data from the on-chip bus is loaded into the registers (via the multiplexers) and then written to the memory module. To perform a partial length word write, a pre-read operation is performed at the target address and a word length data is loaded into the registers. The new data is then received over the on-chip data bus and routed by the multiplexers into the byte locations to be changed.

Abstract: High speed multivibrator circuits operable with lower operating voltages are disclosed. A multivibrator circuit comprises an operating voltage source, first and second nonlinear amplifier components, each comprising a first and a second main electrode and a control electrode, wherein the first main electrode of the second amplifier component is connected to control the control electrode of the first amplifier component, and the first main electrode of the first amplifier component is connected to control the control electrode of the second amplifier component. A capacitor is connected between the second main electrode of the first and second amplifier components. First and second resistors connect the first main electrode of the first and second amplifier components to a first potential of the operating voltage source. A pull-down circuit is connected between the second main electrodes of the first and second amplifier components and a second potential of the operating voltage source.

Abstract: A one-shot circuit comprises a pulse generation circuit having an external clock terminal adapted to receive an external clock signal, a reset terminal coupled to receive a reset signal, and an internal clock terminal on which the pulse generation circuit develops an internal clock signal. The pulse generation circuit operates in a first mode to drive the internal clock signal from a first level to a second level in response to a transition of the external clock signal from a first level to a second level. The pulse generation circuit operates in a second mode to drive the internal clock signal from the second level to the first level in response to the reset signal going active. A delay circuit has input and output terminals coupled to the internal clock terminal and reset terminal, respectively, of the pulse generation circuit. The delay circuit operates to drive the reset signal active a delay time after the pulse generation circuit drives the internal clock signal from the first level to the second level.

Abstract: A dynamic pulse register which uses a standard clock signal and exhibits reduced propagation delay. The dynamic pulse register includes a precharge logic block configured to precharge an evaluate signal and an evaluate complement signal during a precharge phase. During an evaluate phase, a pulldown logic block is configured to discharge either the evaluate or evaluate complement signal in response to a valid data input to the pulse register. A driver logic block is configured to convey a data out signal as the complement of the evaluate complement signal, and a data out complement signal as the complement of the evaluate signal. Either the data out signal or the data out complement signal is thus charged (thereby producing the rising edge of the output pulse) in response to the discharging performed by the pulldown logic block.

Abstract: The disclosure relates to an electrical circuit used in automotive passenger restraint systems. The circuit utilizes reliable and inexpensive electrical components to provide one-shot actuation of a load. In addition, the circuit allows for very low quiescent current draw, making it ideal for automotive applications.

Abstract: A controllable one-shot circuit for use in a control unit of a memory circuit, for asserting a control signal with variable (and controllable) duration in response to a trigger signal, and a state machine for controlling memory operations of a memory circuit which includes such a controllable one-shot circuit. In preferred embodiments, the one-shot and the state machine of which it is a part are implemented as parts of a single memory chip (preferably, a nonvolatile memory chip such as an integrated flash memory circuit). Other aspects of the invention are methods of operating a state machine of a memory circuit to generate control signals for use in controlling memory operations performed by the memory circuit.

Abstract: An emitter-coupled multivibrator circuit comprises two transistors (Q1, Q2), between which is provided a positive feedback by connecting each transistor base to the collector of the other transistor. In the multivibrator, the transistors (Q1, Q2) are connected to operating voltages via coils (L1, L2, L3, L4) instead of using conventional resistors and current sources. This lowers the necessary operating voltage, since no DC voltage loss is provided across the coils. Additionally, this improvement increases amplification during the avalanche process and thus the speed of the whole circuit. Further, the waveform of a signal is closer to the sinusoidal form at high frequencies. The speed of the circuit can be increased further by providing an electromagnetic coupling between the coils (L1, L2, L3, L4).

Abstract: A dynamic pulse register which uses a standard clock signal and exhibits reduced propagation delay. The dynamic pulse register includes a precharge logic block configured to precharge an evaluate signal and an evaluate complement signal during a precharge phase. During an evaluate phase, a pulldown logic block is configured to discharge either the evaluate or evaluate complement signal in response to a valid data input to the pulse register. A driver logic block is configured to convey a data out signal as the complement of the evaluate complement signal, and a data out complement signal as the complement of the evaluate signal. Either the data out signal or the data out complement signal is thus charged (thereby producing the rising edge of the output pulse) in response to the discharging performed by the pulldown logic block.

Abstract: A phase-locked loop of the type including a locking aid circuit providing a d.c. presetting signal representative of the carrier frequency of an input signal to set the quiescent frequency of a controlled oscillator of the phase-locked lop. The locking aid circuit includes a monostable latch clocked by the input signal to provide pulses of predetermined width, the presetting signal corresponding to the mean value of these pulses.

Abstract: An emitter-coupled multivibrator circuit comprises two transistors (Q1, Q2), between which a positive feedback is provided by connecting each transistor base via buffer transistors (Q3, Q4) to the collector of the other transistor. In the multivibrator, the transistors (Q1, Q2, Q3, Q4) are connected to operating voltages via coils (L1, L2, L3, L4, L5, L6) instead of using conventional resistors and current sources. This lowers the necessary operating voltage, since no DC voltage loss is provided across the coils. Additionally, this improvement increases amplification during the avalanche process and thus the speed of the whole circuit. Further at high frequencies, the waveform of a signal is closer to a sinusoidal form. The speed of the circuit can be increased further by providing an electromagnetic coupling between the coils (L1, L2, L3, L4, L5, L6).

Abstract: A clock-controlled monostable multivibrator circuit comprises a multivibrator circuit arrangement and an associated pulse duration control circuit. The multivibrator has an input terminal to which an input signal is applied, an output terminal from which an output pulse is produced in response to the application of the input signal to the input terminal, and a control terminal. The pulse duration control circuit produces a reference parameter which is coupled to the control terminal of the multivibrator circuit arrangement. A clock signal is applied to a clock input of the pulse duration control circuit and is operative to establish the magnitude of the control parameter and thereby the duration of the output pulse produced by the multivibrator circuit arrangement.

Abstract: A self-resetting logic stage provides for a relatively faster propagation of pulse signals and for relatively less power consumption. For a self-resetting logic stage in a digital logic path of successive logic stages, a forward path creates the forward edge for an output pulse signal and a reset path creates a reset or trailing edge for the output pulse signal. The propagation delay for the reset path may be increased for successive stages in the logic path to minimize or avoid overlap current. As the increased propagation delay increases the width of a pulse signal as the pulse signal propagates from stage to stage, logic stages in the logic path may be configured to reduce the width of the pulse signal, for example when the pulse signal approaches a width that may limit the cycle time for the logic path. Logic stages in the logic path may also be configured to provide for relatively quicker reset recovery to minimize any increase in cycle time.

Abstract: The bias control means determines the operating mode only when the trigger input comes into a valid state or the inverted output signal is low level, and determines the power saving mode in other cases. During the power saving mode, the comparator does not operate since a bias current is not supplied, therefore, the pulse generator of the present invention can attain a low power consumption. Also, the pulse generator of the present invention can generate an output signal having a desired width regardless of the width of the trigger input.

Abstract: A one-shot current circuit generates a current for a desired period during an input signal transition, the desired period during an input signal transition being proportional to the edge rate of the input signal. The circuit includes a MOS transistor device which selectively conducts current between an input terminal and a current generating circuit. The current generating circuit can be a bipolar transistor having its base coupled to the input terminal and a main current path between a circuit output and a supply voltage.