Abstract: Example systems and methods described herein relate to radio communication architectures and techniques for beamforming and down-conversion without a priori knowledge of the source location or frequency. An example radio receiver includes a plurality of antenna elements that include a first element, a second element, and a third element. The radio receiver also includes a plurality of mixers coupled to the plurality of antenna elements and a combiner coupled to the plurality of antenna elements. A signal incident on the first element is mixed with itself via a first mixer of the plurality of mixers. An output of the first mixer is mixed with a signal incident on the second element via a second mixer of the plurality of mixers, and an output of the second mixer is combined via the combiner with a signal incident on the third element.

Abstract: A controller for a micromechanical actuator, and corresponding actuating system, micro-mirror system and method, including a first input for a reference signal, a second input for a measuring signal denoting a recorded response to a control signal, a first controller element to filter/attenuate predefined frequency modes and/or predefined frequency components in the received reference signal and to output a filtered/attenuated reference signal, a second controller element to modify the received measuring signal to minimize the quality of the first/further modes by processing the received measuring signal and to output a modified measuring signal, a third controller element to minimize deviation between the filtered/attenuated reference and received measuring signals and to output a minimized reference signal, a fourth controller element to rotate the phase of the difference between the minimized reference and modified measuring signals for at least one predefined frequency and to transmit the modified referen

Abstract: Systems, methods, apparatuses, and computer readable media are disclosed for providing interference rejection in ultra-wideband real time locating systems. In one embodiment, an ultra-wideband (UWB) receiver is configured to: receive an interference signal from a source positioned outside a monitored region; receive a composite signal transmitted from a tagged object moving about a playing field within the monitored region, wherein the composite signal comprises a location signal and a component of the interference signal; detect whether the component of the interference signal exceeds a threshold value; and adjust, via a processor, filtering of the composite signal to attenuate the component of the interference signal based on whether the component of the interference signal exceeds the threshold value. Some embodiments provide for filtering of the composite signal using a combiner while others employ a tunable notch filter.

Abstract: A system and method for a cold start of a vehicle are provided. The method includes setting a target electrical angle by adding a setting angle to a previously stored initial electrical angle of a driving motor and applying an electric current value that corresponds to the set target electrical angle to the driving motor.

Abstract: According to one embodiment, a low frequency drive control circuit for use with an inductive load comprises a comparator configured to receive a high frequency signal at a first input and a smoothly varying low frequency signal for modulating the high frequency signal at a second input. The comparator is further configured to produce a pulse width modulated output of the low frequency drive control circuit for use in generating a smoothly varying low frequency load current in the inductive load. In one embodiment, the inductive load can comprise a DC brushed motor. In one embodiment, the low frequency drive control circuit can be implemented as part of an integrated circuit further comprising a switching circuit configured to use the pulse width modulated output of the comparator to generate the smoothly varying low frequency load current, which may be a substantially sinusoidal load current, for example.

Abstract: A power control method for performing phase control is provided. The method includes generating a zero-crossing signal that indicates a first level if an absolute value of AC voltage is smaller than a predetermined value, and indicates a second level if the absolute value of the AC voltage is larger than the predetermined value; detecting a zero-crossing width and a non-zero-crossing width, the zero-crossing width being a time width for a case where the absolute value of the AC voltage is smaller than the predetermined value, the non-zero-crossing width being a time width for a case where the absolute value is larger than the predetermined value; detecting a frequency and a voltage value of the AC voltage based on the zero-crossing width and the non-zero-crossing width; and performing phase control depending on the frequency and the voltage value.

Abstract: A phase generator includes a delay element configured to receive an input signal and delay the input signal by a predetermined amount to develop a delayed version of the input signal, a logic element configured to receive the input signal and the delayed version of the input signal, the logic element configured to produce a signal dependent on a phase difference between the input signal and the delayed version of the input signal, a circuit configured to generate a reference signal, and a comparator configured to receive an output of the logic element and the reference signal. The comparator is configured to generate a control signal that is dependent on the difference between the output of the logic element and the reference signal, where the control signal is applied to the delay element to determine the delay applied to the input signal.

Abstract: A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell, while a control circuit (which is generally a current source that is controlled by a control voltage) provides additional delay. Thus, the delay cell provided here can be used to improve the performance of delay locked loops (DLLs) and other circuits.

Abstract: The present invention discloses a cooperation circuit, comprising: a first control module, capable of generating a first control signal and a second control signal, the pulse width of the first control signal being determined by the pulse width of the second control signal; and a second control module, coupled to the first control module to receive the first control signal and the second control signal and generate a third control signal according to the first control signal and the second control signal; wherein, according to the first control signal and the second control signal, the second control module enables the third control signal and the second control signal to exhibit the same frequency and the same duty cycle with a phase delay.

Abstract: A quadrature modulation circuit includes a mixer circuit including an integrated sign modulation control circuit and a plurality of mixer ports. The mixer ports include a first input port, a second input port, an output port and a sign modulation control port. The modulation circuit generates a modulated signal by operation of the mixer circuit multiplying a modulating signal applied to the first input port with a carrier signal applied to the second input port to generate a mixed signal output from the output port, and by operation of the integrated sign modulation control circuit controlling polarity switching of a signal at one of the mixer ports in response to a sign modulation control signal input to the sign modulation control port.

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: An apparatus for scaling a load device with frequency in a phase interpolator can include an analog loop and a digital loop. The load device of the phase interpolator can include a transistor and a plurality of resistors selectively configured in parallel with the transistor. The analog loop controls a resistance of the transistor based on a voltage applied to a control terminal of the transistor. For instance, the analog loop can tune the resistance of a PMOS device by adjusting a voltage applied to the PMOS device's gate terminal. In addition, the analog loop can include a comparator to compare a voltage across the transistor to a reference voltage such that an optimal voltage is maintained for an output swing of the phase interpolator. The analog loop can also include a low pass filter coupled to an output of the comparator to define frequency stability and loop bandwidth of the analog loop.

Abstract: An adaptive electromagnetic interference (EMI) detection and reduction device for multi-port applications is provided. The invention includes at least two physical devices (PHY), where the PHYs transmit data along wire pairs to a register jack (RJ). The transmissions create EMI along the wire pairs, where the transmissions have constructively interfering resonant frequencies having phases and amplitudes. An antenna is disposed proximal to each RJ, where the antennae detect each frequency. A resonating network determines a peak amplitude of each frequency, an envelope detector amplifies each peak amplitude from the resonating network. A discretization circuit converts the amplified peak to discrete amplitude values, where the discretization circuit transmits the discrete amplitude values to a controller.

Abstract: An integrated circuit includes clock deskew circuitry. The deskew circuitry includes multiple loop circuits to align a received clock with a data eye, and to reduce the effects of clock drift caused by voltage and temperature variations. The loop circuits include phase interpolators to produce local clock signals. Local clock signals are provided to seqiuential elements through local clock trees and are also provided to a phase detector through a dummy local clock tree. The operation of the phase interpolators is influenced by the phase detector.

Abstract: One embodiment pertains generally to a method of delaying based on a single clock signal. The method includes providing a first clock signal and generating a second clock signal based on the first clock signal and a third clock signal that is the inverse of the second clock signal. The method also includes generating a unit of delay based the first clock single and generating a half unit of delay based on the first and second clock signal.

Abstract: A clock divider circuit and methods of operating same includes a standard integral clock divider circuit and a phase slip non-integral divider circuit for high granularity non-integral clock division. A multi-phase frequency synthesizer produces a plurality of phases of a clock frequency and applies the multiple phases to the divider circuit of the present invention. In a first embodiment, each phase is applied to a phase slip divider circuit which includes a integral divider portion and a programmable phase slip divider portion which receives the output of the integral division portion. Each phase of the input clock may therefore be divided by a wide variety of integral and non-integral divisors. In a second, simpler embodiment, a multi-phase frequency synthesizer produces a plurality of phases and applies the phases to a single phase slip divider.

Abstract: An oscillator generates an oscillation signal, and a phase shifter outputs a phase shift oscillation signal corresponding to a difference between a frequency of the oscillation signal and a target frequency. A multiplier outputs a multiplied signal corresponding to a multiplied value of the phase shift signal and the oscillation signal, and an error signal generator outputs an error signal according to the multiplied signal. The output frequency of the oscillator is controlled according to the error signal.

Abstract: In the case where the amplitude of the input signal is large, the duty ratio of the signal output from the last stage is greatly changed as compared with the input signal. In the present invention, in order to solve this problem, there is provided a cascade connection type inverter circuit in which the inverters at the odd-number stage is fed back to the input circuit of the inverter at the first stage via an impedance element, the circuit being characterized in that a switching means is connected for supplying to an input circuit of the inverter at the first stage a compensation current for compensating a disparity between the logical threshold value of the inverter at the first stage and the central voltage of the input signal when the voltage generated between the output terminal of the inverter at the first stage and the input terminal thereof exceeds a predetermined threshold value level.

Abstract: An oscillating means having an oscillator outputs a reference clock, and a frequency-dividing means sequentially frequency-dividing the reference clock into a half frequency. A temperature correction data creating means detects a temperature, calculates logical delaying/advancing data for a temperature change, and outputs the logical delaying/advancing data in every predetermined period. A temperature correction data input means receives the delaying/advancing data outputted by the temperature correction data creating means and outputs the logical delaying/advancing data to a logical delaying/advancing means. The logical delaying/advancing means operates a state of the frequency-dividing means in every predetermined period on the basis of the set logical delaying/advancing data to control the period of the frequency-divided output signal of the frequency-dividing means so as to be coincident with a desired period.

Abstract: A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock.

Abstract: A temperature compensation circuit for an IC device delay circuit compensates fluctuations of delay time in the IC device caused by temperature changes. The temperature compensation circuit accurately compensates the temperature even when there exist deviations of electrical characteristics in the circuit components in the IC device delay circuit, such as heat dissipation by a heater. The temperature compensation circuit includes a heater to generate heat to raise temperature of the IC device delay circuit when the heater is on, a flip-flop for turning the heater off when an input signal is provided to an input terminal of the IC device delay circuit and turns the heater on when the input signal returns to the flip-flop after a selected delay time, a plurality of delay elements each having a predetermined delay time for producing delayed signals, and a selector circuit for selecting one of the delayed signals from the delay elements.

Abstract: A control circuit to stop an integrated circuit internal clock includes a signal distribution trace connected to a clock stop pipeline. The signal distribution trace creates a large phase delay signal for a first integrated circuit internal clock cycle which activates the clock stop pipeline, and a small phase delay signal for a final integrated circuit internal clock cycle that deactivates the clock stop pipeline. The clock stop pipeline includes a first circuit component to generate an intermediate stop instruction in response to a clock stop command and the large phase delay signal of the first integrated circuit internal clock cycle. The intermediate stop instruction proceeds through the clock stop pipeline in response to clock cycles following the first clock cycle.

Abstract: A phase shifter using digital counters allows extremely accurate phase shifts. In a parallel circuit arrangement of a number of basic phase shift units, which each includes a dual modulus counter and phase control circuitry for controlling the counter modulus, the outputs of several units are combined in parallel. With the divider ratios of all the dividers of the units consisting of roots of pairwise relatively prime numbers, the total number of phase states is equal to the multiplication of its divider ratios.

Abstract: A self-calibration circuit for sensors and transducers that produce pulse-train outputs of the type having a count-until-disabled counter (250) which counts the number of pulses corresponding to a known value of the sensed or transduced quantity in a variable frequency pulse train during the time that a known number of pulses are counted in a reference pulse train by a frequency divider (210); the count accumulated by the count-until-disabled counter being stored, after accumulation, in a settable-divisor frequency divider (220 or 240) which can provide both calibrated sensor pulse-train outputs and calibration pulse-train outputs having the same frequency as the calibrated sensor pulse-train output at known values of the sensed parameter.

Abstract: A phase shifting circuit has an oscillation circuit. The oscillation circuit is provided with a charging and discharging capacitor at which the oscillation signal is generated. The oscillation signal has a constant level period and a saw tooth wave period. A valve of current flowing through the capacitor is changed in the middle of the saw tooth wave period by an input signal. An output of the phase shifting circuit is phase-shifted by 90.degree. with respect to the input signal.

Abstract: A phase shifter includes first and second single pole double throw switches, a low-pass filter, and a high-pass filter. The first switch has an input terminal and first and second output terminals, and the second switch has first and second input terminals and an output terminal. The low-pass filter is interposed between the first output terminal of the first switch and the first input terminal of the second switch and includes FETs as capacitors. The high-pass filter is interposed between the second output terminal of the first switch and the second input terminal of the second switch and includes a plurality of FETs as capacitors. The input terminal of first switch and the output terminal of the second switch are an input terminal and an output terminal of the phase shifter, respectively. Each of the high-pass filter and the low-pass filter produces two different phase quantities by the on-off switching of the FETs. Therefore, four different phase quantities are obtained in the phase shifter, i.e.

Abstract: A desired value for the yaw velocity or the difference between the wheel speeds of the undriven wheels is determined with the aid of a linear single-track model using the steering angle and the vehicle speed. This desired value is compared with the corresponding actual value and the controlled variable for the adjustment to the engine torque is obtained from the comparison. To avoid unnecessary control operations, the single-track model has connected to its output an all-pass element which matches the phase rotation of the response of the single-track model at high frequencies to that of the vehicle.