Abstract: Embodiments herein describe a self-biased divider for a clock in an integrated circuit. In one embodiment, the clock includes a VCO that generates a clock signal that is output to the self-biased divider. However, because the VCO may generate an analog clocking signal (e.g., a low amplitude sine wave of unknown common mode) to reduce jitter, the amplitude can vary which means it may not sufficiently track CMOS parameters. The clocking signals generated by the self-biased divider are used as feedback signals for DC biasing (or DC leveling). In this manner, the divider is referred to a self-biased divider since signals generated by the divider are used to perform DC biasing/leveling.

Abstract: A system includes a mixer of a phase interpolator. The mixer includes a dynamic load whose output signal is coupled to a subsequent stage of the phase interpolator. The dynamic load is configured to provide an alternating current (AC) signal to the subsequent stage of the phase interpolator as input clock signals. The mixer further includes a static load whose output signal is coupled to the subsequent stage of the phase interpolator in parallel with the respective output signal line of the dynamic load. The static load configured to provide a direct current (DC) signal to the phase interpolator temporarily in replacement of the respective AC signals to prevent output signals of the subsequent stage of the phase interpolator from being unpredictable.

Abstract: A radar system is disclosed for detecting profiles of objects, particularly in a vicinity of a machine work tool. The radar system uses a direct digital synthesiser to generate an intermediate frequency off-set frequency. It also uses an up-converter comprising a quadrature mixer, single-side mixer or complex mixer to add the off-set frequency to the transmitted frequency. It further uses a down-converter in the receive path driven by the off-set frequency as a local oscillator. The radar system enables received information to be transferred to the intermediate frequency. This in turn can be sampled synchronously in such a way as to provide a complex data stream carrying amplitude and phase information. The radar system is implementable with a single transmit channel and a single receive channel.

Abstract: The present invention provides a gate driver on array (GOA) circuit and a display panel, in the GOA circuit, a nth one of GOA units has a pull-up control module, a logical addressing module, a pull-up module, first pull-down module, a second pull-down module, a first pull-down maintenance module connected to a first node, a second pull-down module, a third pull-down module, and a second pull-down maintenance module connected to a third node, and a logical addressing module. The logical addressing module pulls up a potential of a second node potential twice to facilitate increasing a threshold voltage margin.

Abstract: A mixer includes: a VGA (12) configured to amplify one of divided two portions of an input signal at a gain of cos ?; a VGA (13) configured to amplify another one of the divided two portions of the input signal at a gain of sin ?; an IQ generator (15) configured to input an LO wave, and output an LO wave in phase with the input LO wave and an LO wave having a phase difference of 90° with respect to the input LO wave; a mixer (16) configured to input the signal output from the VGA (12) and the LO wave which is output from the IQ generator (15), to output an RF signal; a second mixer (17) configured to input the signal from the VGA (13) and the LO wave which is output from the IQ generator, to output an RF signal; and a combiner (18).

Abstract: A phase interpolator to receive a first and a second input clock with a first and a second input clock edge comprises an interpolating circuit unit comprising: resistors in parallel; for each resistor, a connecting switch to connect and disconnect, as operated in accordance with one of the first and the second input clocks, the resistor to and from a first supply line; and a capacitor in series with the resistors. The phase interpolator allow controlling a partial group of the connecting switches to be operated in accordance with the first input clock, and controlling the rest of the connecting switches to be operated in accordance with the second input clock; and determine the output clock of the phase interpolator on the basis of an output signal of the interpolating circuit unit, defined by the voltage over the capacitor after the second input clock edge.

Abstract: A power amplifier module includes an amplifier that amplifies an input signal and outputs an amplified signal, an emitter follower transistor that supplies a bias signal to the amplifier to control a bias point of the amplifier, and a current source that supplies a control current which changes in accordance with a change in control voltage to a collector of the emitter follower transistor. The current source limits the control current to not greater than an upper limit.

Abstract: A source driver includes an interpolation amplifier configured to generate an interpolation voltage based on a received plurality of input voltages and output the interpolation voltage to a display panel; and an input selector configured to receive a first voltage and a second voltage having a different level from the first voltage, and configured to selectively provide at least one of the first and second voltages as the plurality of input voltages in response to some of the lower bits of pixel data. The interpolation amplifier includes four conductive differential input pairs configured to receive four input voltages from among the plurality of input voltages, respectively. Each of the first differential input pair and third differential input pair comprises a first type transistor. Each of the second differential input pair and fourth differential input pair comprises a second type transistor.

Abstract: Disclosed is an improved approach to implement clock alignments between a test subject and its corresponding controller device. Phase locking is performed for the clocks between the test subject and controller device via a training sequence to obtain the appropriate alignment(s). Alignment logic is included on both the testchip and the controller device to implement alignment.

Abstract: Devices and methods of providing response pulses in response to threat pulses are general described. The threat pulses are detected, identified and validity determined using reprogrammable firmware. Threat pulses are extracted from memory and the amplitude, frequency, phase, length and timing modified to generate a coherent set of superposed response pulses in response to the threat pulses. The modifications are calculated in situ using parameterization, rather than being based on tables. Multiple response pulses in response to different threat pulses are simultaneously generated, combined and transmitted in a single channel. Partial pulse capability and the capability to create a weighted and modulated composition of multiple response pulses is provided.

Abstract: A phase-lock-loop (PLL) circuit includes a reference PLL circuit configured to generate a reference clock signal; a single clock tree circuit, coupled to the reference PLL circuit, and configured to distribute the reference clock signal; and a plurality of designated PLL circuits coupled to the clock tree circuit, wherein the designated PLL circuits are each configured to receive the distributed reference clock signal through the single clock tree circuit and provide a respective clock signal based on the reference clock signal.

Abstract: In one embodiment, an impedance matching network is disclosed that includes a first circuit comprising a first variable component providing a first variable capacitance or inductance, and a second circuit comprising a second variable component providing a second variable capacitance or inductance. Each of the first circuit and the second circuit includes plurality of switching circuits configured to provide the first variable capacitance or inductance and the second variable capacitance or inductance. Each of the plurality of switching circuits includes a diode and a driver circuit configured to switch the diode. The driver circuit includes a first switch, a second switch coupled in series with the first switch, and a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode.

Abstract: A system and method for simulating the radio frequency environment of an aircraft is described. Simulated location data and navigational aid data is used to calculate a digital representation of the radio frequency environment of an airplane at the simulated location. The digital representation of the radio frequency environment is converted into an analog signal and provided to the navigational system of the aircraft.

Abstract: A delay-locked loop circuit and a selection method of unit coarse delay are provided. The delay-locked loop circuit includes a frequency detector and a unit coarse delay selector. The frequency detector receives a reset signal and a clock signal. The frequency detector performs a sampling operation to detect a clock frequency of the clock signal based on a time shift of the reset signal and a sequential delay of the reset signal to generate a plurality of determining signals. The unit coarse delay selector selects one of the plurality of determining signals with an earliest transition time as a selected coarse delay signal to control a timing of the delay-locked loop circuit.

Abstract: This invention relates to analog phase shifters, and more particularly, to analog phase shifters for controlling the phase of an RF signal over a wide range of frequencies with nearly linear phase change. An exemplary phase shifter includes a front end high-low pass filter, a back-end high-low pass filter, and an all-pass filter coupled in series between the two high-low pass filters. At least one of the filters is tunable for controlling the phase of an input signal over a wide range of frequencies. The high-low pass filter comprises low-pass filters as input and output interface for the high-low pass filter to facilitate impedance match for receiving and outputting RF signal.

Abstract: A control method, which is adapted to a phase interpolator configured to generate an output signal based on a current distribution ratio, includes following operations: selecting a first input pair and a second input pair from the phase interpolator; sequentially switching currents associated with the current distribution ratio from the first input pair to flowing through the second input pair, in order to adjust a phase of the output signal to correspond to a first phase interval; and after all of the currents flow through to the second input pair, selecting the second input pair and a third input pair from the phase interpolator, and adjusting the current distribution ratio to correspond the phase of the output signal to a second phase interval, in which the first phase interval and the second phase interval are continuous.

Abstract: A phase shifter includes an input port, a first coupling line connected to the input port, an output port, and a second coupling line connected to the output port and arranged substantially parallel to the first coupling line. The phase shifter also includes a substrate disposed between the first coupling line and the second coupling line, a first variable capacitor disposed on the first coupling line, and a second variable capacitor disposed on the second coupling line. Adjustment of one or more of the variable capacitors causes a phase shift between the input port and the output port.

Abstract: A shift control circuit includes a first limiter circuit, a phase shifter, a first suppressor, and a reducer. The first limiter circuit limits the amplitude of a control target signal input from a microphone, having undergone A-D conversion by an A-D convener, and frequency differentiation by a pre-emphasis circuit, and having the relative intensity of harmonic components increased. The phase shifter performs, for the control target signal having undergone the amplitude limitation, phase shift on the frequency component within a first frequency range. The first suppressor suppresses, for the control target signal having undergone the phase shift, the frequency component equal to or greater than a second threshold. The reducer suppresses, for the control target signal having the suppressed frequency component, the frequency component within a second frequency range, and outputs as an information signal.

Abstract: The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for a CMOS interpolator for an output clock signal with a desirable phase for a high speed serializer/deserializer device. In a specific embodiment, the present invention provides a phase interpolator device that mixes phase-shifted clock signals according to a predetermined weight values at predetermined time intervals. There are other embodiments as well.

Abstract: An impedance converter circuit includes a transformer with a primary coil connected to a power feed port, a phase shifter circuit connected between a secondary coil of the transformer and an antenna port, and a bypass circuit connected between the power feed port and the antenna port. In a high band, an absolute value of impedance of the transformer viewed from the antenna port via the phase shifter circuit is higher than an absolute value of impedance of the bypass circuit. In a low band, the absolute value of the impedance of the transformer viewed from the antenna port via the phase shifter circuit is lower than the absolute value of the impedance of the bypass circuit.

Abstract: A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal.

Abstract: A digital beam-forming network for an array antenna having N>1 antenna ports, to be associated to respective antenna elements, and M?1 beam ports (BP), corresponding to respective antenna beams. The digital beam-forming network comprises a plurality of complex weighting elements interconnected through summing nodes. At least one of the complex weighting elements is connected to either two antenna ports, to be associated with respective antenna elements which are arranged symmetrically with respect to the symmetry axis, or two beam ports corresponding to respective antenna beams pointing toward directions which are symmetrical with respect to the symmetry axis, or both. The digital beam forming network can be a part of an array antenna comprising N antenna elements, NS of which are arranged according to an array pattern having a symmetry axis, NS being an even integer different from zero.

Abstract: Systems and methods disclosed herein provide for a fractional feedback divider with reduced jitter at the output without increasing the input clock frequency and with minimal power increase. Embodiments of the system provide for interpolating, with a multiplexer, different output clock signals depending on whether an extra half period of resolution from the input clock is needed for a certain output clock cycle.

Abstract: A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.

Abstract: An electronic circuit includes an adaptive delay circuit and a test circuit. The adaptive delay circuit is configured to receive an input clock signal, to further receive a delay setting that specifies first and second delays, and to generate first and second delayed versions of the input clock signal that are delayed relative to the input clock signal by the first and second delays, respectively. The test circuit is configured to test the adaptive delay circuit by (i) programming the adaptive delay circuit with multiple different delay settings that each specifies a respective first delay and a respective second delay, (ii) for each of the multiple delay settings, measuring an actual time offset between the first and second delayed versions of the input clock signal, and (iii) generating a test result based on actual time offsets measured for the multiple different delay settings.

Abstract: A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.

Abstract: An electronic device includes: a voltage controlled delay line including delay elements configured to delay an input clock signal and output the clock signal, a delay control element configured to control a delay time of the clock signal delayed by the delay elements in accordance with a control voltage, a delay sensitivity adjustment circuit configured to adjust a ratio of an amount of change of the delay time to an amount of change of the control voltage, and a plurality of delay circuits; and a control voltage generation circuit configured to compare a phase of an output signal of any one of the plurality of delay circuits and a phase of the clock signal, generate the control voltage so as to match the phase of the output signal and the phase of the clock signal based on the comparison result, and output the control voltage to the delay control element.

Abstract: A circuit including and a method utilizing an improved bootstrap topology provide power to a high side (HS) driver for high efficiency applications. The improved bootstrap topology includes a transfer capacitor to store charge and to recharge a bootstrap capacitor, which provides power to the HS driver. The improved bootstrap topology also includes a resistor connected to the transfer capacitor to charge the transfer capacitor from a voltage source and to isolate the transfer capacitor from high voltage pulses.

Abstract: A phase control circuit comprising a differential current generator having a differential output node configured to provide a differential drive current and a current conversion circuit connected to the differential output node configured to receive the differential drive current through saturated input Field-Effect Transistors (FETs), the saturated input FETs connected to triode mirroring FETs, the triode mirroring FETs configured to generate linearized current drive signals through first and second output drive nodes to drive a phase interpolator circuit.

Abstract: Testing I/O (input/output) eye width for an interface with an inverted modulated strobe or clock signal. An I/O interface includes multiple signal lines, each with a hardware I/O buffer with timing characteristics. A system generates a strobe signal with a triggering edge that triggers a write, and a trailing edge that is modulated by adjusting the duty cycle of the strobe signal. The system inverts the modulated strobe signal to generate an inverted strobe signal, wherein the inverted strobe signal has a modulated triggering edge generated from inverting the modulated trailing edge. The device under test writes test data based on the triggering edge of the original strobe signal and reads test data based on the triggering edge of the inverted strobe signal.

Abstract: A bicycle operating system comprises an operating device. The operating device is configured to be mounted to a bicycle body. The operating device includes an operating switch, a signal controller, and a wireless transmitter. The signal controller is configured to generate a pairing demand signal in response to an input operation of the operating switch. The wireless transmitter is configured to wirelessly transmit the pairing demand signal to a bicycle component to establish a wireless communication with the bicycle component.

Abstract: A phase control circuit includes: a phase interpolation circuit including a first transistor connected between a power source and an output terminal, and configured to output an output signal from the output terminal by combining input signals having different phases with each other based on a ratio of input bias currents; a bias circuit configured to control an ON-resistance of the first transistor by adjusting a gate voltage of the first transistor based on a total amount of the input bias currents, and to maintain an output common voltage of the phase interpolation circuit regardless of the total amount; and a current controller configured to control a through rate of the output signal with respect to the input signals by adjusting the total amount.

Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range.

Abstract: A modulation system for AM stereo transmission wherein in a combination of amplitude modulation and phase modulation allows a pair of unique audio channel signals to be modulated onto an AM carrier. When a monophonic audio signal is provided, there is no phase modulation present. However, when a first audio signal (e.g., a “right” channel) differs from a second audio signal (e.g., a “left” audio channel), phase modulation occurs simultaneously with amplitude modulation. The modulation system accepts non-matrixed audio signals and produces quadrature modulation compatible with the industry standard C-QUAM system.

Abstract: An electromagnetic interference (EMI) control method to adjust initial clock phases of radiation sources of an electronic device, so as to control EMI of the electronic device. The EMI control method includes determining positions of radiation sources; determining a preset angle of the radiation sources; calculating an initial phase difference by position between the radiation sources according to the positions of the radiation sources and the preset angle of the radiation sources; calculating, according to the initial phase difference by position, determined initial clock phases of the radiation sources when a far-field superimposed field strength is a limiting value; and configuring a phase-adjustable clock driver of the electronic device using the determined initial clock phases, so as to adjust initial clock phases of the radiation sources to the determined initial clock phases.

Abstract: The present disclosure is directed to a system and method for generating an output oscillating signal using an input oscillating signal that is subject to missing pulses and/or distortions. The output oscillating signal can be generated at a desired frequency by a frequency-locked loop (FLL) that uses the input oscillating signal as a reference clock. Because the input oscillating signal is used as a reference clock, missing pulses and/or distortions in the input oscillating signal can adversely affect the continued, stable generation of the output oscillating signal. To this end, the system and method of the present disclosure use an input oscillating signal error detector to open the FLL upon detecting a missing pulse in the input oscillating signal and/or a distortion in the input oscillating signal.

Abstract: System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.

Abstract: A clock phase interpolator includes: a phase interpolation processing circuit configured to generate an interpolated clock signal whose phase is interpolated from a plurality of operation clock signals having different phases; a band adjustment element coupled to the phase interpolation processing circuit, and configured to adjust an operational frequency band of the phase interpolation processing circuit by changing a setting value of itself; and a control circuit coupled to the phase interpolation processing circuit, and configured to detect a transition state for a reference clock signal of the interpolated clock signal, and configured to control the setting value of the band adjustment element on the basis of the detected transition state.

Abstract: Circuits and related methods for artificial ramp generation for pulse-width modulators (PWM) for current control mode switch mode power supplies (SMPS) are disclosed. The artificial ramp generation is separated from a current sensing part and allows easy trimming of both paths. Artificial ramp is generated as a voltage on a capacitor biased by constant current and placed between a voltage sensing node and an input of a PWM comparator. The circuit disclosed reduces circuit complexity and susceptibility to noise and spikes from the input voltage.

Abstract: Circuits, architectures, a system and methods for providing quadrature output signals. The circuit generally includes a quadrature signal generator and a plurality of frequency dividers. The plurality of frequency dividers are each configured to receive a plurality of quadrature signal generator outputs at a first frequency and provide a plurality of outputs at a second frequency. The method generally includes providing a plurality of quadrature signals at a first frequency and dividing the first frequency of the quadrature signals by n, wherein n is an odd integer of at least 3, thereby providing a plurality of divided-by-n quadrature outputs at a second frequency, wherein the second frequency is about equal to the first frequency divided by n. The present disclosure further advantageously improves quadrature signal generation accuracy, reliability and/or performance.

Abstract: Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the dock signals output from the push-pull buffers.

Abstract: A phase compensation circuit includes: a first circuit that increases phase characteristic of a specific frequency of an electrical signal; a second circuit that decreases the phase characteristic of the specific frequency of the electrical signal; and a limiting amplifier that amplifies an electrical signal that is processed by at least one of the first circuit and the second circuit.

Abstract: Digital signals with higher resolution are generated from dual-phase encode signals indicating phase changes of a position or an angle of a target. A signal processing apparatus for processing dual-phase encode signals indicating changes in position of a target, comprises: a first noise reduction unit configured to remove high frequency noise from each of the dual-phase encode signals before interpolation processing; an interpolating unit configured to apply interpolation processing to the dual-phase encode signals output from the first noise reduction unit to generate dual-phase encode signals with higher resolution; and a second noise reduction unit configured to remove noise from the dual-phase encode signals output from the interpolating unit.

Abstract: Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.

Abstract: A digital delay interpolator may include an array of multiplexers, each multiplexer configured to be input with first and second input voltages, one of the first and second input voltages being delayed in respect to the other, and receive a respective selection signal. The digital delay interpolator may include output lines respectively coupled to the array of multiplexers, and an output terminal configured to be coupled in common to the output lines. Each multiplexer may be configured to selectively output on the respective output line one of the first and the second input voltages based upon a logic value of the respective selection signal.

Abstract: A phase interpolator includes an adaptively biased phase mixer, phase control circuitry and an adaptive bias generator. The adaptively biased phase mixer has mixing transistor circuitry configured to provide an output phase signal in response to a plurality of phase control signals, a bias current, and a number of phase input signals offset in phase from one another. The adaptively biased phase mixer further has adjustable bias transistor circuitry configured to adjust the bias current provided to the mixing transistor circuitry in response to an adaptive bias signal.

Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

Abstract: The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed.

Abstract: A first phase alignment circuit generates an indication of a phase of a first clock signal. A second phase alignment circuit adjusts a phase of a second clock signal based on a data signal. The second phase alignment circuit adjusts the phase of the second clock signal based on the indication of the phase of the first clock signal. The second phase alignment circuit resets an indication of the phase of the second clock signal generated based on the data signal in response to the indication of the phase of the first clock signal. The second phase alignment circuit captures a value of the data signal in response to the second clock signal.

Abstract: Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1.