Abstract: A system includes a first tracking filter configured to track a frequency domain mismatch profile between component analog-to-digital convertors (ADCs) of an interleaved ADC (IADC), and a second tracking filter configured to a track a frequency independent timing delay mismatch and a timing delay mismatch correction error based on frequency domain mismatch profile estimates. An output of the first tracking filter determines a correction of a frequency dependent mismatch profile in an output of the interleaved ADC and an output of the second tracking filter determines a correction of the timing delay mismatch correction error in the output of the interleaved ADC.

Abstract: It is presented a signal generator for providing a first signal on a first output and a second signal on a second output wherein the first signal and the second signal are provided with phase shift relative to each other. The signal generator comprises: a control loop controller; a comparator; a phase shifter, the phase shifter being arranged to provide the first signal on the first output and the second signal on the second output; and a phase error detector, the inputs of which are connected to the outputs of the phase shifter and the output of which is connected to an input of the control loop controller. The output of the control loop controller is connected in a feedback loop to a first input of the comparator, and a second input of the comparator is arranged to be connected to an alternating current source.

Abstract: An input/output (“I/O”) port control system is provided. The system can include an I/O controller (110) comprising a power input (115) and an operably connected I/O interface (120). A power supply (150) and switch (130) can be operably connected to the power input. A detector (140) can be operably connected to the I/O interface and to the switch. The detector can be adapted to close the switch when an electrical circuit is completed through the I/O interface.

Abstract: A method for performing phase shift control in an electronic device and an associated apparatus are provided, where the method includes: obtaining a set of clock signals corresponding to a set of phases; and controlling a phase shift of an output signal of an oscillator by selectively mixing the set of clock signals into the oscillator according to a set of digital control signals, wherein the phase shift corresponds to the set of digital control signals, and the set of digital control signals carries a set of digital weightings for selectively mixing the set of clock signals. More particularly, the method may include: selectively mixing the set of clock signals into a specific stage of a plurality of stages of the oscillator according to the set of digital control signals.

Abstract: Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.

Abstract: Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals are disclosed. One such phase mixer includes a phase mixer circuit having inputs and an output. The phase mixer is configured to receive a plurality of input clock signals and generate an output clock signal at the output having a phase relative to the plurality of input clock signals. The phase mixer further includes an adjustment circuit coupled to the phase mixer circuit. In some phase mixers, a control circuit coupled to the phase mixer circuit and the adjustment circuit is included. The control circuit is configured to generate a control signal based on the input signals to adjust an electrical load-to-drive ratio of the phase mixer.

Abstract: Multi-protocol driver slew rate calibration systems for calibrating slew rate control signal values are provided. Embodiments include generating, by a first phase rotator, a first clock signal; generating, by the second phase rotator, a second clock signal; initially setting, by a calibration controller, phase selector amounts such that the first clock signal is delayed relative to the second clock signal; determining whether the first clock signal is delayed relative to the second clock signal; if the first clock signal is delayed, changing the second phase selector amount; and if the first clock signal is not delayed, using the first clock signal and the second clock signal to calibrate values of control signals provided to control a slew rate of a calibration clock delay line such that the slew rate of the calibration clock delay line substantially matches a target slew rate.

Abstract: A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.

Abstract: A phase adjustment apparatus for providing a clock signal to a core circuit is provided. The core circuit is powered by a core voltage. The phase adjustment apparatus includes two clock receiving ends, a plurality of digital receiving ends and a combination circuit. The two clock receiving ends receive two original clocks having a same frequency while the two original clock signals possess different phases. The digital receiving ends receive a plurality of phase selection signals. The synthesizing circuit is powered by a first voltage lower than the core voltage, and generates the clock signal according to the phase control signals and the two original clock signals.

Abstract: A digital phase detector circuit and corresponding monitor and control logic is presented. The digital phase detector has two storage elements, where the data input of the first storage element receives a first clock signal and the data input of the second storage element receives a second clock signal. A time shifter shifts the second clock signal by a shift period, and transmits the shifted signal to the clock input of the storage elements. The signals applied to the data inputs are transmitted from the storage elements when the clock input receives the shifted second clock signal from the time shifter. A monitor and control module samples the data output from the storage elements after each shifted second clock signal is transmitted by the time shifter. The sampling of the output data provides the data used to determine the time relationship between the first and the second clock signals.

Abstract: A control system for a phase generator including a delay block including delay units, and first and second multiplexers configured to receive output signals of each of the delay units and to respectively supply first and second output signals. The control system may include a controller configured to drive the first multiplexer and the second multiplexer respectively with a first select signal and a second select signal, a detection module configured to detect a phase difference between the first output signal and the second output signal and to generate a corresponding digital phase shift signal, the detection module including a phase comparator, and a Time-Digital converter circuit coupled thereto and having logic elements configured to generate the digital phase shift signal, and a logic circuit connected to the detection module and configured to process the digital phase shift signal and to generate a signal indicative of a control executed.

Abstract: A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals.

Abstract: An electronic circuit for distributing a clock signal to several clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; loop filters for generating and transmitting respective DC voltage feedback signals; current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals to adjust the phase shift of the clock signal for the respective one of the clock destinations.

Abstract: The multiphase clock generation circuit includes a variable slew rate circuit and a phase interpolation circuit. In the variable slew rate circuit, the slew rate varies according to a first control signal. Two reference clocks having a phase difference of 90° from each other are supplied to the phase interpolation circuit via the variable slew rate circuit. The phase interpolation circuit interpolates the two reference clocks having a phase difference of 90° from each other according to a second control signal to thereby generate an output clock having an intermediate phase.

Abstract: A signal processing circuit includes: a phase modulating path arranged to adjust a phase component of an input signal to generate an adjusted phase component such that a phase difference of the input signal falls within a target phase difference range; and an amplitude modulating path arranged to exchange a sign of an amplitude component of the input signal corresponding to the phase component to generate an adjusted amplitude component when the phase modulating path adjusts the phase component.

Abstract: A phase rotator includes a phase selector stage operative to receive a clock signal and output a first phase and a second phase of the clock signal, a slew rate control stage including a first pass gate circuit operative to control a slew rate of the first phase of the clock signal and a second pass gate circuit operative to control a slew rate of the second phase of the clock signal, and a phase blending stage operative to combine the first phase with the second phase of the clock signal and output a phase rotated signal.

Abstract: Phase mixers, clock signal generators, memories and methods for providing an output signal having a phase relative to the phase difference of input clock signals are disclosed. One such phase mixer includes a phase mixer circuit having inputs and an output. The phase mixer is configured to receive a plurality of input clock signals and generate an output clock signal at the output having a phase relative to the plurality of input clock signals. The phase mixer further includes an adjustment circuit coupled to the phase mixer circuit. In some phase mixers, a control circuit coupled to the phase mixer circuit and the adjustment circuit is included. The control circuit is configured to generate a control signal based on the input signals to adjust an electrical load-to-drive ratio of the phase mixer.

Abstract: A method, system and device for eliminating intra-pair skew are disclosed. The method includes: measuring a phase difference between the received differential signals as a transmission delay difference; and compensating delays of the differential signals using the transmission delay difference, to eliminate intra-pair skew of the differential signals. A phase difference measuring apparatus is used to measure a phase difference between the differential signals as the transmission delay difference, so that the transmission delay difference may be adjusted according to the phase difference. Therefore, the procedure for eliminating intra-pair skew is effectively simplified, and the effect of adjusting the transmission delay difference is improved.

Abstract: The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, switching on of a switching transistor of source current and switching off of the switching transistor of sink current; and iii) following detection of an edge of another reference signal at a point in time about midway between the first edge and a next similar edge of the reference clock signal has past, switching off of the switching transistor of source current while maintaining the switching transistor of sink current switched off.

Abstract: A double-balanced sinusoidal mixing phase interpolator circuit comprises: a double-balanced gain stage having a first input for receiving a first phasor clock, a second input for receiving a second phasor clock, and a phase interpolator (PI) output, wherein the double-balance gain stage includes (i) a first gain stage having a positive input side and a negative input side for the first phasor clock and (ii) a second gain stage having a positive input side and a negative input side for the second phasor clock; and a sinusoidal digital-to-analog (DAC) stage coupled to the double-balanced gain stage and configured to implement sinusoidal weighting of positive and negative sides of differential DAC current for the first phasor clock and positive and negative sides of differential DAC current for the second phasor clock, wherein the sinusoidal weighting provides uniformly spaced phase steps in the phase interpolator (PI) output.

Abstract: A reference signal is split and input to first and second variable phase shifters 10, 20. The first and second variable phase shifters output to first and second inputs 31, 32 respectively of a phase comparator 30. Initially, the first and second variable phase shifters 10, 20 are preferably set to the same phase. The first and second phase shifters are then aligned, e.g. by adjusting the calibration of one or both of the phase shifters so that the phase comparator 30 indicates that they output the same phase. The phase of the first phase shifter 10 is then adjusted by one step and a phase delay section 60 is placed between the output of the second phase shifter 20 and the second input 32 of the phase comparator 30. The first and second phase shifters 10, 20 are then aligned again.

Abstract: A reference signal is split and input to first and second variable phase shifters 10, 20. The first and second variable phase shifters output to first and second inputs 31, 32 respectively of a phase comparator 30. Initially, the first and second variable phase shifters 10, 20 are preferably set to the same phase. The first and second phase shifters are then aligned, e.g. by adjusting the calibration of one or both of the phase shifters so that the phase comparator 30 indicates that they output the same phase. The phase of the first phase shifter 10 is then adjusted by one step and a phase delay section 60 is placed between the output of the second phase shifter 20 and the second input 32 of the phase comparator 30. The first and second phase shifters 10, 20 are then aligned again.

Abstract: A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation.

Abstract: A transmitter includes a first amplifier to amplify an in-phase oscillator signal to produce an in-phase mixing signal and a second amplifier to amplify a quadrature-phase oscillator signal to produce a quadrature-phase mixing signal. A first mixer mixes the in-phase mixing signal with a first information signal to produce a first output signal. A second mixer mixes the quadrature-phase mixing signal with a second information signal to produce a second output signal. The first output signal and an inverted second output signal are summed to produce a transmitter output signal that includes an image signal caused by a phase imbalance between the in-phase and quadrature-phase mixing signals. An image monitor monitors the image signal and reduces or eliminates the phase imbalance by independently adjusting a phase of the in-phase mixing signal and/or a phase of the quadrature-phase mixing signal. Consequently, a power of the image signal is reduced or eliminated.

Abstract: A method of generating an output signal from an input signal includes a step of generating a set of n signals, n being an integer greater than or equal to 3, by generating a signal for each integer i such that 0?i?(n?1), each signal within the set having the same frequency and approximately equal amplitude and a phase equal to (360/n)i degrees. The method also includes a step of inputting each of the set of n signals to a gate terminal of a corresponding one of a set of n transistors. Each of the transistors has a source terminal electrically connected to a common voltage drain and each of the transistors has a drain terminal electrically connected to a coupling. The coupling is electrically connected to a common voltage source. The output signal at the coupling has a frequency equal to the frequency of the input signal multiplied by n.

Abstract: A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.

Abstract: A phase generator includes a phase-shift enable and disable signal generator connected to configuration bits at its first input and connected to a reset signal at its reset input for generating a control signal; the configuration bits corresponding to the phase shift desired. The phase generator includes a logic signal generation device connected at its control input to the output of the phase-shift enable and disable signal generator and connected to a reset signal at its reset input for providing a phase generating signal; and a feedback element connected between the output of the logic signal generation device and control input of the phase-shift enable and disable signal generator for providing controlled clock signal to the phase-shift enable and disable signal generator.

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: The present invention provides a phase shifter comprising a first multiplier unit that outputs a first output signal obtained by multiplying an input signal input thereto by a multiplication value calculated based upon a first digital control signal also input thereto and specifying a phase shift quantity for the input signal, a second multiplier unit that outputs a second output signal obtained by multiplying an orthogonal input signal input thereto and having a phase perpendicular to the phase of the input signal by a multiplication value calculated based upon a second digital control signal also input thereto and specifying the phase shift quantity, and an adder/subtractor unit that executes addition or subtraction by using the first output signal and the second output signal based upon a third digital control signal corresponding to the phase shift quantity.

Abstract: A programmable delay lock loop system provides a delayed output signal having a programmed delay from an input signal. A phase detector provides a phase delay signal indicative of an actual phase difference between the input signal and the delayed output signal. An accumulator provides a delay command signal as a function of a difference between a commanded delay and the actual phase difference. A programmable phase delay circuit is configured to generate a ramp signal based upon the input signal, to adjust the ramp signal with respect to a threshold level in response to the delay command signal, to generate a trigger signal based upon a comparison of the ramp signal with the threshold level, and to clock the delayed output signal in response to the trigger signal.

Abstract: An automatic calibration scheme is provided, which calibrates the equivalent taps per period ETT/P every time a delay lock loop is used. More specifically, a digital phase shifter is used to measure equivalent taps per period ETT/P. Alternately, the digital phase shifter is used to directly measure the signal delay through a clock phase shifter of the delay lock loop, thereby directly determining the high frequency and low frequency overhead constants.

Abstract: A phase interpolation circuit and method are provided that are capable of operating in a low voltage and capable of generating a substantially exact phase-interpolation signal, where the phase interpolation circuit is configured to output a phase interpolation signal having a phase between phases of at least two input signals and comprises an interpolation unit configured to discharge an output node by a first interpolation control signal in case a first input signal of two input signals having different phases is inputted to the interpolation unit when the output node has been precharged to a power supply voltage level, the interpolation unit additionally discharging the output node by a second interpolation control signal in case of input of a second input signal of the two input signals; a comparison unit for comparing a reference voltage level and a voltage level of the output node of the interpolation unit to output a signal corresponding to the comparison; and a short pulse generation unit for generatin

Abstract: The methods and circuits of the various embodiments of the present invention relate to phase shifting of a generated clock signal. According to one embodiment, a method of phase shifting a clock signal using a delay line is described. The method comprises the steps of coupling a first delay line and a second delay line in series; generating a transition edge using the first delay line; generating an opposite transition edge using the second delay line; and outputting a first phase shifted clock signal based upon the transition edge and the opposite transition edge of the clock signal. A circuit for shifting a clock signal is also disclosed.

Abstract: A phase interpolator generates a phase-interpolated output clock signal Z from two phase-offset input clock signals A and B, where the interpolation angle of the output clock is based on a weight value W. The phase interpolator has A-side and B-side circuitry, each having (1) an array of parallel current mirrors, (2) a block of parallel switches, where each switch is connected in series with a corresponding current mirror, and (3) an encoder that controls the corresponding switches based on the weight value W. The total current through the phase interpolator varies with interpolation angle, such that, for example, the variation in output amplitude with interpolation angle is reduced. In general, individual bit values in weight value W are not used to control individual switches for all interpolation angles.

Abstract: A high speed passband phase modulation apparatus and method are provided. In the phase modulation apparatus, an RF phase shifter modulates a phase of a local signal that is generated in a VCO according to a digital input. The RF phase shifter is controlled by a phase-controlled loop so that a baseband phase shifter is phased locked to a modulation reference signal from the local signal and a reference clock signal according to the digital input. The phase-controlled loop phase-locks using the modulation reference signal so that the phase-modulated signal generated in the RF phase shifter has a phase value according to the digital input.

Abstract: A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.

Abstract: Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.

Abstract: There is provided a shift clock generator for phase-shifting a shift clock by inserting insertion pulses into the shift clock, wherein an insertion pulse generating section has a compensation memory for storing compensation data for calculating a number of insertion pulses to be inserted into the shift clock with respect to a phase difference preset value based on a phase shift amount, a number-of-pulses calculating section for integrating the compensation data stored in an address range of the compensation memory to calculate a number-of-insertion pulses data based on the phase difference preset value and a pulse generating section for generating the insertion pulses based on the number-of-insertion pulses data.

Abstract: A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.

Abstract: Methods of and apparatuses for matching the signal delay, clock timing, frequency response, gain, offset, and/or transfer function of signal pathways in electrical circuits such as, for example, time-interleaved and pipelined circuits using analog-valued floating-gate MOSFETs are disclosed. The methods and apparatuses disclosed are applicable to a variety of circuits, including but not limited to, sample-and-hold or track-and-hold circuits, quadrature mixers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), analog or digital filters, and amplifiers.

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

Abstract: A phase shift control voltage distribution scheme for a phased array utilizes analog voltage-proportional phase shift devices, to which respective input signals are supplied and from which phase-shifted output signals are produced. A voltage supply unit has a plurality of voltage outputs supplying respectively different analog voltages. A switch network coupled between voltage outputs of the multiple voltage supply unit and the voltage control inputs of the plurality of voltage-controlled phase shift elements, is operative to selectively couple any of the different voltages supplied by the multiple voltage supply unit to the voltage control inputs of any of the voltage-controlled phase shift elements.

Abstract: An apparatus comprising a quadrature network, an RF combining circuit and a weighting network. The quadrature network may be configured to generate a first and a second signal in response to an input signal. The RF combining circuit may be configured to generate an output signal comprising the input signal variably phase shifted from a selectable fixed phase starting point in response to the first signal, the second signal and one or more weighting signals. The weighting network may be configured to generate the weighting signals in response to a voltage control signal and one of four possible output selections. The voltage control signal may be configured to control the variable phase shift.

Abstract: A fuse that includes an arc energy reducing coating to reduce arc energy during a short-circuit and/or a full voltage overload current interrupt is described. The fuse includes end conductor elements, and at least one fuse element secured between and making electrical contact with the end conductor elements. An elongate fuse housing, having a passageway extending longitudinally through the housing, extends between the end conductor elements. The fuse element extends through the housing passageway. An arc energy reducing coating at least partially coats each end portion of the fuse element.

Abstract: An oscillator generates an oscillation signal, and a phase shifter outputs a phase shift oscillation signal corresponding to a difference between a frequency of the oscillation signal and a target frequency. A multiplier outputs a multiplied signal corresponding to a multiplied value of the phase shift signal and the oscillation signal, and an error signal generator outputs an error signal according to the multiplied signal. The output frequency of the oscillator is controlled according to the error signal.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: A method of controlling a clock, including the steps of (a) receiving an external clock signal, (b) calculating a first period of time defined as (T1−T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the external clock signal is transmitted through devices generating skew to the external clock signal, (c) stopping the external clock signal to be transmitted by the first period of time, and (d) driving the external clock signal to thereby turn the external clock signal into an internal clock signal. The method makes it possible to detect delay in a clock signal, and generate no delay error inherent to a digital circuit.

Abstract: An apparatus and method for an improved hardware implementation of a digital phase shifter which provides a simplified process for phase correction of digital signals and eliminates the use of a lookup ROM and complex digital Multipliers. The digital phase shifter operates by applying a phase correction to complex digital I/Q samples in separate stages, where each stage performs a phase rotation by an amount specified directly by the binary values of an integer input phase. In one aspect, an apparatus for applying a phase shift to a complex digital signal comprises a plurality of phase shift stages each having a phase shift value associated therewith, whereby each of the plurality of phase shift stages selectively applies the corresponding phase shift value to the complex digital signal.