Abstract: In a circuit provided in a single integrated circuit unit for use in a signal delay device, there is provided with a device in which an input signal is delayed and a plurality of delay signals, each having a different delay period from the input signal, are outputted, and a detector in which a delay signal having a specific relation with the input signal among the plurality of delay signals is detected.

Abstract: In a circuit provided in a single integrated circuit unit for use in a signal delay device, there is provided with a device in which an input signal is delayed and a plurality of delay signals, each having a different delay period from the input signal, are outputted, and a detector in which a delay signal having a specific relation with the input signal among the plurality of delay signals is detected.

Abstract: A first basic clock supplied from outside is delayed by a first delay circuit to generate a second basic clock which is fed to a frequency divider to generate a group of multi-phase clocks, each of which has a clock width equal to an integer number multiple of the clock width of the second basic clock and has a phase delay sequentially by a value equal to an integer number multiple of the clock period of the second basic clock, wherein the (n-1)th multi-phase clock and a nth multi-phase clock neighboring to each other in the phase sequence, and the first basic clock, are fed to a delay generating circuit as inputs, which comprises a second delay circuit for delaying the (n-1)th clock in the phase sequence, and a circuit arrangement for generating an output clock phase having a delay time relative to the nth clock, being equal to an smaller value of one half clock width of the first basic clock minus a delay time of the first delay circuit and a delay time of the second delay circuit.