Abstract: Technology is disclosed herein for correcting skew between data signals and a clock signal. In one aspect, a memory system has a delay circuit having delay blocks, with each delay block having one or more inverters. The delay circuit is configured to pass a data signal through either an odd number of the inverters or an even number of the inverters to produce a delayed data signal. The memory system has a skew correction circuit configured to control the number of inverters in the delay circuit through which the data signal is passed in order to correct skew between the data signal and the clock signal. The memory system has a polarity correction circuit configured to invert the data signal in the event that the delay circuit passed the data signal through the odd number of the inverters.

Abstract: A receiving device receives a received signal in which a data signal, modulated by using a phase modulation method, and a pilot signal are time-multiplexed. The receiving device includes a synchronizing circuit that synchronizes the phase of the received signal. The synchronizing circuit extracts a pilot signal from the received signal. The synchronizing circuit estimates a phase error by comparing the extracted pilot signal and a predetermined pattern. The synchronizing circuit conducts phase rotation on constellation points of the received signal in accordance with the reference phase, obtained from the phase error, and the phase in the modulation method related to the received signal. The synchronizing circuit estimates a phase estimate value of the received signal in accordance with the constellation points, on which phase rotation has been conducted. The synchronizing circuit compensates for a phase error of the received signal in accordance with the phase estimate value.

Abstract: A phase detection circuit includes a first sample circuit, a second sample circuit, and a third sample circuit. The first sample circuit may be configured to sample a first signal based on a first phase of a second signal to generate a first sample of the first signal and to output the first sample. The second sample circuit may be configured to sample the first signal based on a second phase of the second signal to generate a second sample of the first signal and to output second sample. The third sample circuit coupled to the first sample circuit and to the second sample circuit. The third sample circuit may be configured to sample the first sample based on a change of the second sample to generate a third sample and to output the third sample.

Abstract: A circuit includes a first circuit, a second circuit and a third circuit. The first circuit is configured to receive a first phase of a clock signal, a second phase of a clock signal and a first control signal. The first circuit is configured to generate a first interpolated phase of a clock signal. The second circuit is configured to receive a third phase of a clock signal, a fourth phase of a clock signal and a second control signal, and generate a second interpolated phase of a clock signal. The third circuit is configured to receive the first interpolated phase of the clock signal and the second interpolated phase of the clock signal, and generate the first control signal. The first control signal dynamically adjusts the first interpolated phase of the clock signal.

Abstract: A phase frequency detector realizes a highly linear conversion from noise-shaped ?? modulation into charge quantities without degradation of phase-locked loop (PLL) phase noise. The phase frequency detector may feature a construction of an Up signal output and a Down signal output, in which the Up signal rises when a divided VCO input rises, an Up signal falls when the divided VCO input falls, a Down signal rises when the divided VCO input rises, and a Down signal falls when a reference input rises. A mode selection input may be utilized for a fast lock-up PLL.

Abstract: A phase excursion/carrier wave frequency excursion compensation device has a signal dividing unit, a preprocessing compensation circuit, post-processing compensation circuits, a signal combination unit, a correction amount calculation unit, and a signal correction unit. The preprocessing compensation circuit and the post-processing compensation circuits calculate a phase compensation amount with respect to the input signal, and output the phase compensation amount, and a compensation circuit output signal such that the input signal can be compensated accordingly. The signal combination unit acquires compensation circuit output signals from the post-processing compensation circuits and, based on order of input to the signal dividing unit, outputs rearranged signals.

Abstract: There is provided a frequency synthesizer capable of improving phase noise. A sinusoidal signal with a frequency set by a frequency setting part is output as a digital signal from a set signal output part, and the digital signal is D/A-converted. A difference between a sinusoidal signal with a frequency corresponding to an output frequency of a voltage controlled oscillating part and a sinusoidal signal output from a D/A converting part is amplified by a differential amplifier, and an amplified signal is input via an A/D converting part to a means for extracting a phase difference between the aforesaid sinusoidal signals. A voltage corresponding to a signal being the result of integration of the phase difference is input as a control voltage to the voltage controlled oscillating part. Then, a gain of the differential amplifier is set larger than a maximum value of phase noise degradation of the A/D converting part, whereby the phase noise degradation of the A/D converting part is cancelled.

Abstract: A method for reducing noise in a frequency synthesizer includes selecting a design variable k, calibrating a feedback time delay (Td), such that Td=kTVCO, where TVCO is the period of the synthesizer output signal. The method further includes estimating an instantaneous quantization error to a number of bits equal to q, defining a reference bias current of Icp/(k2q), where Icp is a charge pump current signal, and applying the estimated instantaneous quantization error to a current array to produce a down modification signal (?I). The current array is biased by the reference bias current. The down modification signal (?I) is summed with the charge pump current signal Icp to modulate a down current portion of the charge pump current signal Icp.

Abstract: A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial data into the plurality of data components in response to a second clock signal generated from the serial data. The transmitter adds at least one dummy bit to the serial data at predetermined intervals. The at least one dummy bit includes information regarding a data type of the plurality of data components.

Abstract: A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.

Abstract: A circuit includes a phase adjustment circuit and a dead zone detect circuit. The phase adjustment circuit is operable to receive periodic signals and is operable to provide one of the periodic signals as a selected periodic signal based on a phase comparison between a data signal and the selected periodic signal. Each of the periodic signals has a different phase. The dead zone detect circuit is operable to cause the phase adjustment circuit to shift a phase of the selected periodic signal if the dead zone detect circuit determines that the data signal is in a dead zone. The dead zone detect circuit defines the dead zone based on two of the periodic signals. The phase adjustment circuit is operable to adjust a phase range of the dead zone.

Abstract: The present invention relates to a PLL circuit and an associated method that allows the PLL circuit to operate at a higher operating frequency with a wider bandwidth and a better out-band noise suppression. The PLL circuit comprises a delay locked loop (DLL), a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO) and a frequency divider.

Abstract: A Time-to-Digital Converter (TDC) is provided.

Abstract: In one embodiment, a circuit comprises a first inductor-capacitor based voltage-controlled oscillator (LCVCO) generating a first periodic signal with a first frequency and a first phase and a second LCVCO generating a second periodic signal with a second frequency and a second phase, and the second phase is offset relative to the first phase by a 90 degrees offset.

Abstract: Burst mode clock and data recovery (BCDR) circuit and method capable of fast data recovery of passive optical network (PON) traffic. An over-sampled data stream is generated from an input burst data signal and a phase interpolator generates sampling clock signals using a reference clock and phase information. A phase estimation unit (PEU) determines a phase error in the over-sampled data streams; and a phase retrieval unit sets the phase interpolator with the respective phase information of the input burst data signal prior to reception of the input burst data signal.

Abstract: An electronic circuit for distributing a clock signal to several clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; loop filters for generating and transmitting respective DC voltage feedback signals; current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals to adjust the phase shift of the clock signal for the respective one of the clock destinations.

Abstract: A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data.

Abstract: An inter-phase skew detection circuit includes a frequency division circuit that frequency-divides N-phase clocks to be measured at predetermined timings so as to generate N+2 frequency-divided clocks; a phase comparison target clock generation circuit that generates N phase comparison target clocks by using predetermined N frequency-divided clocks among the N+2 frequency-divided clocks; a phase comparison reference clock generation circuit that generates N reference clocks by using the N+2 frequency-divided clocks, in accordance with predetermined combinations between the N+2 frequency-divided clocks and an operation criterion; and a phase comparison circuit that detects respective phase differences between the N phase comparison target clocks and the corresponding N reference clocks.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at a boundary of coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from an input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates a final output clock having a phase between phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract: A phase detection system (100) comprises an input terminal (101), first and second peak detectors (103, 113), an averaging unit (107), an offset unit (122), and a comparator (126). Input terminal (101) is coupled to the first and to the second peak detectors (103, 113) and provides an input signal to phase detection system (100). Averaging unit (107) is coupled between offset unit (122) and both the first peak detector and the second peak detector (103, 113), and generates an intermediate signal. Offset unit (122) is coupled to input terminal (101) and generates two comparable signals by applying a predetermined offset in signal strength to the input signal or the intermediate signal. The comparator (126) is coupled to the offset unit (122) and generates an output signal by comparing the two comparable signals which is indicative of the phase of the input signal.

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract: Phase noise detection systems for a device under test (DUT) are provided that can be embedded within a chip. According to one embodiment, the embedded phase noise detection system can include an active delay line cell, a phase shifter, and a phase detector. The active delay line and phase shifter separately receive the output signal of the DUT. The phase detector can include a double-balanced mixer followed by an active RC filter. The double-balanced mixer receives, as input, the outputs from the active delay line and phase shifter and can produce different dc voltages proportional to the difference from the input phase quadrature. An auto-adjustment circuit can also be included to help the input signal from the phase shifter to the mixer maintain quadrature.

Abstract: A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase error signal for adjusting the clock signal that is generated from a voltage-controlled oscillator. The phase detector includes a positive-edge detector circuit that generates an edge detection signal P to indicate whether data transitions are present in the input data. The phase detector also includes a lead/lag indicator circuit that generates a lead/lag indicator signal T to indicate whether the clock signal is early or late with respect to the input data.

Abstract: In various aspects, ion sources, mass spectrometer systems, and a power supply circuit coupled to a feedback circuit are provided. A power supply is provided that includes at least the power supply circuit and is operable to transfer charge to a load. The feedback circuit is responsive to a DC component of an output voltage supplied by the power supply in a first feedback loop and an AC component of the output voltage in a second feedback loop to produce a feedback signal representative of at least one of: a value of the output voltage before a charge transfer from a capacitor of the power supply to a load; the value of the output voltage during the charge transfer from the capacitor of the power supply to the load; or the value of the output voltage after the charge transfer from the capacitor of the power supply to the load.

Abstract: A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal.

Abstract: A clock and data recovery circuit that tracks the frequency and phase fluctuation of serial data includes a feedback controller for monitoring tracking speed of an extraction clock with respect to the frequency and phase fluctuation of the serial data and applying feedback control to an integrator adaptively and moment to moment, thereby raising the tracking speed of the recovered clock and improving the jitter tolerance characteristic.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract: An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a clock divider generating first and second intermediate signals having edges delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay element delaying the first intermediate signal by a first delay amount; a second delay element delaying the first intermediate signal by a second delay amount; a third delay element delaying the second intermediate signal by a third delay amount; and a fourth delay element delaying the second intermediate signal by a fourth delay amount. The third delay amount is equal to the first delay amount. The fourth delay amount is equal to the second delay amount.

Abstract: Disclosed is a phase shifting circuit that includes a PLL loop in which a reference frequency received is branched into first and second signals. The first signal becomes one input to a phase comparator and the second signal becomes another input to the phase comparator after being shifted in phase via a phase shifter. The output of the phase comparator is supplied to one input terminal of a differential amplifier via a low-pass filter. The amount of phase shift of the phase shifter is controlled by the output signal of the differential amplifier. The amount of phase shift of the phase shifter is decided by a reference voltage applied to another input terminal of the differential amplifier.

Abstract: A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.

Abstract: In various aspects, ion sources, mass spectrometer systems, and a power supply circuit coupled to a feedback circuit are provided. A power supply is provided that includes at least the power supply circuit and is operable to transfer charge to a load. The feedback circuit is responsive to a DC component of an output voltage supplied by the power supply in a first feedback loop and an AC component of the output voltage in a second feedback loop to produce a feedback signal representative of at least one of: a value of the output voltage before a charge transfer from a capacitor of the power supply to a load; the value of the output voltage during the charge transfer from the capacitor of the power supply to the load; or the value of the output voltage after the charge transfer from the capacitor of the power supply to the load.

Abstract: A wireless communications device may include a wireless receiver receiving signals having alternating known and unknown symbol portions over a channel, and a demodulator systolic array. The demodulator systolic array may include a channel estimation module generating respective channel estimates for each unknown symbol portion based upon the known symbol portions. An autocorrelation module may generate autocorrelation matrices based upon the channel estimates. A channel match filter module may generate respective channel matching coefficients for the unknown symbol portions, and a factorization module may divide the autocorrelation matrices into respective upper and lower autocorrelation matrices. A transformation module may transform the channel matching coefficients into upper and lower channel matching coefficients.

Abstract: A wireless communications device may include a wireless receiver for receiving signals comprising alternating known and unknown symbol portions, and a demodulator connected thereto. The demodulator may include a channel estimation module for generating respective channel estimates for a prior unknown symbol portion(s), current unknown symbol portion and for future unknown symbol portion(s). An autocorrelation module may generate autocorrelation matrices for the prior, current and future unknown symbol portions. A channel match filter module may generate respective channel matching coefficients for the prior and current/future unknown symbol portions, and a factorization module may divide the autocorrelation matrices into respective upper and lower autocorrelation matrices. A transformation module may transform the channel matching coefficients into upper and lower channel matching coefficients.

Abstract: A circuit apparatus and method for generating multiphase clocks in a delay lock loop (DLL) at sub-picosecond granularity. The circuit and method of the invention involves locking a number of cycles M in an N stage DLL, e.g., M cycles, where M is an prime number, which results in clock edges in each cycle that are not located at the same phase locations in each of the M cycles. Any of the phase locations from any of the cycles can be used to generate a clock edge for all cycle in the system application. This requires a special technique to “lock” the DLL loop over a M cycle period instead of a one cycle period. The benefit is that it improves the clock placement granularity by a factor of M over the previous art.

Abstract: A high speed passband phase modulation apparatus and method are provided. In the phase modulation apparatus, an RF phase shifter modulates a phase of a local signal that is generated in a VCO according to a digital input. The RF phase shifter is controlled by a phase-controlled loop so that a baseband phase shifter is phased locked to a modulation reference signal from the local signal and a reference clock signal according to the digital input. The phase-controlled loop phase-locks using the modulation reference signal so that the phase-modulated signal generated in the RF phase shifter has a phase value according to the digital input.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: A threshold personalization circuit for a reset or supervisor chip includes personalization fuses, which shift a resistor divider to provide a variety of selectable voltage thresholds. The personalization fuses may provide hundreds of millivolts of adjustment. The threshold personalization circuit further includes trim fuses to fine tune the threshold to within a few millivolts of the target threshold voltage. The threshold personalization circuit includes a test mode to cycle through to a particular personalization trim, such that at prelaser testing the personalized value is found (the fuse blow for personalization is emulated) and then the trim fuse amount can be based on the actual final personalized voltage. This results in very accurate threshold voltages for all personalized values.

Abstract: A polyphase filter for wireless communication systems includes at least two phase splitting filters each having a variable resistance across their respective outputs. The variable resistance can take any suitable form, such as a MOS transistor biased in the linear (triode) region, a bipolar differential pair, or a digitally switchable resistance. The phase adjustment required for a particular filter can be identified and adjusted through either a closed loop system or an open loop system. Adjustment of the variable resistance reduces quadrature error.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: Binary hysteresis comparator circuits, methods, and applications. A binary constant defines a window within which a binary input can change its value without triggering the comparator circuit output signal. An exemplary binary hysteresis comparator circuit includes a comparator circuit, an adder circuit, and a multiplexer circuit. The comparator circuit compares two multi-bit input values. A first comparator input is provided by the multiplexer circuit, which selects either a first value or a second value, depending on the comparator output signal. The first and second values differ by the binary constant, which is added to or subtracted from a multi-bit circuit input value by the adder circuit. An increase (or decrease) of less than the binary constant is ignored. Some embodiments include an optional overflow prevention circuit that prevents the selected value from exceeding predetermined parameters.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse.

Abstract: A half-rate linear phase detector is particularly well-suited to clock data recovery in a serial data interface. The phase detector uses a quadrature clock to process different portions of the incoming data with different phases of the clock. The resulting component signals can be combined to provide the expected UP and DOWN phase detector output control signals. The phase detector output signals are balanced and of uniform width, minimizing oscillator control signal ripple in the clock data recovery circuit, while the linearity of the phase detector makes its output predictable.

Abstract: A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock.

Abstract: A delay locked loop (DLL) is provided that generates an internal clock signal in synchronization with an external clock signal. First through third amplifiers convert the swing width of the external clock signal to a small swing width and re-convert the external clock signal to an external signal level. A basic clock generator generates a plurality of basic clock signals that are progressively shifted apart by a predetermined phase. First through third duty correctors correct the external clock signal, a first internal clock signal, and a second internal clock signal to satisfy 50% duty. First and second mixers generate a first clock signal and a second clock signal which is 90 degrees out-of-phase with the first clock signal. Finally, the first internal clock signal is 90 degrees out-of-phase with the second internal clock signal. Thus, the first internal clock signal is synchronous with the external clock signal.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the vernier being programmable to one of a plurality of timing steps within a delay range and the delay range being determined by a control signal applied to a bias input, the method comprising the steps of selecting a first and second control vernier from the plurality of verniers; programming the first control vernier to a first delay; programming the second control vernier to a second delay; triggering the first and second control verniers together to generate respective first and second delay signals; generating a difference pulse signal having a duty cycle corresponding to a difference between the generated first delay signal and second delay signal; comparing the duty cycle of the pulse signal to a duty cycle of the reference pulse signal to generate a difference signal pulse, the difference signal being coupled to the bias input of the verniers to adjust the delay range such that the duty cycle

Abstract: An apparatus and method for detecting wrinkling of sheets of material is provided. A change in an angle the sheet forms with a reference line can be detected. When the change in the angle exceeds a threshold value, wrinkling of the sheet can be detected. In an exemplary embodiment, ultrasound signals may be used to detect wrinkling. As ultrasound passes through a sheet of material, for example, paper, there is both a phase shift and an amplitude reduction to that ultrasound signal. As the angle of the sheet changes with respect to the ultrasound signal due to wrinkling of the sheet, the phase shift and amplitude of the signal after it passes through the sheet changes. Thus, as the sheet begins to wrinkle, there is a change in the phase shift and amplitude of the signal. These changes can be used to detect the start of a document jam or wrinkling of a sheet of material.

Abstract: The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate voltage which controls the frequency of the MVCO and to generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.

Abstract: A method for determining a digital phase in a signal comprises sampling a reference signal for a low going edge. If the low going edge is not detected the reference signal is sampled again. If low going edge is detected (78) a counter is initialized (70). The reference signal is again sampled if a high going edge is not detected the reference signal is resampled until the high going edge is detected (79). When a high going edge is detected (79) a counter is started (73). A resulting signal is then sampled if the level of the resulting signal is high the resulting signal is sampled until a low going edge is detected (78). If a low going edge is not detected sampling of the resulting signal continues. If a low going edge is detected (78) sampling is continued until a high going edge is detected (79) at which point the counter is stopped (76). The counter updates a register (96).

Abstract: A semiconductor integrated circuit comprises a phase control unit for shifting the phase of an input signal by two or more different fixed phases so as to generate two or more output signals out of phase. A phase detector detects phase differences among the two or more output signals from the phase control unit, and generates one or more correction signals each having a value corresponding to a deviation of one of the detected phase differences from a desired phase difference. The phase detector feeds the one or more correction signals back to the phase control unit so as to make the detected phase differences equal to desired phase differences, respectively.

Abstract: A delay-locked loop (DLL) circuit having a master-slave structure wherein the DLL circuit includes a master delay loop and a slave stage. The master delay loop delays an external clock signal by a predetermined delay time and generates a feedback signal which is phase-synchronized with the external clock signal. The slave stage delays the external clock signal by the predetermined delay time and generates an internal clock signal. The master delay loop includes a phase comparator, a delay controller, a delay part and a compensation delay part. The slave stage includes a low-pass filter and a slave delay part. The master delay loop may have a structure in which a plurality of delay parts are connected in series. According to the DLL circuit, the high frequency phase noise of the internal clock signal can be minimized in a locked state.