Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Abstract: Clock data recovery can be accomplished using a phase change determination circuit that generates, based upon detected phase differences between a capture clock signal and data signal, a delta signal and a delta selection signal. A calculation circuit generates a set of phase interpolation (PI) codes from prior and speculative values of the delta signal. A selection circuit selects, in response to the delta selection signal, between the sets of PI codes, which are provided as an output of the clock data recovery device.

Abstract: A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition Multimedia Interface (HDMI) configuration, one of the processing channels is disabled, and the PLL provides a locked clock signal to the other three processing channels. Each of the other three processing channels adjusts the phase of the locked clock signal to generate a sampling clock signal. In a DisplayPort (DP) configuration, the PLL changes to connect to the phase detecting circuit of one of the four signal processing channels to form an analog clock data recovery (ACDR) circuit to generate a fundamental clock signal. Each of the three other processing channels adjusts the phase of the fundamental clock signal to generate the sampling clock signal.

Abstract: Embodiments are disclosed of an apparatus capable of performing multi-rate synchronous communication between component chips. Each chip may receive a common clock reference signal, and may generate an internal clock signal dependent on the clock reference signal. A clock distribution tree and phase-locked loop may be used to minimize internal clock skew at I/O circuitry at the chip perimeter. Each chip may also generate an internal synchronizing signal that is phase-aligned to the received clock reference signal. Each chip may use its respective synchronizing signal to synchronize multiple clock dividers that provide software-selectable adjusted-frequency clock signals to the I/O cells of the chip. In this way, the adjusted-frequency clock signals of the multiple chips are edge-aligned to the low-skew internal clock signals, and phase-aligned to the common clock reference signal, allowing the I/O cells of the multiple chips to perform synchronous communication at multiple rates with low clock skew.

Abstract: Disclosed are a phase shifter, a wireless communication apparatus, and a phase control method in which power consumption is reduced. A phase shifter includes a 90° step phase shifter (17) and a 45° phase shifter (18) and adds phase information to two baseband signals to be output to an orthogonal modulator. The 90° step phase shifter (17) contributes to adding any one of phases 0°, 90°, 180°, and 270° to the baseband signals according to a first control signal. The 45° phase shifter (18) contributes to adding one of phases 0° and 45° to the baseband signals according to a second control signal. A phase shifter (8) performs replacement of component signals of one of the baseband signals with component signals of the other of the baseband signals and inversion of polarities of the component signals.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: An arrangement is disclosed for offset compensation of a time-interleaved analog-to-digital converter, having a plurality of computing channels and being adapted to convert a signal from an analog domain to a digital domain. The arrangement comprises the time-interleaved analog-to-digital converter, an analog offset estimation and compensation unit adapted to estimate a mean offset for the plurality of computing channels, a digital offset estimation and compensation unit adapted to estimate a residual computing channel specific offset for each of the plurality of computing channels, and offset compensation means. The offset compensation means are adapted to perform offset compensation in the analog domain of each of the plurality of channels based on the estimated mean offset in the analog domain, and to perform offset compensation in the digital domain of each of the plurality of channels based on respective residual computing channel specific offset.

Abstract: In a case where two constant envelope signals corresponding to an input signal are generated through analog signal processing, variation in detection sensitivities of amplitudes of those signals is suppressed. At least one of a mixer (24) for detecting an amplitude of a first intermediate signal S1 and a mixer (26) for detecting an amplitude of a second intermediate signal S2 detects an amplitude of a given reference signal, and sampling hold circuits (36, 38) hold a voltage related to those amplitudes. Then, detection sensitivities of the mixer (24, 26) are corrected based on the held voltage.

Abstract: In a case where two constant envelope signals corresponding to an input signal are generated through analog signal processing, variation in detection sensitivities of amplitudes of those signals is suppressed. At least one of a mixer (24) for detecting an amplitude of a first intermediate signal S1 and a mixer (26) for detecting an amplitude of a second intermediate signal S2 detects an amplitude of a given reference signal, and sampling hold circuits (36, 38) hold a voltage related to those amplitudes. Then, detection sensitivities of the mixer (24, 26) are corrected based on the held voltage.

Abstract: A voltage control circuit is disclosed. A power factor corrector may utilize the control circuit to provide power factor correction for an AC induction motor. An AC induction motor system may combine the power factor correct with an AC induction motor.

Abstract: The present invention provides a phase shifter comprising a first multiplier unit that outputs a first output signal obtained by multiplying an input signal input thereto by a multiplication value calculated based upon a first digital control signal also input thereto and specifying a phase shift quantity for the input signal, a second multiplier unit that outputs a second output signal obtained by multiplying an orthogonal input signal input thereto and having a phase perpendicular to the phase of the input signal by a multiplication value calculated based upon a second digital control signal also input thereto and specifying the phase shift quantity, and an adder/subtracter unit that executes addition or subtraction by using the first output signal and the second output signal based upon a third digital control signal corresponding to the phase shift quantity.

Abstract: Binary hysteresis comparator circuits, methods, and applications. A binary constant defines a window within which a binary input can change its value without triggering the comparator circuit output signal. An exemplary binary hysteresis comparator circuit includes a comparator circuit, an adder circuit, and a multiplexer circuit. The comparator circuit compares two multi-bit input values. A first comparator input is provided by the multiplexer circuit, which selects either a first value or a second value, depending on the comparator output signal. The first and second values differ by the binary constant, which is added to or subtracted from a multi-bit circuit input value by the adder circuit. An increase (or decrease) of less than the binary constant is ignored. Some embodiments include an optional overflow prevention circuit that prevents the selected value from exceeding predetermined parameters.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: The present invention provides for a circuit for programmable stepless clock shifting, consisting of a splitter generating a 0° and a 90° shifted clocks from a reference clock, and an interpolator of the two shifted clocks, which provides at the output the desired pre-set clock phase.

Abstract: A phase-locked loop includes a phase detector which receives an input signal and a first internal periodic signal and provides a phase signal indicative of a phase difference between the input signal and the internal signal. A rotator then receives the phase signal and provides first and second periodic signals each having a frequency that is a function of the phase difference, the first and second periodic signals being 90 degrees out of phase with each other. An interpolator circuit then linearly combines the first and second periodic signals with third and fourth periodic signals to provide the first internal periodic signal. The interpolator circuit may provide a second internal periodic signal that is 90 degrees out of phase relative to the first internal periodic signal. The phase-locked loop may further include a low-pass filter provided between the phase detector and the rotator.

Abstract: In a &pgr;/2 phase shifter, first and second signals and first and second inverted signals are produced based on input signals. The first and second signals have the same amplitude and are out of phase from each other, and the first and second inverted signals respectively correspond to the first and second signals with their respective phases inverted. A first output signal is produced by adding the first signal and the second signal, and a second output signal is produced by adding the first signal and the second inverted signal. Since the first and second signals have the same amplitude, the first output signal and the second output signal respectively correspond to diagonal lines of a rhombus formed by a vector representing the first signal and a vector representing the second signal. Accordingly, the phase difference between the first and second output signals of the &pgr;/2 phase shifter is accurately set to &pgr;/2 even when the phase difference between the first and second signals is not &pgr;/2.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A delay circuit includes a phase vernier having a plurality of logic components. Each logic component includes a selectable injection input capable of adjusting a phase of an input to the phase vernier.

Abstract: A system and method of implementing precision time delays that provides important and novel improvements over prior techniques of implementing time delays by utilizing a new strategy for selecting the values in the sine and cosine lookup tables. Sine and cosine values which result in non-uniform amplitudes enable increased overall accuracy with fewer bits communicated from the look-up tables to the analogue portion of the system. Further, herein is provided the addition of a variable amplitude threshold crossing capability following the combining of the sine and cosine signals. The time delay accuracy of the resulting phase and amplitude hybrid system can be improved either by increasing the number of bits in the sine/cosine phase management section or by increasing the number of bits in the amplitude section. There is provided herein an optimum strategy for choosing the number of bits used in the phase and amplitude sections for the best overall delay accuracy with the fewest overall control bits.

Abstract: A clock divider circuit and methods of operating same includes a standard integral clock divider circuit and a phase slip non-integral divider circuit for high granularity non-integral clock division. A multi-phase frequency synthesizer produces a plurality of phases of a clock frequency and applies the multiple phases to the divider circuit of the present invention. In a first embodiment, each phase is applied to a phase slip divider circuit which includes a integral divider portion and a programmable phase slip divider portion which receives the output of the integral division portion. Each phase of the input clock may therefore be divided by a wide variety of integral and non-integral divisors. In a second, simpler embodiment, a multi-phase frequency synthesizer produces a plurality of phases and applies the phases to a single phase slip divider.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator and separated into rising and falling edges. The edges are adjusted to a desired slope. The adjusted edges and the unadjusted edges are summed and output as multiple clock signals with a desired pulse edge alignment. The clock signals control switches in a manner to reduce signal dependent sampling distortion.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A method and circuit for adjusting clock pulse widths in a high speed sample and hold circuit. A single phase clock signal is input into a pulse discriminator and separated into rising and falling edges. The edges are adjusted to a desired slope. The adjusted edges and the unadjusted edges are summed and output as multiple clock signals with a desired pulse edge alignment. The clock signals control switches in a manner to reduce signal dependent sampling distortion.

Abstract: Sine and cosine weighting functions are applied to phase quadrature versions of an input signal to be phase shifted, and the weighted results are summed to provide a phase shifted output signal with an amplitude which is relatively independent of the phase shift. A weighting circuit comprises two translinear sine shaping circuits having differential current outputs providing weighting signals from input currents supplied thereto, the input currents of the two sine shaping circuits being offset relative to one another so that the differential current outputs of the two sine shaping circuits are provided in accordance with a sine function and a cosine function, respectively, of a control signal.

Abstract: A source (20) provides an input signal (S1) to be phase shifted and a combining circuit (24) concurrently combines first (A), second (B) and third (C) intermediate signals derived from the input signal (S1), and having differing phase shifts (0, −45, +135 deg), to form a phase shifted output signal (S2). A first amplitude controller (34, 38, 30, 32), responsive to a phase control signal (S3) supplied thereto, varies the amplitudes of the second (B) and third (C) intermediate signals in opposite directions (38) for controlling the phase of the phase shifted output signal. Additionally, a further amplitude controller (40, 42) is provided for reducing a tendency for variations in the phase shift control signal (S3) to alter the amplitude of alternating current (FIG. 5) and direct current (FIG. 6) components of the phase shifted output signal (S2).

Abstract: A phase adjusting circuit including an input level adjuster using two detection signals having different phases and adjusting an amplitude of at least one detection signal to a predetermined level and a signal processor for signal processing including at least one of addition and subtraction on the two detection signals after level adjustment to generate a pair of output signals having a phase difference of 90 degrees or a single output signal having a phase difference of 90 degrees with respect to one of the detection signals, and a position measuring apparatus including an output level adjuster, a scaling signal generator, a detector, an A/D converter, and a memory in addition, wherein the position measuring apparatus cancels a phase error so that a signal having a phase difference of 90 degrees can be obtained.

Abstract: A broadband phase-shifting circuit, in particular for an IQ modulator, has two phase-shifting branches connected in parallel, to the input of which is supplied the input signal of which the phase is to be shifted, and which supply at their outputs output signals of which the phase is shifted over a predetermined angle, in particular of 90°. The phase shifter of one phase-shifting branch is controlled depending on the frequency of the input signal in such a way that the phase angle between the two output signals approximately corresponds to the desired value (coarse control), whereas the phase shifter of the other phase-shifting branch is set to the desired phase angle (fine regulation by a phase detector connected between the outputs of the two phase-shifting branches.

Abstract: A gated-delay locked loop that generates an output clock in phase with and having a frequency which is an integer multiple of the frequency of a reference clock. The gated delay-locked loop includes a voltage-controlled gated oscillator having first and second serially connected voltage-controlled delay elements that each introduce a time delay to produce a first delayed clock and the output clock. An S-R flip-flop receives the first delayed clock on its R-input and either the output clock or the reference clock on its S-input to produce a loop clock. The loop clock is provided to the first delay element. A multiplexer selects the reference clock as the S input to the flip-flop once every N cycles, and selects the output clock as the S input the remaining N−1 cycles. A phase detector, a charge pump and a loop filter compare the phase of the output clock to the phase of the reference clock and apply a voltage to the delay elements to correct any phase differences.

Abstract: The present invention is a method and an apparatus for measuring phase differences between signals A and B using an absolute voltage value for each phase difference between .+-.180.degree.. This is accomplished using a third signal C, which is a signal having a phase approximately equal to the average phase between signals A and B. Signals C and A are subsequently amplitude limited and mixed to produce a fourth signal D, which is a signal having associated an absolute voltage value for each degree of phase difference between .+-.180.degree. for signals A and B.

Abstract: A digital filter includes a)--a plurality of means for the sampling (10, 11, 12, 13, 20, 21, 22, 30, 31) with different delays, of an incoming signal (S), and b)--means (7) to carry out a linear combination of samples produced by the said sampling means (10, 11, 12, 13, 20, 21, 22, 30, 31). The filter is characterized in that a sampling frequency (F/2) of at least some of the sampling means (20, 21, 22) which are associated with delays longer than some of the other sampling means (10, 11, 12, 13) is lower than a sampling frequency (F) of said other sampling means.

Abstract: The present invention provides a method of and an apparatus for producing an output signal which is, relative to a periodic input signal, delayed by a predetermined phase angle phi. Initially, the phase angle phi between 0 and 2.pi. is divided by 2.pi. and multiplied by a predetermined positive integer number Z, whereby an integer phase number F between 0 and Z in obtained after rounding. Then, timing-pulse are, beginning with zero, counted between a first and a second input pulse, and an integer relative phase number P is obtained from the number N of the timing-pulses by multiplying by the phase number F, dividing by Z and rounding. Following the second input signal, the timing pulses are, beginning with zero, counted until the relative phase number P in reached. At last, an output pulse is emitted upon reaching the relative phase number P.

Abstract: A frequency converting circuit has a phase divider, a switching circuit, and switching pulse generator. The phase divider divides a phase of a first input signal and outputting m-units of channel signals having a same frequency but different phases shifted 2.pi./m by 2.pi./m radian respectively, where m is a three or more natural number except 2.sup.n (n: a natural number). The m-units of the channel signals are switched by the switching circuit to output switched channel signals. In response to a second input signal having a frequency higher than that of the first input signal, the switching pulse generator generates switching pulse signals, and switches and outputs the m-units of channel signals having different phases shifted 2.pi./m by 2.pi./m radian for each constant period, by controlling the switching circuit based on the switching pulse signals.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier 10 and then subjected to frequency conversion by a frequency converter 50 including: an exclusive OR element 51; a running average generator 52 consisting of a shift register 53 and an adder 54; and a comparator 55. In response to the output of the frequency converter 50, the phase comparator 60 outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator 60 includes: an exclusive OR element 61; an absolute phase shift measurement means 62 consisting of an adder 63 and D flip-flop arrays 64 and 65; and a D flip-flop 66 serving as a phase shift polarity decision means.

Abstract: An oscillator circuit including a current-controlled phase shift circuit and a feedback circuit including a quartz resonator is capable of varying the oscillation frequency in accordance with control current signals. A phase shift circuit included in the current-controlled phase shift circuit includes a first low-pass filter including a resistor and a capacitor, a first buffer amplifier, a second low-pass filter including a resistor and a capacitor, and a second buffer amplifier. The phase shift circuit has a significant gain at any frequency for oscillation. Especially an oscillation circuit implemented by an integrated circuit satisfies the suitable condition in which relative value of resistances and capacitances do not vary.