Abstract: A system for linearized-mixer interference mitigation includes first and second linearized frequency downconverters; a sampling analog interference filtering system that, in order to remove interference in the transmit band, filters the sampled BB transmit signal to generate a cleaned BB transmit signal; an analog interference canceller that transforms the cleaned BB transmit signal to a BB interference cancellation signal; and a first signal coupler that combines the BB interference cancellation signal and the BB receive signal in order to remove a first portion of receive-band interference.

Abstract: An input device is configured to detect signals from of an input object. Examples include acquiring a first signal on a first sensor electrode of the input device; acquiring a second signal on a second sensor electrode of the input device; combining the first signal and the second signal to produce a combined signal; demodulating the combined signal to determine an in-phase component of the combined signal and a quadrature component of the combined signal; and combining the in-phase component and the quadrature component to determine signal magnitude information.

Abstract: Circuits, architectures, a system and methods for providing quadrature output signals. The circuit generally includes a quadrature signal generator and a plurality of frequency dividers. The plurality of frequency dividers are each configured to receive a plurality of quadrature signal generator outputs at a first frequency and provide a plurality of outputs at a second frequency. The method generally includes providing a plurality of quadrature signals at a first frequency and dividing the first frequency of the quadrature signals by n, wherein n is an odd integer of at least 3, thereby providing a plurality of divided-by-n quadrature outputs at a second frequency, wherein the second frequency is about equal to the first frequency divided by n. The present disclosure further advantageously improves quadrature signal generation accuracy, reliability and/or performance.

Abstract: An apparatus comprising a frequency divider comprising a first latch configured to receive a first clock signal and a complement of the first clock signal and to generate a first latch first output, and a second latch coupled to the first latch in a toggle-flop configuration, a first output circuit comprising a p-channel transistor, wherein the gate of a p-channel transistor is configured to receive the first clock signal, and a n-channel transistor, wherein the drain of the p-channel transistor is directly connected to the drain of a n-channel transistor, wherein the gate of the n-channel transistor is configured to receive the first latch first output, wherein the source of the n-channel transistor is configured to receive the complement of the first clock signal, and wherein the first output circuit is configured to generate an in-phase reference signal, and a second output circuit configured to generate a quadrature signal.

Abstract: An automatic quadrature network with amplitude and phase detection produces quadrature signals for an input oscillator signal, the quadrature signals being equal in amplitude and having ideal quadrature phase between them. An RC circuit provides one quadrature path, and a CR circuit provides another quadrature path. The outputs from the RC/CR circuits are amplitude detected to produce an amplitude control signal. The outputs also are amplitude limited, and the phase between the limiter outputs is detected to produce a phase control signal. The amplitude and phase control signals are combined to generate respective control signals for the RC/CR circuits to automatically align them so that the quadrature signals are of equal amplitude and ideal quadrature phase.

Abstract: An apparatus for dividing a frequency by 1.5 to produce a quadrature signal is disclosed. The apparatus includes a divider that receives a differential input signal with a first frequency and two phases and creates a six-phase signal at a second frequency. The second frequency is the first frequency divided by 3. The apparatus also includes precision phase rotation circuitry that receives the six-phase signal and produces an eight-phase signal. The apparatus also includes a doubler that receives the eight-phase signal and produces a quadrature signal. The quadrature signal has a third frequency that is the first frequency divided by 1.5.

Abstract: High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

Abstract: A 0-to-90-degree phase shifter (13) includes a voltage-variable power supply (16), a transistor (17), a 90-degree divider (18), gain-variable amplifiers (19) (19-1 and 19-2), and a combiner (20). The 90-degree divider (18) divides an input signal into a signal to which a 90-degree phase is given and a signal to which no phase is given, and outputs the divided signals to the gain-variable amplifiers (19). The gain-variable amplifiers (19) (19-1 and 19-2) output signals whose amplitudes are changed according to a phase control amount to the combiner (20). The combiner (20) combines the signals input from the two gain-variable amplifiers (19) and outputs the combined signal. The impedance between the source and the drain of the transistor connected to the isolation port of the 90-degree divider (18) can be changed as appropriate.

Abstract: A voltage generator (400) includes a resistor ladder including resistors (4000-4008) which divide a supplied voltage to generate a plurality of reference voltages, a resistor (4009) provided between a power supply voltage (VCC) and one terminal of the resistor ladder, and a resistor (4010) provided between a power supply voltage (VEE) and the other terminal of the resistor ladder.

Abstract: A vector sum phase shifter includes a 90° phase shifter (1) which generates an in-phase signal (VINI) and a quadrature signal (VINQ) from an input signal (VIN), a four-quadrant multiplier (2I) which changes the amplitude of the in-phase signal (VINI) based on a control signal (CI), a four-quadrant multiplier (2Q) which changes the amplitude of the quadrature signal (VINQ) based on a control signal (CQ), a combiner (3) which combines the in-phase signal (VINI) and the quadrature signal (VINQ), and a control circuit (4). The control circuit (4) includes a voltage generator which generates a reference voltage, and a differential amplifier which outputs the difference signal between a control voltage (VC) and the reference voltage as the control signal (CI, CQ). The differential amplifier performs an analog operation of converting the control voltage (VC) into the control signal (CI, CQ) similar to a sine wave or a cosine wave.

Abstract: A clock phase shift detector circuit may include a phase detector for generating a phase signal based on a phase difference between first and second clock signals. A current mirror having a first, a second, and a third integrator may be coupled to the phase detector, whereby the first integrator integrates the first clock signal and generates a first voltage, the second integrator integrates the first clock signal and generates a second voltage, and the third integrator integrates the phase signal and generates a third voltage. A first comparator receives the first and the third voltage, and generates a first control signal. A second comparator receives the second and the third voltage, and generates a second control signal. The first and second control signals may detect a change between the phase difference of the first and the second clock signal and an optimized phase difference.

Abstract: The present invention provides an improvement of a 4-quadrant clock phase interpolator design to allow independent rotation of the output clocks in steps of 90°. This feature is useful in clock/data recovery where the 90° “jumps” can be used as a coarse control to re-align the data capture clock to achieve any desired data word alignment and/or receive bus clock alignment. The phase interpolator has a switching circuit comprising a single level of switches; a set of four transistor loads; and a set of four current sources operable to be switched by the switching circuit through to any of the set of four transistor loads.

Abstract: High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors, The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

Abstract: An integrated receiver circuit includes a phase locked loop circuit (21) with a voltage controlled oscillator (VCO) (25) and a quadrature generator circuit (29) which uses hybrid-branch line coupler circuits (27, 28) coupled to buffered VCO outputs, where the hybrid-branch line coupler circuits (27, 28) are tuned by same control voltage (25a) that controls the VCO (25). By replicating the VCO core circuitry in each hybrid-branch line coupler circuit (27, 28) under common control of a control voltage, calibrated quadrature signals are generated that have the same frequency as the phase locked loop circuit (21).

Abstract: This invention deals with an advanced Real-time Grid Monitoring System (RTGMS) suitable for both single-phase and three-phase electric power systems. This invention provides an essential signal processing block to be used as a part of complex systems either focused on supervising and diagnosing power systems or devoted to control power processors interacting with the grid. This invention is based on a new algorithm very suitable for real-time characterization of the grid variables under distorted and unbalanced grid conditions. The main characteristic of this invention is the usage of a frequency-locked loop, based on detecting the grid frequency, for synchronizing to the grid variables. It results in a very robust system response in relation to existing technique based on the phase-angle detection since grid frequency is much more stable variable than the grid voltage/current phase-angle, mainly during grid faults.

Abstract: A voltage generator (400) includes a resistor ladder including resistors (4000-4008) which divide a supplied voltage to generate a plurality of reference voltages, a resistor (4009) provided between a power supply voltage (VCC) and one terminal of the resistor ladder, and a resistor (4010) provided between a power supply voltage (VEE) and the other terminal of the resistor ladder.

Abstract: A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

Abstract: Methods and apparatus are provided for time-balanced switching of multiplexer circuits. An embodiment of the invention includes a transistor chain coupled to the output of the multiplexer circuit. The transistor chain preferably delays transitions that would otherwise occur relatively quickly, to match the timing of transitions that occur relatively slowly. The timing of relatively slow transitions is left unaltered. The invention advantageously allows all selector input transitions to yield a data output transition with a substantially constant delay.

Abstract: Embodiments of the present invention provide a current mode logic circuit, comprising first and second differential switching stages, each stage arranged being arranged to receive a plurality of clock signals, such that the first and second differential switching stages respond to a combination of the plurality of clock signals.

Abstract: A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out, N-bit code values are stored according to a plurality of detected phase differences. A controller shares the N-bit code counter, controls the generation of the N-bit code values according to the plurality of detected phase differences, and controls the storing of the N-bit code values in an allocated space of the storage by use of a multiplexer configured to provide the plurality of detected phase differences to the N-bit code counter, and a demultiplexer configured to store the N-bit code values in the allocated space of the storage.

Abstract: A phase shift circuit that includes two, rather than four, delay chains and corresponding selectors is described. This provides a significant area savings and reduces the intrinsic delay of the phase shift circuit, which is particularly beneficial for embodiments in which there is no intrinsic delay matching. In one implementation, the phase shift circuit includes a first delay circuit and a matching delay circuit. The first delay circuit provides a first delay that includes a first intrinsic delay and a first intentional delay. The delay matching circuit provides a matching delay that matches the first intrinsic delay. In one implementation, the phase shift circuit also includes a second delay circuit to provide a second delay that includes a second intrinsic delay and second intentional delay, where the second intrinsic delay matches the first intrinsic delay and the second intentional delay is half as long as the first intentional delay.

Abstract: A phase shifter includes a phase shifting unit for operating at a timing at which a clock signal becomes equal to or greater than a threshold value and outputting periodic signals having phases shifted by 90 degrees from each other; a DC voltage setting unit for setting a voltage value of a DC component of the clock signal input into the phase shifting means; and a clock signal slope varying unit for varying a slope of a rising edge of the clock signal.

Abstract: An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount.

Abstract: An integrated receiver circuit includes aphase locked loop circuit (21) with a voltage controlled oscillator (VCO) (25) and a quadrature generator circuit (29) which uses hybrid-branch line coupler circuits (27, 28) coupled to buffered VCO outputs, where the hybrid-branch line coupler circuits (27, 28) are tuned by same control voltage (25a) that controls the VCO (25). By replicating the VCO core circuitry in each hybrid-branch line coupler circuit (27, 28) under common control of a control voltage, calibrated quadrature signals are generated that have the same frequency as the phase locked loop circuit (21).

Abstract: For the purpose of achieving multiplexing of data signals for the channels of more than four in number in the generating of a frequency-divided clock signal using toggle flip-flop circuits (TFF), while avoiding any possible phase shift relationship between generated frequency-divided clock signals attributed to the indefinite initial state posing the inherent problem of the TFF, there is provided a clock generator circuit comprising a plurality of toggle flip-flop circuits connected in series, capable of outputting a pair of frequency-divided clock signals with different phases; and a delay circuit connected to the toggle flip-flop circuit, capable of outputting a clock signal with a phase shifted with respect to the phases of the pair of frequency-divided clock signal phases by delaying either one or both of the pair of frequency-divided clock signals being outputted from the toggle flip-flop circuits.

Abstract: A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of the first feedback circuit, based on the logic level of a first clock signal. The second latch has a second feedback circuit and a second selecting circuit which selects an output signal of the first latch and an output signal of the second feedback circuit based on the inverted logic level in case of the first latch. The first feedback circuit has a third selecting circuit which selects one of an output signal of the first latch and a second data input signal based on the logic level of a second clock signal, and outputs a signal selected by the third selecting circuit to the first selecting circuit.

Abstract: A phase interpolation circuit and method are provided that are capable of operating in a low voltage and capable of generating a substantially exact phase-interpolation signal, where the phase interpolation circuit is configured to output a phase interpolation signal having a phase between phases of at least two input signals and comprises an interpolation unit configured to discharge an output node by a first interpolation control signal in case a first input signal of two input signals having different phases is inputted to the interpolation unit when the output node has been precharged to a power supply voltage level, the interpolation unit additionally discharging the output node by a second interpolation control signal in case of input of a second input signal of the two input signals; a comparison unit for comparing a reference voltage level and a voltage level of the output node of the interpolation unit to output a signal corresponding to the comparison; and a short pulse generation unit for generatin

Abstract: A system and method for implementing an IQ generator includes a master latch that generates an I signal in response to a clock input signal, and a slave latch that generates a Q signal in response to an inverted clock input signal. A master selector is configured to provide a communication path from the master latch to the slave latch, and a slave selector is configured to provide a feedback path from the slave latch to the master latch. The foregoing I and Q signals are output directly from the respective master and slave latches without any intervening electronic circuitry.

Abstract: Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises controllable delay stages arranged in series and dual-edge phase detector circuitry. The dual-edge phase detector circuitry may generate a control signal to adjust the delay provided by the delay stages based on corresponding rising edges and corresponding falling edges of same-state signals operated on by the delay stages. Other circuits, systems, and methods are described.

Abstract: A broad frequency range phase shift circuit is responsive to a radio-frequency signal generated by a radio-frequency source and generates a lagging phase signal and a leading phase signal, 90° out of phase with the lagging phase signal, corresponding to the radio-frequency signal. An operational amplifier has a signal input that receives the radio-frequency signal from the radio-frequency source and generates a low impedance amplified output signal. A series resonant circuit receives the amplified signal from the operational amplifier and shifts the phase of the amplified signal in an amount that approaches 90° as the amplified signal frequency approaches DC to 0° as the amplified signal frequency increases to the cut-off frequency. A transmission line receives the amplified signal from the operational amplifier and has an electrical length substantially equal to one-fourth of a wavelength corresponding to the cut-off frequency.

Abstract: The 90-degree phase shifter of the invention has: a T flip-flop including transistors Q3 to Q6 and Q9 to Q12 that together constitute a dual differential circuit, input transistors Q1 and Q2 that receive at their bases an input signal, and input transistors Q7 and Q8 that receive at their bases a signal complementary to the input signal; variable current sources 14 to 17 connected respectively to the nodes between the individual input transistors and the dual differential circuit; and a 90-degree phase comparator 10 that compares the phase differences between the signals outputted from the T flip-flop to output signals commensurate with the deviations of those phase differences from 90 degrees. The variable current sources 14 to 17 are controlled by signals based on the signals outputted from the 90-degree phase comparator 10. This configuration more surely yields output signals with a phase difference of exactly 90 degrees.

Abstract: In a signal generating circuit SG1, a 90 -degree divider 3 generates, from a local oscillation signal SLO supplied through an input terminal 1, an intermediate reference phase signal ISREF and an intermediate quadrature signal ISQR orthogonal in phase to the intermediate reference phase signal ISREF for output to mixers 6 and 7, respectively. A shifter 4 shifts the phase of the local oscillation signal supplied through an input terminal 2 by a predetermined amount to generate a shift signal SSFT for output through a divider 5 to the mixers 6 and 7. The mixer 6 mixes the input intermediate reference phase signal ISREF and the input shift signal SSFT to generate a reference phase signal SREF. The mixer 7 mixes intermediate quadrature signal ISQR and the input shift signal SSFT to generate a quadrature signal SQR. With this, it is possible to provide a signal generator capable of generating highly-accurate, high-frequency reference phase signals and quadrature signals.

Abstract: The present invention provides for a circuit for programmable stepless clock shifting, consisting of a splitter generating a 0° and a 90° shifted clocks from a reference clock, and an interpolator of the two shifted clocks, which provides at the output the desired pre-set clock phase.

Abstract: The present invention relates to a tunable quadrature phase shifter comprising an input (IN) for inputting an input signal (vin), splitting means (10) for splitting the input signal into two essentially orthogonal first and second signals (i1, i2), adding means (6) for adding said first and second signals (i1, i2), subtracting means (7) for subtracting said first and second signals (i1, i2), a first output (OUT+) for outputting a first output signal (vo1) based on the output signal from said adding means (6), and a second output (OUT?) for outputting a second output signal (vo2) based on the output signal from said subtracting means (7), wherein that said splitting means (10) is provided as an all-pass.

Abstract: A transmit frequency is generated for a transceiver by a controllable oscillator which generates an oscillator frequency, a divider by a factor N, and a mixer stage with a subsequent band filter. Signals with the oscillator frequency and the oscillator frequency divided by the factor N are to the mixer stage to generate an output signal at the transmit frequency.

Abstract: Disclosed is an integrated circuit device in which a 90-degree phase shifter is implemented. The 90-degree phase shifter includes four input capacitors all having equal capacitance and four output capacitors all having equal capacitance. The input capacitors and the output capacitors are alternately arranged in a loop-shape array in plan view. Eight resistors of the 90-degree phase shifter are arranged inside the annular shape in which the capacitors are arranged.

Abstract: The present invention relates to a tunable quadrature phase shifter comprising an input (IN) for inputting an input signal (vin), splitting means (10) for splitting the input signal into two essentially orthogonal first and second signals (i1, i2), adding means (6) for adding said first and second signals (i1, i2), subtracting means (7) for subtracting said first and second signals (i1, i2), a first output (OUT+) for outputting a first output signal (vo1) based on the output signal from said adding means (6), and a second output (OUT−) for outputting a second output signal (vo2) based on the output signal from said subtracting means (7), wherein that said splitting means (10) is provided as an all-pass.

Abstract: A direct conversion receiver having a DC offset eliminating function that eliminates a DC offset component in which an oscillator generates a local frequency signal, A first phase shifter shifts a phase of the local frequency signal from the oscillator by 90°, a first frequency mixer mixes the received radio frequency signal and the local frequency signal from the oscillator, a first low pass filter low-pass filters an output signal of the first frequency mixer, a second phase shifter shifts a phase of the received radio frequency signal by 90°, a second frequency mixer mixes output signals of the first and second phase shifters, a second low pass filter low-pass filters an output signal of the second frequency mixer, a subtracter subtracts an output signal of the second low pass filter, and a DC offset component generated by a direct conversion receiver is eliminated.

Abstract: A system and method of implementing precision time delays that provides important and novel improvements over prior techniques of implementing time delays by utilizing a new strategy for selecting the values in the sine and cosine lookup tables. Sine and cosine values which result in non-uniform amplitudes enable increased overall accuracy with fewer bits communicated from the look-up tables to the analogue portion of the system. Further, herein is provided the addition of a variable amplitude threshold crossing capability following the combining of the sine and cosine signals. The time delay accuracy of the resulting phase and amplitude hybrid system can be improved either by increasing the number of bits in the sine/cosine phase management section or by increasing the number of bits in the amplitude section. There is provided herein an optimum strategy for choosing the number of bits used in the phase and amplitude sections for the best overall delay accuracy with the fewest overall control bits.

Abstract: The polyphase signal generator includes a first delay circuit which adds a first predetermined phase delay to an input signal, a first phase interpolation circuit which generates a first output signal having an output phase prescribed according to a phase difference between the input signal input to one terminal of the first output signal generation unit and a signal input to another terminal of the first output signal generation unit which is output from the delay addition unit, and a second phase interpolation circuit which generates a second output signal having an output phase prescribed according to a phase difference between a signal input to one terminal of the second output signal generation unit which is output from the delay addition unit and an inverted signal of the input signal input to another terminal of the second output signal generation unit.

Abstract: An additional clock is delayed from a master clock by 90 degrees to provide needed additional clock edges during a cycle. The need for the additional clock edges arises from the desire to perform a read and a write in the same clock cycle. The precise delay is achieved through a clock programmable delay that can be updated as the frequency of the master clock may change. The amount of delay is conveniently detected by using two other programmable delays to achieve a 180 degree delay. The 180 degree delay is easily detected using a flip-flop. The programming signal that caused the total of 180 degrees of delay caused 90 degrees per programmable delay. The same programming signal is then coupled to the clock programmable delay to achieve the desired 90 degrees of delay for the additional clock.

Abstract: A frequency multiplier circuit comprises: a source oscillator configured to generate a source oscillator signal using a crystal oscillator; and n frequency multiplier circuits (n is an integer which is 2 or more), each of which includes a 90° phase shifter circuit configured to shift the phase of an input signal by 90°, and a mixer configured to generate a doubled signal of the input signal on the basis of the input signal and an output signal of the 90° phase shifter circuit, wherein the n frequency multiplier circuits are cascade-connected, the source oscillation signal being inputted to a first stage frequency multiplier circuit of the n frequency multiplier circuits, and a final stage frequency multiplier circuit of the n frequency multiplier circuits outputting a signal having a frequency 2n times as high as the frequency of the source oscillation signal.

Abstract: A DC-offset canceller in a receiver of a communication system using a burst signal including a training sequence with a predetermined periodicity at the head thereof is disclosed. In the canceller, a quadrature demodulator 112 converts the received burst signal to a base band signal. An AD converter 113 converts an output signal of the quadrature demodulator to a digital signal. A one-cycle delay element 114 makes a delay of an output signal of the AD converter 113 corresponding to one-cycle of the training sequence. A DC-offset detector 115 detects a DC-offset component in the converted signal by the AD converter 113 on the basis of an output signal of the AD converter 113 and an output signal of the one-cycle delay element 114. A subtractor 116 removes the DC-offset component detected by the DC-offset detector 115 from the output signal of the AD converter 113.

Abstract: There is disclosed a 90-degree phase shifter so configured that an input signal is supplied through a variable gain amplifying circuit and a phase adjusting circuit to a low pass filter and also supplied through another variable gain amplifying circuit and another phase adjusting circuit to a high pass filter, so that the low pass filter and the high pass filter generate output signals, respectively, which have a 90-degree phase difference therebetween. An amplitude error and a phase error between the output signals are detected, so that the variable gain amplifying circuits are gain-controlled by the detected amplitude error, and the phase shift amounts of the phase adjusting circuits are controlled by the detected phase error. Thus, the amplitude error and the phase error attributable to the variation in the device characteristics and the parasite component can be removed, so that it is possible to obtain the output signals having the 90-degree phase difference with no amplitude error and no phase error.

Abstract: A phase adjusting circuit including an input level adjuster using two detection signals having different phases and adjusting an amplitude of at least one detection signal to a predetermined level and a signal processor for signal processing including at least one of addition and subtraction on the two detection signals after level adjustment to generate a pair of output signals having a phase difference of 90 degrees or a single output signal having a phase difference of 90 degrees with respect to one of the detection signals, and a position measuring apparatus including an output level adjuster, a scaling signal generator, a detector, an A/D converter, and a memory in addition, wherein the position measuring apparatus cancels a phase error so that a signal having a phase difference of 90 degrees can be obtained.

Abstract: A 90° phase shift circuit receives an input signal to generate a Q-signal and an I-signal having a phase difference of 90° therebetween. The 90° phase shift circuit has a CR-type high-pass filter having a variable capacitor and fixed resistor, a CR-type low-pass filter having a variable capacitor and a fixed resistor, and a level comparator for comparing the amplitudes of both the outputs from the filters to feed-back a control signal for controlling the cut-off frequencies of both the filters.

Abstract: An approach for demodulating a frequency-modulated signal involves processing a frequency-modulated signal with a phase shifter network to provide a demodulated signal that has a relatively constant amplitude around the center frequency of the frequency-modulated signal and that exhibits a relatively linear phase change over an operational frequency range. Embodiments of the invention include a phase shifter network, using N number of cascaded all-pass filters, that receives as an input a limited amplitude signal and outputs a phase-shifted limited amplitude signal that is mixed with the limited amplitude signal. The phase shifter network may also comprise a low-pass bessel filter.

Abstract: A clock signal generator includes a phase shifter for generating four clock signals having phases consecutively shifted from one another by 90 degrees based on an external clock signal, a mixer for mixing two of the four clock signals to output an internal clock signal, and an initializing circuit for selecting consecutively one and another of the four clock signals as an internal clock signal in an initializing period. A phase comparator compares the internal clock signal against the external clock signal in the initializing period to determine which of the internal clock signal and the external clock signal leads. The initializing circuit reduces the time length for locking of the internal clock signal to the external clock signal in an operational period of the mixer.

Abstract: A phase shift circuit includes a CR phase shifter for receiving an input signal to output a pair of first signals having a 90.degree. phase difference therebetween, a pair of variable-gain amplifiers for receiving the first signals to output a pair of second signals, an adder for adding both the second signals to output a sum signal, a subtracter for outputting a difference signal between the second signals, and a phase error detector for detecting the phase difference between the outputs from the adder and the subtracter to output a pair of gain control signal based on the phase difference. The gain control signal is fed-back to the variable-gain amplifier to control the ratio between the gains of the variable-gain amplifiers.

Abstract: A phase shifting circuit that may be used as part of a quadrature clock generator. The phase shifting circuit comprises a triangle wave generator coupled to receive an input reference signal. The triangle wave generator outputs a pair of complementary triangle wave signals in response to the input reference signal. A comparator having a pair of inputs is coupled to receive the pair of complementary triangle wave signals. The comparator outputs an output signal having a predetermined phase relationship with the input reference signal in response to a comparison between the pair of complementary triangle wave signals.