Abstract: Techniques and apparatus are described for reducing power consumption when performing wireless communications by dynamically changing the frequency of a local oscillator signal for a radio frequency (RF) downconversion circuit, based on signal conditions. An example method includes receiving an RF signal and downconverting the RF signal using an oscillating signal with a first frequency at a first time. The method also includes switching to downconverting the RF signal using the oscillating signal with a second frequency, based on a property associated with the RF signal at a second time. The second frequency is a subharmonic of the first frequency.

Abstract: Octagonal phase rotator apparatus is provided for producing an output signal that is phase dependent on a digital control code. The apparatus includes an I-mixer, a Q-mixer, and first and second IQ-mixers. The I-mixer is responsive to I-control bits of the digital control code. The Q-mixer is responsive to Q-control bits of the digital control code. The first and second IQ-mixers are respectively responsive to one or more IQ1-control bits and one or more IQ2-control bits of the digital control code. The I-mixer comprises an I-DAC for steering current between a positive phase IP and a negative phase IN of an in-phase (I) signal wherein the one or more I-control bits control switching of a first current unit between IP and IN, and a set of amplifiers for weighting the phases IP and IN, in dependence on current steered to each phase by the I-DAC, to produce a weighted I-signal.

Abstract: A power amplifier cell includes a first input arranged to receive an in-phase control signal, a second input arranged to receive a quadrature control signal, an input stage arranged to output a drive signal based at least partly on the received in-phase and quadrature control signals, and an output stage arranged to receive at an input thereof the drive signal output by the input stage, and to generate an output signal for the power amplifier cell in response to the received drive signal.

Abstract: Differential crystal oscillator circuits are disclosed that may provide low-power, low phase noise operation, and prevent latching at low frequency by providing a low impedance DC path using active super diodes.

Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, ?. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various ? values.

Abstract: Methods and apparatuses for high rotation rate low I/O count phase interpolation are disclosed, including techniques to reduce redundant phase interpolation coding and method steps by modifying phase mapping and generation with pluralities of amplifiers. I/O reduction count is achieved while maintaining resolution and allowing scalability in phase interpolation. Control circuits include techniques to interpolate phases at a high rotation rate while reducing discontinuities and risk for logic hazards.

Abstract: A phase splitter includes: a first signal path; and a second signal path, wherein the phase splitter outputs an internal signal of the first signal path as a first phase signal, and mixes an output signal of the first signal path with an output signal of the second signal path, thereby outputting a second phase signal having a predetermined phase difference from the first phase signal.

Abstract: A device may include first, second, and third buffer stages. The device may further include a selector circuit to selectively output one of an output of the second buffer stage or an output of the third buffer stage. The device may include an output to provide a first clock signal, where the first clock signal is an output of the first buffer stage, and the device further include an output to provide a second clock signal, where the second clock signal is an output of the selector circuit.

Abstract: A digital-to-analog conversion apparatus and a current-mode interpolation buffer thereof are provided. The current-mode interpolation buffer comprises a current source, a first differential transistor pair, a second differential transistor pair and an output stage. The current source outputs a first current and draws a second current. Wherein, the amperages of the first current and the second current are dependent on a digital code. First differential transistor pair generates a first differential current according a first rough voltage, an analog voltage and the first current. Second differential transistor pair generates a second differential current according a second rough voltage, the analog voltage and the second current. Output stage generates the analog voltage according to the first differential current and the second differential current, where the analog voltage belongs to a rough range from the first rough voltage to the second rough voltage.

Abstract: A method for generation of high frequency, non-overlapping clocks may include receiving input clock signals at a clock input node of a circuit. Multiple feedback signals may be received at a number of input feedback nodes of the circuit. At a startup node, a startup signal of the circuit may be received, and, in response to receiving the startup signal, an output clock may be generated at a predefined portion of at least one of the received input clock signals. A stable high frequency output clock may be generated at an output stage by utilizing the feedback signals received by the input feedback nodes.

Abstract: Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.

Abstract: An RF system for reducing intermodulation (IM) products is disclosed. The RF system includes a first nonlinear element and a second nonlinear element, wherein the second nonlinear element generates inherent IM products and the first nonlinear element is adapted to generate compensating IM products. Alternatively, the first nonlinear element generates inherent IM products and the second nonlinear element is adapted to generate compensating IM products. The amplitudes of the compensating IM products are substantially equal to amplitudes of the inherent IM products. The RF system further includes a phase shifter that is adapted to provide a phase shift that results in around 180° of phase shift between the inherent IM products and the compensating IM products. The phase shifter is coupled between the first nonlinear element and the second nonlinear element.

Abstract: Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.

Abstract: A system is provided for generating a plurality of different voltage level clock signals. The system comprises an electrical energy storage pack having a plurality of series coupled electrical energy storage cells that provide a plurality of different output voltage level, a reference oscillator that provides a reference clock signal and a plurality of voltage clamps that receive the plurality of different output voltage levels and output the plurality of different voltage level clock signals at respective output nodes. The plurality of voltage clamps are configured to clamp each of a given output node to a respective high-side voltage level in response to pulling up of the given output node toward a respective high output voltage level and to clamp each of the given output node to a respective low-side voltage level in response to pulling down of the output node toward a low output voltage level.

Abstract: The present invention is a controllable input impedance RF mixer, which when fed from a high impedance source, such as a current source, provides a high quality factor (Q) impedance response associated with an impedance peak. The high-Q impedance response may be used as a high-Q RF bandpass filter in a receive path upstream of down conversion, which may improve receiver selectivity and replace surface acoustic wave (SAW) or other RF filters. The present invention uses polyphase reactive circuitry, such as capacitive elements, coupled to the down conversion outputs of an RF mixer. The RF mixer mixes RF input signals with local oscillator signals to translate the impedance of the polyphase reactive circuitry into the RF input impedance of the RF mixer. The RF input impedance includes at least one impedance peak. The local oscillator signals are non-overlapping to maximize the energy transferred to the polyphase reactive circuitry.

Abstract: A voltage comparator includes an input portion, an output portion, and a diverting portion. The input portion accepts a first voltage and a second voltage and then outputs a first current based on the first voltage and outputs a second current based on the second voltage. The output portion outputs a result signal based on a difference between the first current and the second current. The diverting portion is electrically connected to the input portion and diverts a portion of the higher current amongst the first current and the second current.

Abstract: In one illustrative embodiment, an apparatus for a current-mode phase rotator with partial input phase switching comprises a mixer, wherein the mixer is a four quadrant current-mode mixer comprised of four interpolation buffers, wherein each interpolation buffer receives as input a clock phase from a set of four equidistant clock phases, and a set of two-output current-steering digital to analog converters that supply tail currents to the mixer wherein a first digital to analog converter has additional switches to connect each of two outputs to one of two polarities of a given clock while each remaining digital to analog converter has no additional switches and has two outputs supplying current only to two different polarities of a same clock phase wherein steering the current during incremental rotation about a phase circle defines an octagonal shaped phase envelope.

Abstract: Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of delay stages, each of which consists of a single inverting delay device. The inputs and outputs of a selected stage are applied to a phase inverter that inverts one of the signals and applies it to a first input of a phase mixer with the same delay that the other signal is applied to a second input of the phase inverter. The delay of the signals from the selected delay element are delayed from each other by a coarse delay interval, and the phase mixer interpolates within the coarse delay interval by fine delay intervals. A phase detector compares the timing of a signal generated by the phase interpolator to the timing of a reference clock signal applied to the delay line to determine the selected delay stage and a phase interpolation value.

Abstract: The present invention includes a solution to the adherence to and improvement of the specifications regarding the conducted susceptibility of a microwave chain. It has an advantage of enabling significant attenuation of parasitic modulated signals carried in microwave chains of microwave devices such as those that are integrated into satellites by adding one or more 180° phase shifters between the units which do not exhibit a sufficient conducted susceptibility performance. The invention consequently makes it possible to do away with certain elements charged with the attenuation of the parasitic signals generally integrated into the power supplies and other DC/DC converters present in all contemporary microwave equipment.

Abstract: Provided are a digital phase interpolator, which performs linear phase interpolation irrelevantly to input order of two input signals, and a semi-digital delay locked loop (DLL), which includes and controls the same. The phase interpolator includes: a first clocked inverter controlled by a phase indicating signal and providing a first output signal to a common output terminal by inverting a first input signal, and a second clocked inverter controlled by the phase indicating signal and providing a second output signal to the common output terminal by inverting the second input signal. The second clocked inverter is clocked by the first input signal when the phase indicating signal is in a first logic state, and the first clocked inverter is clocked by the second input signal when the phase indicating signal is in a second logic state.

Abstract: Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of delay stages, each of which consists of a single inverting delay device. The inputs and outputs of a selected stage are applied to a phase inverter that inverts one of the signals and applies it to a first input of a phase mixer with the same delay that the other signal is applied to a second input of the phase inverter. The delay of the signals from the selected delay element are delayed from each other by a coarse delay interval, and the phase mixer interpolates within the coarse delay interval by fine delay intervals. A phase detector compares the timing of a signal generated by the phase interpolator to the timing of a reference clock signal applied to the delay line to determine the selected delay stage and a phase interpolation value.

Abstract: In one illustrative embodiment, an apparatus for a current-mode phase rotator with partial input phase switching comprises a mixer, wherein the mixer is a four quadrant current-mode mixer comprised of four interpolation buffers, wherein each interpolation buffer receives as input a clock phase from a set of four equidistant clock phases, and a set of two-output current-steering digital to analog converters that supply tail currents to the mixer wherein a first digital to analog converter has additional switches to connect each of two outputs to one of two polarities of a given clock while each remaining digital to analog converter has no additional switches and has two outputs supplying current only to two different polarities of a same clock phase wherein steering the current during incremental rotation about a phase circle defines an octagonal shaped phase envelope.

Abstract: For the purpose of achieving multiplexing of data signals for the channels of more than four in number in the generating of a frequency-divided clock signal using toggle flip-flop circuits (TFF), while avoiding any possible phase shift relationship between generated frequency-divided clock signals attributed to the indefinite initial state posing the inherent problem of the TFF, there is provided a clock generator circuit comprising a plurality of toggle flip-flop circuits connected in series, capable of outputting a pair of frequency-divided clock signals with different phases; and a delay circuit connected to the toggle flip-flop circuit, capable of outputting a clock signal with a phase shifted with respect to the phases of the pair of frequency-divided clock signal phases by delaying either one or both of the pair of frequency-divided clock signals being outputted from the toggle flip-flop circuits.

Abstract: An inverting cell including a first inverter having first and second inputs; a second inverter having first and second inputs, wherein the second input of the second inverter is connected to the first input of the first inverter and the output of the first and second inverters is connected to the second input of the first inverter; and a third inverter connected between the output of the first and second inverters and the first input of the second inverter.

Abstract: A phase splitter that receives an external clock signal and that generates first and second internal clock signals having a phase difference of 180° between the first and second internal clock signals, the phase splitter including: a first buffer that buffers the external clock signal and outputs a first signal; an inverting unit that inverts the external clock signal and outputs a second signal; a second buffer that buffers the second signal and outputs a third signal; a first interpolating signal generator that inverts the external clock signal and outputs a fourth signal; and a second interpolating signal generator that inverts the second signal and outputs a fifth signal. The first signal and the fifth signal are interpolated to generate the first internal clock signal. The third signal and the fourth signal are interpolated to generate the second internal clock signal.

Abstract: A phase interpolation circuit and method are provided that are capable of operating in a low voltage and capable of generating a substantially exact phase-interpolation signal, where the phase interpolation circuit is configured to output a phase interpolation signal having a phase between phases of at least two input signals and comprises an interpolation unit configured to discharge an output node by a first interpolation control signal in case a first input signal of two input signals having different phases is inputted to the interpolation unit when the output node has been precharged to a power supply voltage level, the interpolation unit additionally discharging the output node by a second interpolation control signal in case of input of a second input signal of the two input signals; a comparison unit for comparing a reference voltage level and a voltage level of the output node of the interpolation unit to output a signal corresponding to the comparison; and a short pulse generation unit for generatin

Abstract: Circuits and methods provide single-ended and differential signals. Single-ended drivers are used to, e.g., reduce pin capacitance. The output cell uses an inversion circuit, such as a phase splitter, to derive the differential signals from the same output signal and provide low skew between the differential signals at the output pins. Selection circuits are used to select between single-ended and differential output.

Abstract: Phase interpolation techniques for voltage-controlled delay line (VCDL) implementation are provided. The techniques of the invention may employ a second-order phase interpolation topology to improve tuning range performance of the VCDL over process and temperature variation. In one aspect of the invention, the technique may use a complementary input signal to set an absolute 180-degree phase reference. As a result, the maximum tuning range of 180 degrees can be achieved regardless of internal delay variation.

Abstract: A clock generating circuit of a semiconductor memory apparatus includes a phase splitter that delays a clock to generate a delayed clock and inverts the clock to generate an inverted clock, and a clock buffer that buffers the delayed clock and the inverted clock and outputs a rising clock and a falling clock.

Abstract: There is provided a clock phase interpolator comprising a pair of output nodes, at least three complementary clock signal inputs, an equal plurality of current sources, and an equal plurality of clock switching sections. Each clock switching section is connected to switch, under the control of a complementary clock signal on a respective one of the complementary clock signal inputs, the current provided by a respective one of the current sources between the two output nodes. The current sources are controllable to provide interpolation between signals on the complementary clock signal inputs. Also provided is a clock phase interpolator comprising a pair of output nodes, two complementary clock signal inputs, an equal plurality of current sources, an equal plurality of clock switching sections.

Abstract: A three-phase voltage-fed AC/DC converter includes a conversion circuit which converts power from a DC voltage source to three-phase AC power. The converter further includes a UM conversion circuit which carries out dq conversion of the three-phase output voltage, a superior voltage control circuit which outputs a voltage reference vector based on a superior reference vector and an output voltage vector obtained by the UM conversion circuit, an inferior voltage control circuit which outputs a PWM reference based on the voltage reference vector and the output voltage vector, and a frequency control circuit which synchronizes a value generated based on a q-axis component from the UM conversion circuit with a rotation angle of a conversion matrix in the UM conversion circuit.

Abstract: A system is provided that includes a power distribution network to provide a switching current and a resonance reduction circuit to sense the switching current within a frequency range and to generate a resonance reduction signal having a current component at substantially a same frequency and substantially 180 degrees out of phase from the sensed switching current. The power distribution network may combine the switching current with the resonance reduction signal to provide a total switching current that may be provided to a processor as the powering signal.

Abstract: A complementary digital signal generator circuit and method receives a periodic digital signal, such as a square wave, as an input and generates at the output complementary versions of the digital signal delayed by matching increments of delay with minimum skew at GHz frequencies. The digital signal is processed by inverters and interpolators which may be readily matched in size and functional characteristics by close proximity placement on integrated circuits. An inverted and first delayed version of the original digital signal is applied to both inputs of a first interpolator, to generate at the output of the interpolator the complement of the digital signal as delayed by the first delayed and the delay introduced by the interpolator. The inverted and first delayed digital signal is inverted and second delayed by a second matching inverter and applied as one input to a second interpolator. The second input of the second interpolator is the original digital signal.

Abstract: A complementary signal generator, for outputting complementary positive-phase and antiphase signals that vary between a first logical value and a second logical value, which includes a signal forming unit for outputting a positive-phase intermediate signal being in phase with an input signal varying between the first logical value and the second logical value, and an antiphase intermediate signal antiphase to the input signal. The generator also includes a first connecting means for simultaneously transferring the second logical value of the positive-phase intermediate signal and the first logical value of the antiphase intermediate signal to a positive-phase signal output part and an antiphase signal output part in synchronism with a state change of the input signal from the first logical value to the second logical value.

Abstract: A phase splitter circuit includes a first signal generator and a second signal generator. The first signal generator generates a first signal in response to an input signal. The second signal generator generates a second signal in response to the input signal. The phase of the first signal is different from that of the first signal. In particular, the phase splitter circuit has a means that is capable of controlling the first and second signals such that transition times thereof are equal. As a result, the phase splitter circuit may fulfill not only delay matching of each element, but also equality of the transition times of output signals.

Abstract: A design for an inverting delay component of an oscillator is disclosed, which enables the oscillator to be more tolerant of parameter variations. This increased parameter variation tolerance allows the KVCO of the oscillator to vary less between the worst case scenario (where the components of the oscillator meet minimum specifications) and the best case scenario (where the components meet the maximum specifications). This in turn means that the worst case KVCO value will be significantly smaller than in the prior art. By using a significantly smaller KVCO value, the jitter experienced at the output of the oscillator will be substantially reduced. Thus, this design enables a low-jitter oscillator to be realized.

Abstract: An active quadrature signal generator produces poly-phase quadrature signals necessary in high frequency transmit and receive elements of a communication system. The quadrature signals are produced using the phase difference between a load representing a low-pass filter characteristic and a load representing a high-pass filter characteristic and the quadrature signal is then used in the differential structure to produce amplified signal having 4 quadrature phases. The device can reduce a loss characteristic of the signal and additional power consumption for compensating for it in a common poly-phase quadrature filter having only conventional resistors and capacitor.

Abstract: A phase splitter is formed by first and second branches that generate respective first and second complimentary output clock signals from an input clock signal. The first branch includes two series connected inverters, the first of which receives the input clock signal and the second of which outputs a non-complimentary output clock signal. The second branch includes three series connected inverters, the first of which receives the input clock signal and the third of which outputs a complimentary output clock signal. An inverter is coupled from the output of the second inverter in the second branch to the output of the first inverter in the first branch to increase the slew rate of the signal applied to the input of the second inverter. In one embodiment, first and second parallel pairs of diode-coupled transistors are coupled from the output of the third inverter in the second branch to the outputs of respective first inverters in the first and second branches.

Abstract: A multiplier circuit is specified, for the multiplication of two input signals, in which two transistor pairs (2, 3; 4, 5) couple a first input (1, 2) to an output (9, 10) of the multiplier, load terminals of the transistor pairs (2, 3; 4, 5) being connected to a second input (15, 16) of the multiplier via a current mirror (11, 12). The differential amplifier usually provided in Gilbert multipliers is thereby obviated, with the result that it is possible to achieve improved noise properties of a transmitter arrangement with vector modulator in which the multipliers can preferably be used.

Abstract: The invention relates to a phase-interpolation circuit and a phase-interpolation signal generating circuit applying the phase-interpolation circuit. The phase-interpolation circuit can avoid short-circuit current effectively. In addition, an inter-phase signal can be interpolated between the rising edge and the falling edge of the clock pulse. The phase-interpolation signal generating device can generate multiphase clock signals which not only have linearly distributed phases but also maintain good 50% duty cycle of the multiphase clock signals.

Abstract: A single-event upset immune flip-flop circuit is disclosed. The single-event upset immune flip-flop circuit includes a first single-event upset immune latch and a second single-event upset immune latch. The first single-event upset immune latch has two inputs and two outputs. The second single-event upset immune latch also has two inputs and two outputs. The two inputs of the second single-event upset immune latch is connected to the two outputs of the first single-event upset immune latch. The state of the first single-event upset immune latch changes only when the signal polarities at both inputs of the first single-event upset immune latch are identical. Similarly, the state of the second single-event upset immune latch changes only when the signal polarities at both inputs of the second single-event upset immune latch are identical.

Abstract: A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit (22 and 24) for receiving an input signal and a symmetry circuits (205 and 210) advantageously configured to provide an output signal exhibiting a symmetrical rising and falling edge waveform in response to the received input signal. An integrated power source (Is) provides current to a common node (N1) in which current is advantageously steered to each half circuit (22, 205 and 24, 210) to reduce voltage variation on the common node during voltage transition of the input signal, hence, reducing current fluctuation from the current source.

Abstract: A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

Abstract: An additional clock is delayed from a master clock by 90 degrees to provide needed additional clock edges during a cycle. The need for the additional clock edges arises from the desire to perform a read and a write in the same clock cycle. The precise delay is achieved through a clock programmable delay that can be updated as the frequency of the master clock may change. The amount of delay is conveniently detected by using two other programmable delays to achieve a 180 degree delay. The 180 degree delay is easily detected using a flip-flop. The programming signal that caused the total of 180 degrees of delay caused 90 degrees per programmable delay. The same programming signal is then coupled to the clock programmable delay to achieve the desired 90 degrees of delay for the additional clock.

Abstract: An apparatus comprising a control circuit and a logic circuit. The control circuit may be configured to receive an input signal and an indication signal and present a complement of the input signal. The logic circuit may be configured to receive the complementary input signal and generate an output signal. The output signal may provide full scale voltages between a first supply (e.g., VSS) and a second supply (e.g., VDD2).

Abstract: A clock splitter device for forming a clock/inverted clock signal pair. The input clock signal is sent through an initial buffer stage and applied to two parts of a second stage. The second stage includes a single stage buffer and constricted inverter to provide two inverted outputs. The transistor arrangement of these two parts provides an equal delay to the two signal paths. The outputs of these two parts are sent to identical output buffers. Because the two paths have identical transistor delays, and since the metal paths on the board are arranged to have identical delays, the two paths can very low skew therebetween.

Abstract: A clock splitter circuit for providing a single event upset (SEU) tolerant clock signal to latches in a space-based environment. The clock splitter circuit can include one or more event offset circuit delay circuits. The event offset delay receives a clock signal and generates a delayed clock signal. The event offset delay circuit can generate an inverted clock signal, a delayed inverted clock signal and a pair of intermediate clock signals. The delayed clock signal and inverted delayed clock signal can be delayed by the known duration of single event effects (SEE). The delayed and undelayed clock signals can be passed to an event blocking filter which can block any disturbance in the delayed and/or undelayed clock signals. A synchronizer can synchronize outputs of the event blocking filter prior to or coincident with being passed to corresponding inverting clock drivers. The synchronizers can also insure that the synchronized blocking filter outputs can not be low simultaneously.

Abstract: A phase splitter is formed by first and second branches that generate respective first and second complimentary output clock signals from an input clock signal. The first branch includes two series connected inverters, the first of which receives the input clock signal and the second of which outputs a non-complimentary output clock signal. The second branch includes three series connected inverters, the first of which receives the input clock signal and the third of which outputs a complimentary output clock signal. An inverter is coupled from the output of the second inverter in the second branch to the output of the first inverter in the first branch to increase the slew rate of the signal applied to the input of the second inverter. In one embodiment, first and second parallel pairs of diode-coupled transistors are coupled from the output of the third inverter in the second branch to the outputs of respective first inverters in the first and second branches.

Abstract: Sine and cosine weighting functions are applied to phase quadrature versions of an input signal to be phase shifted, and the weighted results are summed to provide a phase shifted output signal with an amplitude which is relatively independent of the phase shift. A weighting circuit comprises two translinear sine shaping circuits having differential current outputs providing weighting signals from input currents supplied thereto, the input currents of the two sine shaping circuits being offset relative to one another so that the differential current outputs of the two sine shaping circuits are provided in accordance with a sine function and a cosine function, respectively, of a control signal.

Abstract: A bias circuit (200, FIG. 2) includes a first bipolar junction transistor (BJT) (240), which provides, to an external transistor (204), a biasing voltage (294) equal to the first BJT's base-emitter junction voltage plus a biasing voltage at the first BJT's base (244). A current multiplying mirror circuit (250) senses a fraction of the first BJT's collector current, and produces a current equal to the collector current. This mirror current flows through a second BJT (230). A voltage at the collector (232) of the second BJT is divided, producing the biasing voltage at the base (244) of the first BJT. This biasing voltage has a temperature coefficient with an opposite sign and a same magnitude as a temperature coefficient of the first BJT's base-emitter junction voltage, resulting in a near zero temperature coefficient for the biasing voltage (294).