Having Specific Passive Circuit Element Or Structure (e.g., Rlc Circuit, Etc.) Patents (Class 327/268)
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Patent number: 11423829Abstract: The present disclosure provides a technique for reducing power consumption of circuits generating clocks for driving LEDs.Type: GrantFiled: February 25, 2021Date of Patent: August 23, 2022Assignee: SILICON WORKS CO., LTD.Inventors: Jin Ho Choi, Jang Su Kim, Tae Geun Kim
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Patent number: 8933742Abstract: Time-Mode Signal Processing (TMSP) offers a means for offsetting some of the challenges for analog circuit designs when exploiting CMOS circuit processes designed for digital applications. It would therefore be beneficial to provide a digital method for the storage, addition and subtraction of Time-Mode variables as these offer significant benefit to providing TMSP techniques and expanding their exploitation within devices, systems, and applications. While driven by CMOS process challenges the TM circuits outlined may exploit essentially any digital circuit technology since they are based upon delay. The inventors present an approach to TM variables wherein a switched delay unit is exploited and adopted such that the instantaneous phase difference between two rising signal edges can be latched and used to perform various arithmetic operations. Beneficially, the technique allows analog sampled-data signal processing to be implemented within digital circuitry.Type: GrantFiled: May 9, 2013Date of Patent: January 13, 2015Assignee: The Royal Institution for the Advancement of Learning/McGill UniversityInventors: Gordon Roberts, Mohammad Ali Bakhshian
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Patent number: 8847650Abstract: A method and apparatus for generating a wave shaped pulse electronic signal of a predetermined format from a square pulse signal generator. A signal is applied from the square pulse generator to circuitry having a plurality of transmission lines. Each transmission line having a certain length creating a certain signal time delay and signal reflection for a signal applied to the circuitry from the square pulse generator so as to create a delay pulse from each transmission line. Each delay pulse is combined from each transmission line to generate the wave shaped pulse electronic signal of a desired predetermined format.Type: GrantFiled: May 20, 2013Date of Patent: September 30, 2014Assignee: Hamilton Sundstrand CorporationInventor: Robert D. Klapatch
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Patent number: 8810298Abstract: Circuits and circuit elements configured to generate a random delay, a monostable oscillator, circuits configured to broadcasting repetitive messages wireless systems, and methods for forming such circuits, devices, and systems are disclosed. The present invention advantageously provides relatively low cost delay generating circuitry based on TFT technology in wireless electronics applications, particularly in RFID applications. Such novel, technically simplified, low cost TFT-based delay generating circuitry enables novel wireless circuits, devices and systems, and methods for producing such circuits, devices and systems.Type: GrantFiled: November 24, 2009Date of Patent: August 19, 2014Assignee: Thin Film Electronics ASAInventors: Vivek Subramanian, Mingming Mao, Zhigang Wang
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Patent number: 8624652Abstract: Delay circuits are described for which the delay remains substantially constant within a desired range of variation of supply voltage and/or temperature.Type: GrantFiled: July 18, 2012Date of Patent: January 7, 2014Assignee: SanDisk Technologies Inc.Inventors: Ekram H. Bhuiyan, Steve X. Chi
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Publication number: 20130300483Abstract: Time-Mode Signal Processing (TMSP) offers a means for offsetting some of the challenges for analog circuit designs when exploiting CMOS circuit processes designed for digital applications. It would therefore be beneficial to provide a digital method for the storage, addition and subtraction of Time-Mode variables as these offer significant benefit to providing TMSP techniques and expanding their exploitation within devices, systems, and applications. Whilst driven by CMOS process challenges the TM circuits outlined may exploit essentially any digital circuit technology since they are based upon delay. The inventors present an approach to TM variables wherein a switched delay unit is exploited and adopted such that the instantaneous phase difference between two rising signal edges can be latched and used to perform various arithmetic operations. Beneficially, the technique allows analog sampled-data signal processing to be implemented within digital circuitry.Type: ApplicationFiled: May 9, 2013Publication date: November 14, 2013Applicant: The Royal Institution for the Advancement of Learning / McGill UniversityInventor: The Royal Institution for the Advancement of Learning / McGill University
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Publication number: 20120268183Abstract: An electronic oscillation signal generation circuit includes an electronic oscillation circuit, a DC voltage source for providing a DC voltage to the electronic oscillation circuit, a switch for electrically connecting the electronic oscillation circuit to ground when the switch is turned on so as to generate an analog oscillation signal after the switch is turned off, a conversion circuit for converting the analog oscillation signal to a digital oscillation signal, a counter for generating a control signal when the digital oscillation signal reaches a predetermined number of periods, a delay unit for generating a delay signal a predetermined time after a falling edge of the digital oscillation signal is triggered, and a pulse signal generation circuit electrically connected to the counter and the delay unit for generating a pulse signal according to the control signal and the delay signal so as to turn on the switch.Type: ApplicationFiled: May 27, 2011Publication date: October 25, 2012Inventors: Hsin-Chin Hsu, Fang-Lih Lin
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Patent number: 8264265Abstract: An apparatus and methodology for operating an automatic darkening filter (ADF) eye protection device alternately applies an operating voltage to a pair of control terminals of an ADF device circuit in a continuing sequence, where a first polarity voltage is applied to the pair of terminals and then reversed. A delay period is provided between application of the alternating polarities. In some embodiments ground potential is applied to both terminals of the pair of terminals during the delay period.Type: GrantFiled: September 30, 2010Date of Patent: September 11, 2012Assignee: Kimberly-Clark Worldwide, Inc.Inventors: Donald William Greiner, Thomas Joe Hamilton
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Patent number: 7932764Abstract: A delay circuit has: an inverting receiver with a resistive element, the inverting receiver having an input node for receiving an input signal and an output node coupled to the resistive element; a capacitive element, coupled to the output node of the inverting receiver and the resistive element; a first transistor, having lower turned ON voltage at higher temperature; a second transistor, used for generating a rail to rail signals on a terminal of the first transistor; and an output inverter, having an input node coupled to the first transistor and an output node for outputting an output signal of the delay circuit. Further, a third transistor is used for enhancing pulling low of the output signal of the delay circuit.Type: GrantFiled: December 6, 2007Date of Patent: April 26, 2011Assignee: Elite Semiconductor Memory Technology Inc.Inventor: Min-Chung Chou
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Patent number: 7750709Abstract: One embodiment of the present invention provides a system that biases a floating node within an integrated circuit. During operation, the system first identifies the floating node within the integrated circuit to be biased. The system then determines a desired bias voltage. Next, the system couples a low-power bias source to the floating node to supply the desired bias voltage, wherein the floating node is biased without stopping data transmission through the floating node during biasing.Type: GrantFiled: January 5, 2007Date of Patent: July 6, 2010Assignee: Oracle America, Inc.Inventors: Justin M. Schauer, Robert D. Hopkins
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Patent number: 7746141Abstract: A delay circuit includes a delay time setting circuit to set a delay time of an output signal with respect to an input signal, a first transistor connected to an input terminal of the delay time setting circuit and configured to set a first voltage to the input terminal of the delay time setting circuit and a second transistor connected to an output terminal of the delay time setting circuit and configured to reset the output terminal of the delay time setting circuit to a second voltage and clear the reset of the output terminal of the delay time setting circuit after the first voltage is set.Type: GrantFiled: June 7, 2007Date of Patent: June 29, 2010Assignee: NEC Electronics CorporationInventor: Hiroyuki Takahashi
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Patent number: 7737747Abstract: A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a scheme for controlling transmitter rise-fall transitions (to selectively speed up or slow down transitions) without requiring additional timing controls or affecting reflection coefficient of the transmitter port. The scheme uses at least one pre-charged capacitor, e.g., PMOS capacitor, interacting with the transmitter pad and connected through resistances or otherwise across the differential impedance with a switch. A modified scheme uses first and second parallely connected PMOS capacitors connectable with the transmission pad by switches, which may be NMOS switches. The scheme may be used in a MIPI D-PHY compliant DSI transmitter operating at, for e.g. 800 Mbps, and low signal common-modes. The scheme controls signal transition times of high speed circuitry including transmitters and uses a DATA signal which is already available to the circuitry.Type: GrantFiled: August 31, 2007Date of Patent: June 15, 2010Assignee: Texas Instruments IncorporatedInventor: Anant Shankar Kamath
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Patent number: 7586352Abstract: A converter includes a time-delay circuit for a PWM signal, applied to input of the time-delay circuit, by which rising edges of the PWM signal are delayed by an ON delay and falling edges of the PWM signal are delayed by an OFF delay, in order to form a drive signal, available at the output of the time-delay circuit, for a semiconductor switch element. The time-delay circuit includes two resistors, two capacitors, a diode and a comparator, and is therefore particularly easy to implement.Type: GrantFiled: December 17, 2007Date of Patent: September 8, 2009Assignee: Dr. Johannes Heidenhain GmbHInventor: Norbert Huber
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Patent number: 7518429Abstract: A delay circuit (12) includes a resistor (R1), a capacitor (C), and a discharging circuit (14). The discharging circuit includes a PNP transistor (Q1) and an NPN transistor (Q2). The capacitor has one terminal connected to one terminal of the resistor, and the other terminal connected to ground. The PNP transistor has a base connected to the other terminal of the resistor, a collector, and an emitter connected to a voltage source. The NPN transistor has a base connected to the collector of the PNP transistor, an emitter connected to ground, and a collector connected to the one terminal of the resistor.Type: GrantFiled: June 23, 2007Date of Patent: April 14, 2009Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Bai-Hong Liu, Ze-Shu Ren
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Patent number: 7456664Abstract: The invention discloses a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting the input signal into a first and a second branch. The signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch. The delay component is a passive tunable delay line, and the circuit comprises tuning means for the tunable delay line, the tuning means being affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay. Suitably, the delay component is continuously tunable, for example a tunable ferroelectric delay line.Type: GrantFiled: December 10, 2003Date of Patent: November 25, 2008Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Harald Jacobsson, Spartak Gevorgian, Thomas Lewin
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Patent number: 7456670Abstract: A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of variable capacitors responsive to a control voltage. The variable delay line can also have a ladder configuration of multiple LC subcircuits each having a variable impedance responsive to a control voltage.Type: GrantFiled: May 11, 2006Date of Patent: November 25, 2008Assignee: The Regents of the University of CaliforniaInventors: Ravindran Mahanavelu, Payam Heydari
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Patent number: 7444119Abstract: The present invention proposes novel antenna means mounted on handheld devices and methods of use of such antenna means with multiple radios. The novel antenna means exhibit smaller sizes, good performance, have higher reliability, and exhibit novel hardware configurations. The novel methods of utilization for the antenna means comprise the reception of an 802.11 RF signal to the antennas, the acquisition step while a radio is determining which antenna has the better signal and acquiring signal from that antenna, and usage by the Bluetooth signal of the remaining antenna.Type: GrantFiled: November 30, 2004Date of Patent: October 28, 2008Assignee: Symbol Technologies, Inc.Inventor: Benjamin Jay Bekritsky
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Patent number: 7397292Abstract: A delay and deglitching circuit suppresses glitches occurring in a received digital signal while introducing a predetermined delay to the signal. The deglitching circuit comprises an RC filter and a Schmitt trigger. A node at the input of the Schmitt trigger fed by the RC filter is pulled to a high supply voltage or a low supply voltage when a glitch is removed or the input signal transitions. By setting the RC filter to initial conditions, multiple glitches can be removed with the same affectivity while reducing a sensitivity of the introduced delay to supply voltage variations.Type: GrantFiled: June 21, 2006Date of Patent: July 8, 2008Assignee: National Semiconductor CorporationInventor: Vladislav Potanin
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Patent number: 7068089Abstract: Delays are produced in differential signals using a variable capacitance provided by MOS varactors coupled between the differential signals. The capacitance values of the MOS varactors is controlled by a bias voltage applied to the bodies of the varactors. Selective application of bias voltages to the MOS varactors may be employed to selectively delay one pair of differential signals with respect to another pair of differential signals so as to change the relative phases of the signals. A logic circuit may be used to control the application of bias voltage to the MOS varactors so that signal phases may be adjusted in a manner that is predictable and programmable. These methods may be implemented to compensate for phase offsets between in-phase and quadrature signals of a local oscillator.Type: GrantFiled: May 28, 2004Date of Patent: June 27, 2006Assignee: Wionics ResearchInventor: Zaw Min Soe
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Patent number: 7057435Abstract: A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of variable capacitors responsive to a control voltage. The variable delay line can also have a ladder configuration of multiple LC subcircuits each having a variable impedance responsive to a control voltage.Type: GrantFiled: May 28, 2004Date of Patent: June 6, 2006Assignee: Regents of the University of CaliforniaInventors: Ravindran Mahanavelu, Payam Heydari
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Patent number: 6987423Abstract: A voltage controlled oscillator (VCO) for use in a personal area network synthesizer includes a delay cell (100), a first current amplifier (201, 203) for amplifying an input current, a resister capacitor (RC) tuning network (207, 209, 211) for varying the amount of amplification and delay of an output of the first current amplifier. A second current amplifier (213, 215) is then used for amplifying an output current from the RC tuning network. The invention includes a unique composite voltage variable capacitor (CVVC) (300) for precisely tuning the amount of delay presented by the delay cell. The unique topology of the delay cell (100) allows it to be readily used in voltage controlled oscillators (VCOs) operable at frequencies above 1 GHz.Type: GrantFiled: August 19, 2003Date of Patent: January 17, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Daniel E. Brueske, David B. Harnishfeger, Stephen T. Machan
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Patent number: 6867628Abstract: A circuit includes an input for receiving an input signal, a delay chain connected to the input for delaying the input signal, and a circuit configuration connected to the delay chain downstream of the input, the circuit configuration for supplying a voltage to the delay chain in response to the input signal.Type: GrantFiled: April 3, 2003Date of Patent: March 15, 2005Assignee: Samsung Electronics Co. Ltd.Inventors: Ji-Ho Cho, Seung-Keun Lee
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Patent number: 6472748Abstract: A system and method for maintaining desired circuit component attributes is shown. According to a preferred embodiment, a high frequency circuit component, such as a MMIC, is retained in a circuit using a degradeable material, such as silver filled epoxy, wherein a portion of the degradeable material remains exposed. A protective coating of resin is applied to the exposed portion of the degradeable material by preferably depositing a predetermined amount of protective material, such as an epoxy resin, a void near the exposed portion of the degradeable material. The protective material preferably migrates to fully cover the exposed portion of the degradeable material without covering the circuit component. Accordingly, the circuit component is protected from substantial changes in operation characteristics due to the protective material and likewise is protected from changes in operation characteristics due to degradation of the degradeable material resulting from exposure.Type: GrantFiled: March 6, 2000Date of Patent: October 29, 2002Assignee: Harris Broadband Wireless Access, Inc.Inventor: Carl Edward Calvert
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Patent number: 6222409Abstract: Programmable analog delay line devices for analog signal processing are constructed on a single integrated circuit chip using a switched capacitor storage scheme for short-term storage of the voltage or charge waveform. These devices provide variable maximum delay times without signal attenuation and with delay-to-risetime ratios of up to 102 to 103. A vector array of switched capacitor analog storage elements may be arranged in a ring-buffer topology, with the number of switched capacitor elements ranging from between about 10 and about 105. Two internal counters incremented by a common clock keep track of the variable delay between an input signal and an output signal.Type: GrantFiled: July 16, 1999Date of Patent: April 24, 2001Assignee: University of Utah Research FoundationInventors: David B. Kieda, Michael H. Salamon
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Patent number: 6097231Abstract: An RC equivalent delay circuit includes an input node, an output node, a feedback node, and an intermediate node; a first inverter having an input coupled to the input node and an output coupled to the intermediate node; a second inverter having an input coupled to the intermediate node and an output coupled to the feedback node; a third inverter having an input coupled to the feedback node and an output coupled to the output node; and one or two switches having a first input coupled to the input node, a second input coupled to the feedback node, and an output coupled to the intermediate node.Type: GrantFiled: May 29, 1998Date of Patent: August 1, 2000Assignee: Ramtron International CorporationInventor: Gary P. Moscaluk
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Patent number: 5990721Abstract: A clock for digital devices. Ordinarily, when multiple digital devices are clocked by a common clock, the clock signals frequently arrive at the digital devices at different times, due to propagation delays. The devices are thus not clocked synchronously. Under the invention, the multiple devices are connected to a common transmission line. A standing wave is generated on the transmission line, and the periodic collapse of the standing wave is used to clock the devices. Synchronous clocking to within about 1.0 nano-seconds has been attained, in a transmission line about ten feet long, wherein a clock signal ordinarily takes about 15 nanoseconds to travel from one end to the other.Type: GrantFiled: August 18, 1997Date of Patent: November 23, 1999Assignee: NCR CorporationInventor: Richard I. Mellitz
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Patent number: 5936475Abstract: A ring oscillator comprising a cascade connection of two or several delay stages (31 to 33), wherein each delay stage comprises two differential pairs of two transistors (Q1, Q2; Q3, Q4; Q5, Q7). In the ring oscillator, the collector resistors and the emitter resistor of a traditional ring oscillator are replaced by coils (L1 to L6) in all stages.Type: GrantFiled: June 11, 1997Date of Patent: August 10, 1999Inventors: Nikolay Tchamov, Petri Jarske
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Patent number: 5896054Abstract: A clock driver circuit (100) comprises an input (102) for a reference clock signal. A filter (106) is connected to the input to receive the reference signal and output a filtered signal. A complementary FET driver circuit (108) having a cross-over threshold is coupled to the filter to receive the filtered signal and output a conditioned clock signal.Type: GrantFiled: December 5, 1996Date of Patent: April 20, 1999Assignee: Motorola, Inc.Inventor: David M. Gonzalez
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Patent number: 5869996Abstract: A semiconductor composite element in which abnormal conditions of overcurrent, control supply voltage reduction and overheat are detected, and different abnormality signals are outputted according to the respective abnormal conditions thus detected. The semiconductor composite element includes: abnormal condition detecting circuitry for detecting the overcurrent and control supply voltage reduction of any one or all of the plurality of semiconductor switching elements and the overheat of the semiconductor composite element. An abnormality signal generating circuit is provided for producing different abnormality signals according to the respective abnormal conditions detected by the abnormal condition detecting circuitry.Type: GrantFiled: December 18, 1996Date of Patent: February 9, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Norihiko Okumura
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Patent number: 5497105Abstract: A programmable output pad is disclosed that reduces ground bounce noise and power supply noise under different power supply values and under different load conditions. The programmable output pad comprises a pre-driver, a driver, and a controllable delay. The pre-driver transfers a signal from the input of the output pad to the driver which, in turn, transfers the signal from the pre-driver to an output of the output pad. The controllable delay provides one or more resistors, transistors, transmission gates, or equivalents thereof at the input of the driver which are controlled in order to provide a plurality of different time delays. By selecting these different time delays, the activation of the driver is delayed by different amounts of time. For a given power supply value and load condition, selection of the proper delay effectively reduces both the ground bounce noise on the ground supply of the programmable output pad and the noise on the power supply of the programmable output pad.Type: GrantFiled: June 30, 1994Date of Patent: March 5, 1996Assignee: VLSI Technology, Inc.Inventors: Sung-Hun Oh, Richard M. Taylor