Abstract: A comparator circuit includes a zeroth capacitor having a first terminal fed with an input voltage, a zeroth inverter having an input terminal connected to a second terminal of the zeroth capacitor at a zeroth node, a first capacitor having a first terminal connected to the output terminal of the zeroth inverter at a first node, a first inverter having an input terminal connected to a second terminal of the first capacitor at a second node, a second inverter having an input terminal connected to the output terminal of the first inverter at a third node, a zeroth switch switching conduction between the zeroth and first nodes, a first switch switching conduction between the second and third nodes, a second switch switching conduction between the first and third nodes, and a third switch switching conduction between the third node and the output terminal of the second inverter.

Abstract: Provided herein are systems and methods for performing dynamic adaption and correction for internal delays in devices connected to a common time-multiplexed bus. The methods allow devices to operate reliably at a higher bus frequency by correcting for inherent and unknown delays within the components and in the system by measuring the actual delays using multiple readings with the bus. Intrinsic noise and jitter are used to increase the precision of the measurements, thereby essentially using these uncertainties as self-dithering for increased measurement resolution. During adaption, delays may be adjusted in multiple step sizes to speed adaption time.

Abstract: Methods and apparatuses are provided for temperature independent resistive-capacitive delay circuits of a semiconductor device. For example, delays associated with ZQ calibration or timing of the RAS chain may be implemented that to include circuitry that exhibits both proportional to absolute temperature (PTAT) characteristics and complementary to absolute temperature (CTAT) characteristics in order to control delay times across a range of operating temperatures. The RC delay circuits may include a first type of circuitry having impedance with PTAT characteristics that is coupled to an output node in parallel with a second type of circuitry having impedance with CTAT characteristics. The first type of circuitry may include a resistor and the second type of circuitry may include a transistor, in some embodiments.

Abstract: A light detection and ranging (LIDAR) system includes a transmitter configured to output a number of output pulses to a target object; a receiver configured to receive a plurality of input pulses corresponding to the number of output pulses; and a signal processor including a signal converter configured to convert the plurality of input pulses into discrete signals and an encoder configured to encode amplitude information of the plurality of input pulses converted into the discrete signals.

Abstract: A power supply device includes a plurality of battery modules, the battery modules are connected to one another in series according to a gate driving signal from a controller, the power supply device delays the gate driving signal in a gate driving signal processing circuit included in each of the battery modules, and thereafter, transmits the gate driving signal from an upstream to a downstream of the series connection, and the power supply device controls the battery modules by superimposing a control signal for the battery module on the gate driving signal.

Abstract: A semiconductor integrated circuit of an embodiment includes: a delay element array circuit in which a plurality of delay elements having a delay amount Tw are connected in series; a flip-flop group including a plurality of flip-flops each of which an input is connected to an output of a corresponding delay element; a delay element group configured to generate, from an input clock signal, a plurality of output clock signals each having a delay difference of a second delay amount smaller than the delay amount Tw; and a delay unit configured to set a third delay amount smaller than the second delay amount, and the delay element group and the delay unit are connected in series between an output terminal of an input signal CLK_DET and an input terminal of the flip-flop group.

Abstract: In a case where signals branched from a single reference signal source are transmitted via a plurality of cables, a phase synchronization circuit can be used to stabilize a phase of a signal to be outputted from each cable. However, the phases of signal to be outputted from each cable is affected by combination of a length of each cable and an amount of delay caused by feedback control, so that phases of synchronization signals to be outputted from a plurality of transmission paths are not always the same as each other. In the present invention, since a frequency multiplier that multiplies a frequency of a signal outputted from each transmission path by an even number is provided for a phase synchronization circuit, the phases of the synchronization signals to be outputted from the transmission paths are aligned even when signals are branched from one reference signal.

Abstract: The present document relates to a timer which is counter-based and uses an asynchronous circuitry to improve the accuracy between the available clock cycles. In particular, a timer is presented which may comprise a first timer circuit configured to receive a clock signal and a trigger signal, wherein an edge of the trigger signal arrives after a first edge of the clock signal and before a second edge of the clock signal. The first timer circuit may be configured to determine, in a capture phase, a time offset interval for approximating a time interval between the first edge of the clock signal and the edge of the trigger signal.

Abstract: A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.

Abstract: A ring oscillator includes a first set of at least three laddered inverter quantizer (LIQAF) circuits connected in stages that are in series, including a first LIQAF circuit and a last LIQAF circuit, and a feedback circuit from the last LIQAF circuit to the first LIQAF circuit having a logical NOT output compared to the first LIQAF circuit. A voltage input creates a pair of phase shifted waveforms in the first of the at least three LIQAF circuits that propagate sequentially through the stages of the at least three LIQAF circuits. Each stage has a pair of outputs to the next stage that are then phase shifted from the previous stage in the next stage.

Abstract: An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switch to the feedback switches to accelerate the pull up or the pull down.

Abstract: The present description concerns a comparator (1) of a first voltage (V+) and of a second voltage (V?), comprising first (100) and second (102) branches each comprising a same succession of alternated first (106) and second (108) gates in series between a node (104) and an output (1002; 1022) of the branch (100; 102), wherein: each branch starts with a first gate (106), each gate (106; 108) has a second node (114) receiving a bias voltage, the second node (114) of each first gate (106) of the first branch (100) and of each second gate (108) of the second branch (102) receives the first voltage (V+), the second node of the other gates receiving the second voltage (V?), and an order of arrival of the edges on the outputs (1002; 1022) of the branches determines a result of a comparison.

Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.

Abstract: A propagation delay balance circuit includes a signal generating circuit, a path switching element, and a signal change detecting element. The signal generating circuit includes delay chains for outputting delay signals respectively. The path switching element has input terminals and output terminals. Each output terminal of the path switching element is electrically connected to the input terminal of each delay chain one-to-one, and input terminals of the path switching element are electrically connected one-to-one to the output terminals of the delay chains. The path switching element is controlled by the path switching controlling signal to change the one-to-one internal electrical connection between input terminals and output terminals of the path switching element. The signal change detecting element is electrically connected to the path switching element, and generates a path switching controlling signal according to delay signals of the path switching element.

Abstract: A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.

Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.

Abstract: According to one embodiment, a duty adjustment circuit includes: a first delay circuit including a plurality of first delay elements connected in series, each of the first delay elements has a first delay amount; a second delay circuit having a first variable delay unit configured to set a second delay amount smaller than the first delay amount; and a third delay circuit having a second variable delay unit configured to set a third delay amount smaller than the first delay amount. An output terminal of the second delay circuit is connected to an even numbered one of the first delay elements, and an output terminal of the third delay circuit is connected to an odd numbered one of the first delay elements.

Abstract: A pure digital ring oscillator with constant power consumption as oscillation frequency is adjusted. Circuit topology includes a multiplexer implemented in NAND gates and a delay element positioned after a path selection NAND gate of that multiplexer such that delay element transistors may not toggle if the non-delaying signal path is selected. Assuming a delay element oscillation frequency f and a total capacitance C, and also assuming a plurality N of delay gates each characterized by a propagation delay t1 and a capacitance C1 such that C=C1*N, the ring oscillator of the present invention is characterized by a C value that is proportional to N and an f value that is inversely proportional to N. Furthermore, each of the N delay gates as well as the input and output gates of the multiplexer are characterized by a common capacitance-to-propagation delay ratio=C1/t1.

Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.

Abstract: A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.

Abstract: An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.

Abstract: A device is disclosed that includes a control circuit and a scope circuit. The control circuit is configured to delay a voltage signal to generate a first control signal. The scope circuit is configured to be operated in one of a first mode and a second mode according to the first control signal. In the first mode, the scope circuit is configured to generate a first current signal indicating amplitudes of the voltage signal, and in the second mode, the scope circuit is configured to stop generating the first current signal.

Abstract: A playback device includes a first generator, a second generator and a combiner. The first generator processes main audio data to output first audio data. The second generator processes additional audio data to output second audio data. The combiner combines the first audio data with the second audio data. While a sampling frequency of the main audio data is different from a sampling frequency of the additional audio data, the second generator generates the second audio data to adjust a playback speed of the additional audio data based on the sampling frequency of the main audio data.

Abstract: A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.

Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

Abstract: A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

Abstract: The embodiments employ a transaction based design methodology to supply clocking when clock pulses are requested. The transactional module receives a clock when it requests a clock pulse and one stage of a logic pipeline is clocked at a time. This methodology reduces dynamic power dissipation by the transactional module from the dynamic power dissipated by traditional synchronous logic designs.

Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

Abstract: A circuit includes: a first delay circuit configured to receive a first clock signal; a second delay circuit configured to receive a second clock signal; a delay control circuit, coupled to the first and second delay circuits, and configured to cause the first and second delay circuits to respectively align the first and second clock signals within a noise window; and a loop control circuit, coupled to the first and second delay circuits, and configured to alternately form a first oscillation loop and a second oscillation loop passing through each of the first and second delay circuits so as to determine the noise window.

Abstract: A time-to-voltage converter (TVC) including a 555 timer integrated circuit (IC), and a charging circuit including a constant current source and a capacitor connected in series. The capacitor can be connected to a discharge pin of the 555 timer IC. The TVC can further include a trigger circuit and a reset circuit to receive a start signal and a stop signal, respectively, from an input line, and accordingly generate a trigger signal or a reset signal to trigger or reset the 555 timer IC. A switch can be configured to, under control of an output signal of the 555 timer IC, connect the input line with the reset circuit. A voltage across the capacitor when the 555 timer IC is reset indicates a time interval corresponding to the start and stop signals.

Abstract: A skew correction system includes delay circuits positioned in front of sampling circuitry. A skew correction controller first delays an input clock signal to create hold violations. Then with, with the delay of an input clock signal fixed at a reference delay amount, the skew correction controller delays input data signals first to remove or reduce the hold violations, and then to create setup violations. Based on the delaying, the skew correction controller identifies data valid windows for the input data signals, and in turn, identifies target delay amounts that position a delayed clock signal in target sampling positions.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for on-chip jitter tolerance testing. A receiver component includes a clock data recovery (CDR) logic circuit. The CDR logic circuit includes a controller to receive a phase signal and to output a DCO control signal; jitter injection (JINJ) logic to generate a first jitter signal at a first frequency and a first amplitude; and digitally controlled oscillator (DCO) to receive the first jitter signal applied to the DCO control signal and to output, based on the first jitter signal applied to the DCO control signal, a first DCO clock signal for on-chip jitter tolerance testing.

Abstract: A lighting system may have a power-supply circuit and at least two strings of solid-state light sources. The power-supply circuit comprises two output terminals where the power-supply circuit supplies a regulated voltage (Vout), and where the regulated voltage (Vout) is periodically activated for a first duration and de-activated for a second duration as a function of a dimming signal. A first string of light sources and a first current regulator are connected in series between the two output terminals, wherein the first current regulator is configured for regulating the current flowing through the first string. A second string of solid-state light sources and a second current regulator are connected in series between the two output terminals, wherein the second current regulator is configured for regulating the current flowing through said second string.

Abstract: Amplification of a signal by a small circuit size and reduction of a power are achieved. A current controlling current source unit 53 changes an outputting current based on a transition time setting signal tp. A current controlling current source unit 54 changes a drawing current based on a transition time setting signal tn. An amplitude control unit 55 changes a power source voltage supplied to the current controlling current source unit 53 and changes amplitude of a voltage generated by a current outputted from the current controlling current source unit 53, based on amplitude setting signal ap. An amplitude control unit 56 changes a power source voltage supplied to the current controlling current source unit 54 and changes amplitude of a voltage generated by the current drawn by the current controlling current source unit 54, based on amplitude setting signal an.

Abstract: An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.

Abstract: In order to provide a semiconductor device capable of detecting HCI degradation of a semiconductor element in a simple structure, the semiconductor device includes an oscillation circuit including a plurality of logic gates of various driving forces which are formed by transistors and coupled in series, a frequency counter that measures an oscillation frequency of the oscillation circuit, and a comparator that compares the oscillation frequency of the oscillation circuit measured by the frequency counter with a predetermined value.

Abstract: A skew detection circuit may include a bias circuit configured to generate a first bias signal and a second bias signal, a reference voltage circuit configured to generate a third bias signal and a fourth bias signal, and a detection circuit configured to generate, using the first to fourth bias signals, a plurality of skew detection signals. The skew detection signals may correspond to effects of one or more of process variations, voltage variations, and temperature variations.

Abstract: In certain aspects, an integrated circuit comprises a signal path having a path delay from an input to an output, wherein the signal path comprises a path capacitor having a path capacitance. The integrated circuit also comprises a variation tracking circuit coupled to the signal path, wherein the variation tracking circuit comprises a tracking resistor have a tracking resistance, and wherein a product of the tracking resistance and the path capacitance is substantially constant over process variation.

Abstract: In one form, a power factor correction (PFC) controller, comprising includes a regulation circuit, a dead-time detection circuit, and a pulse width modulator. The regulation circuit provides a control voltage in response to a feedback voltage received at a feedback input terminal, wherein the feedback voltage is proportional to an output voltage. The dead-time detection circuit has an input coupled to a zero current detection input terminal, and an output for providing a dead-time signal. The pulse width modulator is responsive to the control voltage and the dead-time signal to provide a drive signal that controls conduction of a switch to improve a power factor of an offline converter, wherein the pulse width modulator modulates both an on-time and a switching period of the drive signal using the dead-time signal in a discontinuous conduction mode.

Abstract: A flicker noise measurement circuit includes a first section. The first section includes a plurality of first stages connected in series. The first section includes a first feedback switching element configured to selectively feedback an output of the plurality of first stages to an input of the plurality of first stages. The first section includes a first section connection switching element. The flicker noise measurement circuit includes a second section connected to the first section. The second section includes a plurality of second stages connected in series, wherein the first section connection switching element is configured to selectively connect the plurality of second stages to the plurality of first stages. The second section includes a second feedback switching element configured to selectively feedback an output of the plurality of second stages to the input of the plurality of first stages.

Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

Abstract: The serial communication system includes a first communication device and a second communication device connected with the first communication device. The first communication device and the second communication device respectively operates in response to a first clock signal and a second clock. The first communication device generates a first training signal, transmits the first training signal to the second communication device, encodes a first data signal to generate a first encoded signal, and transmits the first encoded signal to the second communication device. The second communication device measures a second interval length, receives the first encoded signal from the first communication device, and decodes the first data signal from the first encoded signal by detecting the level of the first encoded signal at a preset first point of time preset and a preset second point of time.

Abstract: Methods and apparatuses of compensating for delays of a storage device are disclosed. The method includes: performing a communication operation a preset number of times with the storage device through the extension line, each time if a correct response is received from the storage device, recording a status value of the current communication operation as a first value, otherwise recording as a second value, to obtain a resultant data string; searching, in the resultant data string, for a longest data segment comprised of the continuous first values; taking a delay value of the communication operation corresponding to the status value at the middle position of the longest data segment as an optimal delay value; and setting the optimal delay value as a phase difference between a source clock and a sampling clock of the storage device to compensate for the delays caused by the extension line of the storage device.

Abstract: A probe, including a first input configured to receive a first input signal, a second input configured to receive a second input signal, a first cable connected to the first input, a second cable connected to the second input, an electronically adjustable delay connected to the first cable, the electronically adjustable delay configured to delay the first input signal to remove a skew between the first input signal and the second input signal, and an amplifier configured to receive the first input signal from the electronically adjustable delay and a second input signal.

Abstract: A CMOS all-digital pulse-mixing device includes a plurality of homogeneous logic elements serially connected to form a basic element sequence, an odd-positioned element parallel connection set and an even-positioned element parallel connection set. The basic element sequence includes odd combination positions and even combination positions. The odd-positioned element parallel connection set serially connects with one of the odd combination positions and the even-positioned element parallel connection set serially connects with one of the even combination positions. The odd-positioned element parallel connection set and the even-positioned element parallel connection set are provided to stretch or shrink a pulse mixture, which is distinguished from a conventional full-customized pulse-mixing device.

Abstract: Systems, methods, and apparatus for reducing standing wave reflections between delay line modules are described. The delay line modules include semiconductor switches, particularly MOSFET switches fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates and embedded attenuators. According to one aspect, a delay line module includes two switches with delay lines coupled between respective output ports of the switches. Each switch includes MOSFET switches forming conduction paths with selectable high and low impedances. According to another aspect, at least one of the conduction paths includes an attenuator block formed by one or more shunting resistors coupled to one of the MOSFET switches. The output ports of the switches can be selectively coupled to a reference ground via a shunted MOSFET switch.

Abstract: A first encoding part encodes a reference timing determined by a reference clock by using a delay line. A second encoding part encodes a measurement start timing and a measurement end timing of a measurement period determined by a measurement signal to be measured by also using the delay line. A count part counts the reference clocks included in the measurement period. A fraction calculation part calculates a start fraction number indicating a time difference from the measurement start timing and an immediately-following reference timing and an end fraction number indicating a time difference from the measurement end timing to an immediately-following reference timing, based on the encoding result. The fraction calculation part then calculates a fraction data indicating a difference between the measurement period and a product of the period of the reference timing and the count value of the count part.

Abstract: An organic light emitting display, including a first data line extending along a first direction, a second data line extending along the first direction and disposed parallel to the first data line, a first scan line extending along a second direction perpendicular to the first direction, a first pixel connected to the first data line and the first scan line, a second pixel connected to the second data line and the first scan line, a first constant current source connected to the first data line, a second constant current source connected to the second data line, and a temperature information generation unit comprising a first input port connected to the first data line and a second input port connected to the second data line.

Abstract: The resolution of a time to digital converter (TDC) is improved by using a gain stage at the input of the fine TDC. A delay line receives a pulse corresponding to the time information and recirculates the pulse in the delay line by coupling an output of the delay line to an input of the delay line. An integrating fine TDC receives a number of pulses from the delay line corresponding to the desired gain.