Having Specific Delay In Producing Output Waveform Patents (Class 327/261)
  • Patent number: 11509299
    Abstract: The present description concerns a comparator (1) of a first voltage (V+) and of a second voltage (V?), comprising first (100) and second (102) branches each comprising a same succession of alternated first (106) and second (108) gates in series between a node (104) and an output (1002; 1022) of the branch (100; 102), wherein: each branch starts with a first gate (106), each gate (106; 108) has a second node (114) receiving a bias voltage, the second node (114) of each first gate (106) of the first branch (100) and of each second gate (108) of the second branch (102) receives the first voltage (V+), the second node of the other gates receiving the second voltage (V?), and an order of arrival of the edges on the outputs (1002; 1022) of the branches determines a result of a comparison.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: November 22, 2022
    Assignee: Commissariat à l'Energie Atomique et aux Energies Alternatives
    Inventor: Arnaud Verdant
  • Patent number: 11418177
    Abstract: A propagation delay balance circuit includes a signal generating circuit, a path switching element, and a signal change detecting element. The signal generating circuit includes delay chains for outputting delay signals respectively. The path switching element has input terminals and output terminals. Each output terminal of the path switching element is electrically connected to the input terminal of each delay chain one-to-one, and input terminals of the path switching element are electrically connected one-to-one to the output terminals of the delay chains. The path switching element is controlled by the path switching controlling signal to change the one-to-one internal electrical connection between input terminals and output terminals of the path switching element. The signal change detecting element is electrically connected to the path switching element, and generates a path switching controlling signal according to delay signals of the path switching element.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: August 16, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Fu-Sheng Hsu
  • Patent number: 11418189
    Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: August 16, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jagadeesh Anathahalli Singrigowda, Ashish Sahu, Rajesh Mangalore Anand, Aniket Bharat Waghide, Girish Anathahalli Singrigowda, Prasant Kumar Vallur
  • Patent number: 11405029
    Abstract: A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: August 2, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hundae Choi, Garam Choi
  • Patent number: 11385677
    Abstract: A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: July 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Michael Ryan Hanschke, Pankaj Pandey, Joseph Pham, David Wayne Evans
  • Patent number: 11380409
    Abstract: According to one embodiment, a duty adjustment circuit includes: a first delay circuit including a plurality of first delay elements connected in series, each of the first delay elements has a first delay amount; a second delay circuit having a first variable delay unit configured to set a second delay amount smaller than the first delay amount; and a third delay circuit having a second variable delay unit configured to set a third delay amount smaller than the first delay amount. An output terminal of the second delay circuit is connected to an even numbered one of the first delay elements, and an output terminal of the third delay circuit is connected to an odd numbered one of the first delay elements.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 5, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Masashi Nakata
  • Patent number: 11283430
    Abstract: A pure digital ring oscillator with constant power consumption as oscillation frequency is adjusted. Circuit topology includes a multiplexer implemented in NAND gates and a delay element positioned after a path selection NAND gate of that multiplexer such that delay element transistors may not toggle if the non-delaying signal path is selected. Assuming a delay element oscillation frequency f and a total capacitance C, and also assuming a plurality N of delay gates each characterized by a propagation delay t1 and a capacitance C1 such that C=C1*N, the ring oscillator of the present invention is characterized by a C value that is proportional to N and an f value that is inversely proportional to N. Furthermore, each of the N delay gates as well as the input and output gates of the multiplexer are characterized by a common capacitance-to-propagation delay ratio=C1/t1.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: March 22, 2022
    Assignee: Fermi Research Alliance, LLC
    Inventor: Jinyuan Wu
  • Patent number: 11239228
    Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien
  • Patent number: 11233512
    Abstract: The present technology may include: a first logic gate coupled to an internal voltage terminal and configured to receive data and invert and output the data according to a first enable signal; and a second logic gate coupled to the internal voltage terminal and configured to invert an output of the first logic gate and to output an inverted output as a first buffer signal according to the first enable signal, and configured to compensate for a duty skew of the first buffer signal according to a level of an external voltage.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: January 25, 2022
    Assignee: SK hynix Inc.
    Inventors: Jin Ha Hwang, Yo Han Jeong, Eun Ji Choi
  • Patent number: 11226649
    Abstract: A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: January 18, 2022
    Assignee: NXP B.V.
    Inventors: Hamidreza Hashempour, Jos Verlinden, Ids Christiaan Keekstra
  • Patent number: 11151287
    Abstract: An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 19, 2021
    Assignees: STMICROELECTRONICS SA, INSTITUT POLYTECHNIQUE DE GRENOBLE
    Inventors: Sophie Germain, Sylvain Engels, Laurent Fesquet
  • Patent number: 11035886
    Abstract: A device is disclosed that includes a control circuit and a scope circuit. The control circuit is configured to delay a voltage signal to generate a first control signal. The scope circuit is configured to be operated in one of a first mode and a second mode according to the first control signal. In the first mode, the scope circuit is configured to generate a first current signal indicating amplitudes of the voltage signal, and in the second mode, the scope circuit is configured to stop generating the first current signal.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Peng Hsieh, Chih-Chiang Chang, Chung-Chieh Yang
  • Patent number: 10871936
    Abstract: A playback device includes a first generator, a second generator and a combiner. The first generator processes main audio data to output first audio data. The second generator processes additional audio data to output second audio data. The combiner combines the first audio data with the second audio data. While a sampling frequency of the main audio data is different from a sampling frequency of the additional audio data, the second generator generates the second audio data to adjust a playback speed of the additional audio data based on the sampling frequency of the main audio data.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: December 22, 2020
    Assignee: FUNAI ELECTRIC CO., LTD.
    Inventor: Eiji Nakata
  • Patent number: 10855280
    Abstract: A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 10855291
    Abstract: The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Tso Lin, Chin-Ming Fu, Mao-Ruei Li
  • Patent number: 10812056
    Abstract: A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 20, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Zhengzheng Wu, Xu Zhang, Xuhao Huang
  • Patent number: 10761560
    Abstract: The embodiments employ a transaction based design methodology to supply clocking when clock pulses are requested. The transactional module receives a clock when it requests a clock pulse and one stage of a logic pipeline is clocked at a time. This methodology reduces dynamic power dissipation by the transactional module from the dynamic power dissipated by traditional synchronous logic designs.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 1, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chang Hoon Lee, John Edward Vincent, Louis-Philippe Hamelin, Paul Alepin
  • Patent number: 10707199
    Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien
  • Patent number: 10684325
    Abstract: A circuit includes: a first delay circuit configured to receive a first clock signal; a second delay circuit configured to receive a second clock signal; a delay control circuit, coupled to the first and second delay circuits, and configured to cause the first and second delay circuits to respectively align the first and second clock signals within a noise window; and a loop control circuit, coupled to the first and second delay circuits, and configured to alternately form a first oscillation loop and a second oscillation loop passing through each of the first and second delay circuits so as to determine the noise window.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Tien-Chien Huang
  • Patent number: 10530347
    Abstract: A skew correction system includes delay circuits positioned in front of sampling circuitry. A skew correction controller first delays an input clock signal to create hold violations. Then with, with the delay of an input clock signal fixed at a reference delay amount, the skew correction controller delays input data signals first to remove or reduce the hold violations, and then to create setup violations. Based on the delaying, the skew correction controller identifies data valid windows for the input data signals, and in turn, identifies target delay amounts that position a delayed clock signal in target sampling positions.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 7, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tianyu Tang, Venkatesh Ramachandra
  • Patent number: 10528010
    Abstract: A time-to-voltage converter (TVC) including a 555 timer integrated circuit (IC), and a charging circuit including a constant current source and a capacitor connected in series. The capacitor can be connected to a discharge pin of the 555 timer IC. The TVC can further include a trigger circuit and a reset circuit to receive a start signal and a stop signal, respectively, from an input line, and accordingly generate a trigger signal or a reset signal to trigger or reset the 555 timer IC. A switch can be configured to, under control of an output signal of the 555 timer IC, connect the input line with the reset circuit. A voltage across the capacitor when the 555 timer IC is reset indicates a time interval corresponding to the start and stop signals.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: January 7, 2020
    Assignee: King Fahd University of Petroleum and Minerals
    Inventor: Muhammad Taher Abuelma'Atti
  • Patent number: 10498469
    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for on-chip jitter tolerance testing. A receiver component includes a clock data recovery (CDR) logic circuit. The CDR logic circuit includes a controller to receive a phase signal and to output a DCO control signal; jitter injection (JINJ) logic to generate a first jitter signal at a first frequency and a first amplitude; and digitally controlled oscillator (DCO) to receive the first jitter signal applied to the DCO control signal and to output, based on the first jitter signal applied to the DCO control signal, a first DCO clock signal for on-chip jitter tolerance testing.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Mor Cohen, Amir Mezer, Golan Perry, Adee Ofir Ran
  • Patent number: 10492250
    Abstract: A lighting system may have a power-supply circuit and at least two strings of solid-state light sources. The power-supply circuit comprises two output terminals where the power-supply circuit supplies a regulated voltage (Vout), and where the regulated voltage (Vout) is periodically activated for a first duration and de-activated for a second duration as a function of a dimming signal. A first string of light sources and a first current regulator are connected in series between the two output terminals, wherein the first current regulator is configured for regulating the current flowing through the first string. A second string of solid-state light sources and a second current regulator are connected in series between the two output terminals, wherein the second current regulator is configured for regulating the current flowing through said second string.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 26, 2019
    Assignee: OSRAM GmbH
    Inventor: Luca Volpato
  • Patent number: 10448923
    Abstract: Amplification of a signal by a small circuit size and reduction of a power are achieved. A current controlling current source unit 53 changes an outputting current based on a transition time setting signal tp. A current controlling current source unit 54 changes a drawing current based on a transition time setting signal tn. An amplitude control unit 55 changes a power source voltage supplied to the current controlling current source unit 53 and changes amplitude of a voltage generated by a current outputted from the current controlling current source unit 53, based on amplitude setting signal ap. An amplitude control unit 56 changes a power source voltage supplied to the current controlling current source unit 54 and changes amplitude of a voltage generated by the current drawn by the current controlling current source unit 54, based on amplitude setting signal an.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: October 22, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Takuma Nishimoto, Yutaka Igarashi, Yusaku Katsube, Kengo Imagawa
  • Patent number: 10403335
    Abstract: An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Uemura, Yasuhiro Takai
  • Patent number: 10396802
    Abstract: In order to provide a semiconductor device capable of detecting HCI degradation of a semiconductor element in a simple structure, the semiconductor device includes an oscillation circuit including a plurality of logic gates of various driving forces which are formed by transistors and coupled in series, a frequency counter that measures an oscillation frequency of the oscillation circuit, and a comparator that compares the oscillation frequency of the oscillation circuit measured by the frequency counter with a predetermined value.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Mitsuhiko Igarashi, Kan Takeuchi, Takeshi Okagaki
  • Patent number: 10361691
    Abstract: A skew detection circuit may include a bias circuit configured to generate a first bias signal and a second bias signal, a reference voltage circuit configured to generate a third bias signal and a fourth bias signal, and a detection circuit configured to generate, using the first to fourth bias signals, a plurality of skew detection signals. The skew detection signals may correspond to effects of one or more of process variations, voltage variations, and temperature variations.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: July 23, 2019
    Assignee: SK HYNIX INC.
    Inventor: Yeonsu Jang
  • Patent number: 10312891
    Abstract: In certain aspects, an integrated circuit comprises a signal path having a path delay from an input to an output, wherein the signal path comprises a path capacitor having a path capacitance. The integrated circuit also comprises a variation tracking circuit coupled to the signal path, wherein the variation tracking circuit comprises a tracking resistor have a tracking resistance, and wherein a product of the tracking resistance and the path capacitance is substantially constant over process variation.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 4, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Chao Song, Zhengzheng Wu, Haitao Cheng, Ye Lu
  • Patent number: 10312799
    Abstract: In one form, a power factor correction (PFC) controller, comprising includes a regulation circuit, a dead-time detection circuit, and a pulse width modulator. The regulation circuit provides a control voltage in response to a feedback voltage received at a feedback input terminal, wherein the feedback voltage is proportional to an output voltage. The dead-time detection circuit has an input coupled to a zero current detection input terminal, and an output for providing a dead-time signal. The pulse width modulator is responsive to the control voltage and the dead-time signal to provide a drive signal that controls conduction of a switch to improve a power factor of an offline converter, wherein the pulse width modulator modulates both an on-time and a switching period of the drive signal using the dead-time signal in a discontinuous conduction mode.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: June 4, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Joel Turchi, Radim Mlcousek, Lukas Olivik
  • Patent number: 10295583
    Abstract: A flicker noise measurement circuit includes a first section. The first section includes a plurality of first stages connected in series. The first section includes a first feedback switching element configured to selectively feedback an output of the plurality of first stages to an input of the plurality of first stages. The first section includes a first section connection switching element. The flicker noise measurement circuit includes a second section connected to the first section. The second section includes a plurality of second stages connected in series, wherein the first section connection switching element is configured to selectively connect the plurality of second stages to the plurality of first stages. The second section includes a second feedback switching element configured to selectively feedback an output of the plurality of second stages to the input of the plurality of first stages.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao Chieh Li, Ruey-Bin Sheen
  • Patent number: 10269784
    Abstract: An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Te Lin, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Li-Chun Tien
  • Patent number: 10177893
    Abstract: The serial communication system includes a first communication device and a second communication device connected with the first communication device. The first communication device and the second communication device respectively operates in response to a first clock signal and a second clock. The first communication device generates a first training signal, transmits the first training signal to the second communication device, encodes a first data signal to generate a first encoded signal, and transmits the first encoded signal to the second communication device. The second communication device measures a second interval length, receives the first encoded signal from the first communication device, and decodes the first data signal from the first encoded signal by detecting the level of the first encoded signal at a preset first point of time preset and a preset second point of time.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: January 8, 2019
    Assignee: Ricoh Company, Ltd.
    Inventor: Yoshinori Shimosakoda
  • Patent number: 10162570
    Abstract: Methods and apparatuses of compensating for delays of a storage device are disclosed. The method includes: performing a communication operation a preset number of times with the storage device through the extension line, each time if a correct response is received from the storage device, recording a status value of the current communication operation as a first value, otherwise recording as a second value, to obtain a resultant data string; searching, in the resultant data string, for a longest data segment comprised of the continuous first values; taking a delay value of the communication operation corresponding to the status value at the middle position of the longest data segment as an optimal delay value; and setting the optimal delay value as a phase difference between a source clock and a sampling clock of the storage device to compensate for the delays caused by the extension line of the storage device.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: December 25, 2018
    Assignee: AUTOCHIPS INC.
    Inventor: Songlin Chen
  • Patent number: 10145822
    Abstract: A probe, including a first input configured to receive a first input signal, a second input configured to receive a second input signal, a first cable connected to the first input, a second cable connected to the second input, an electronically adjustable delay connected to the first cable, the electronically adjustable delay configured to delay the first input signal to remove a skew between the first input signal and the second input signal, and an amplifier configured to receive the first input signal from the electronically adjustable delay and a second input signal.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: December 4, 2018
    Assignee: Tektronix, Inc.
    Inventors: Daniel G. Knierim, Christopher R. Muggli, Martin Rockwell, Ira G. Pollock
  • Patent number: 10141919
    Abstract: A CMOS all-digital pulse-mixing device includes a plurality of homogeneous logic elements serially connected to form a basic element sequence, an odd-positioned element parallel connection set and an even-positioned element parallel connection set. The basic element sequence includes odd combination positions and even combination positions. The odd-positioned element parallel connection set serially connects with one of the odd combination positions and the even-positioned element parallel connection set serially connects with one of the even combination positions. The odd-positioned element parallel connection set and the even-positioned element parallel connection set are provided to stretch or shrink a pulse mixture, which is distinguished from a conventional full-customized pulse-mixing device.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: November 27, 2018
    Assignee: National Kaohsiung First University of Science and Technology
    Inventors: Chun-Chi Chen, Che-Hsun Chu, Chorng-Sii Hwang
  • Patent number: 10056889
    Abstract: Systems, methods, and apparatus for reducing standing wave reflections between delay line modules are described. The delay line modules include semiconductor switches, particularly MOSFET switches fabricated on silicon-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates and embedded attenuators. According to one aspect, a delay line module includes two switches with delay lines coupled between respective output ports of the switches. Each switch includes MOSFET switches forming conduction paths with selectable high and low impedances. According to another aspect, at least one of the conduction paths includes an attenuator block formed by one or more shunting resistors coupled to one of the MOSFET switches. The output ports of the switches can be selectively coupled to a reference ground via a shunted MOSFET switch.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: August 21, 2018
    Assignee: pSemi Corporation
    Inventors: Raul Inocencio Alidio, Peter Bacon
  • Patent number: 9964928
    Abstract: A first encoding part encodes a reference timing determined by a reference clock by using a delay line. A second encoding part encodes a measurement start timing and a measurement end timing of a measurement period determined by a measurement signal to be measured by also using the delay line. A count part counts the reference clocks included in the measurement period. A fraction calculation part calculates a start fraction number indicating a time difference from the measurement start timing and an immediately-following reference timing and an end fraction number indicating a time difference from the measurement end timing to an immediately-following reference timing, based on the encoding result. The fraction calculation part then calculates a fraction data indicating a difference between the measurement period and a product of the period of the reference timing and the count value of the count part.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: May 8, 2018
    Assignee: DENSO CORPORATION
    Inventors: Shigenori Yamauchi, Takamoto Watanabe, Nobuyuki Taguchi
  • Patent number: 9959810
    Abstract: An organic light emitting display, including a first data line extending along a first direction, a second data line extending along the first direction and disposed parallel to the first data line, a first scan line extending along a second direction perpendicular to the first direction, a first pixel connected to the first data line and the first scan line, a second pixel connected to the second data line and the first scan line, a first constant current source connected to the first data line, a second constant current source connected to the second data line, and a temperature information generation unit comprising a first input port connected to the first data line and a second input port connected to the second data line.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: May 1, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hyun Sik Kim
  • Patent number: 9917591
    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingdong Deng, Chung S. Ho, David Flye, Zhenrong Jin, Ramana M. Malladi
  • Patent number: 9866225
    Abstract: Some embodiments include apparatuses and methods having a digitally controlled oscillator (DCO) in a digital phase-locked loop (PLL) and a control loop. The DCO can generate an output signal having a frequency based on a value of a digital information. The control loop can adjust a value of a supply voltage of the DCO based on the value the digital information. Additional apparatuses and methods are described.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: January 9, 2018
    Assignee: Intel Corporation
    Inventors: Noam Familia, Avigdor Saksonov, Eyal Fayneh, Joseph Shor
  • Patent number: 9837994
    Abstract: A digital control ring oscillator (DCO) generally comprises a first delay element and at least one second delay element that is coupled to the first delay element, wherein each of the first and second delay elements are disposed laterally with respect to one another in a first direction and include at least one cell. The cell includes a plurality of transistors arranged in at least one stack.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Tsung-Hsien Tsai
  • Patent number: 9712145
    Abstract: A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 18, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Fu-Lung Hsueh
  • Patent number: 9704581
    Abstract: Method, system and apparatus for detecting voltage ramping to a target voltage level in steady state, comprising, ramping a regulated voltage to a steady state target voltage for an operation of a load circuit, the steady state target voltage being a voltage level that enables the load circuit to perform the operation, generating an output signal indicating that the regulated voltage has reached the target voltage and generating a ready signal responsive to detecting the output signal.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Jason Guo, Qiang Tang
  • Patent number: 9697662
    Abstract: An activate signal is sent out from a remote controller via a first channel. An authorization process is activated after the activate signal is received by an access control terminal. A control signal is sent out from the remote controller via a second channel to the access control terminal. The access control terminal is unlocked if the control signal received by the access control terminal is verified by the authorization process to be consistent with a predetermined rule. The first channel is different from the second channel.
    Type: Grant
    Filed: May 10, 2015
    Date of Patent: July 4, 2017
    Assignee: LEADOT INNOVATION, INC.
    Inventor: Justin Wang
  • Patent number: 9689917
    Abstract: Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit may include a clock jitter monitor circuit configured with a constant supply voltage. This clock jitter monitor is configured to measure the clock jitter that is experienced by the digital voltage monitor circuit and, when compared to measured voltage captured by the circuit, may be used to calibrate or otherwise correct the readings provided by the digital voltage monitor circuit.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: June 27, 2017
    Assignee: Oracle International Corporation
    Inventors: Sebastian Turullols, Vijay Srinivasan, Changku Hwang
  • Patent number: 9692362
    Abstract: An amplifier circuit applied to a source driver of a display apparatus includes a first input terminal, a second input terminal, an operational amplifier, an output stage and an output terminal. The first input terminal receives a first input signal. The second input terminal receives a second input signal. The operational amplifier is coupled to the first input terminal and second input terminal and receives the first input signal and second input signal and outputs a first control signal and a second control signal respectively. The output stage includes a first BJT and a second BJT coupled in series between a first terminal and a second terminal. The first BJT and second BJT are coupled to the operational amplifier and receive the first control signal and second control signal respectively. The output terminal is coupled between the first BJT and second BJT and outputs an output signal.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: June 27, 2017
    Assignee: Raydium Semiconductor Corporation
    Inventors: Yu-Chun Lin, Yung-Hsiang Yang
  • Patent number: 9685937
    Abstract: A CMOS pulse shrinking or stretching device includes a basic element sequence, including odd combination positions and even combination positions, and homogeneous logic elements connected to form the basic element sequence. The device further includes an inhomogeneous logic element serially connected between two of the basic elements at the odd or even combination position for shrinking or stretching a pulse signal. A CMOS pulse shrink-and-stretch mixing device further includes an inhomogeneous logic element set, including an odd-positioned inhomogeneous logic element and an even-positioned inhomogeneous logic element to combine stretching and shrinking functions of the pulse signal by adding a stretched pulse and a shrunk pulse signal together.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 20, 2017
    Assignee: National Kaohsiung First University of Science and Technology
    Inventor: Chun-Chi Chen
  • Patent number: 9665118
    Abstract: A semiconductor apparatus includes a controller configured to generate a plurality of control signals for selecting an operation mode of the semiconductor apparatus in response to a number of input chip enable pulses, and an output driving unit configured to be operated according to the operation mode of the semiconductor apparatus based on the plurality of control signals.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: May 30, 2017
    Assignee: SK hynix Inc.
    Inventor: Sang Hwan Kim
  • Patent number: 9651983
    Abstract: A clock generation device and a semiconductor device including the same are disclosed, which may tune an internal clock to a desired frequency. The clock generation device may include an oscillator configured to tune an oscillation signal in response to a tuning signal, and adjust a period of an internal clock. The clock generation device may include a counter configured to count the internal clock in response to a count enable signal, and output a count signal. The clock generation device may include a comparator configured to compare the count signal with a test count signal including a target count number of the internal clock, and output the tuning signal.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: May 16, 2017
    Assignee: SK hynix Inc.
    Inventors: Min Su Park, Jae Il Kim
  • Patent number: RE48735
    Abstract: The resolution of a time to digital converter (TDC) is improved by using a gain stage at the input of the fine TDC. A delay line receives a pulse corresponding to the time information and recirculates the pulse in the delay line by coupling an output of the delay line to an input of the delay line. An integrating fine TDC receives a number of pulses from the delay line corresponding to the desired gain.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: September 14, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Raghunandan Kolar Ranganathan