Abstract: A trigger signal detection apparatus includes: a clock gating circuit which is supplied with a trigger signal and a clock signal and outputs the clock signal; a trigger signal processing circuit which outputs a first signal only for a predetermined time when the clock signal is supplied from the clock gating circuit; a counter which operates in response to the trigger signal, thus outputting a count value of the clock signal; and a time set-up circuit which outputs a second signal to the trigger signal processing circuit when count value supplied from the counter reaches a preset value, and the trigger signal processing circuit stops outputting the first signal when the trigger signal processing circuit receives the second signal.

Abstract: A trigger signal detection apparatus includes: a clock gating circuit which is supplied with a trigger signal and a clock signal and outputs the clock signal; a trigger signal processing circuit which outputs a first signal only for a predetermined time when the clock signal is supplied from the clock gating circuit; a counter which operates in response to the trigger signal, thus outputting a count value of the clock signal; and a time set-up circuit which outputs a second signal to the trigger signal processing circuit when count value supplied from the counter reaches a preset value, and the trigger signal processing circuit stops outputting the first signal when the trigger signal processing circuit receives the second signal.

Abstract: A multi-port circuit and corresponding method for simultaneous shaping of sub-nanosecond pulses (MCS3P). The MCS3P includes a coupled-line coupler, a Schottky detector diode, and circuitry for compressing the rising and falling edges of a waveform. The MCS3P simultaneously produces square wave, Gaussian, and monocycle waveforms by differentiating a sinusoidal source. The method includes the steps of compressing the rising edge of a sinusoidal source waveform, differentiating the resulting waveform to form a square waveform and a Gaussian waveform, filtering out the positive going Gaussian to produce a negative going Gaussian, differentiating the Gaussian waveform to form a monocycle waveform, and compressing the falling edge of the square waveform to produce a square wave form with both edges compressed.

Abstract: A fast masked summing comparator apparatus includes a comparator unit configured to compare a masked first number to a masked sum of a second number and a third number to determine whether the masked sum is equivalent to the masked first number without performing a summation portion of an addition operation between the second number and the third number. The comparator unit may concurrently mask both the sum and the first number using the same mask value.

Abstract: A circuit arrangement for detecting unwanted signals on a clock signal comprises an input for receiving the clock signal, and a Phase Lock Loop PLL circuit having a reference input coupled to the input of the circuit arrangement for receiving the clock signal and an output for providing a PLL output signal. The circuit arrangement further comprises a detector coupled to the output of the PLL circuit and to the input of the circuit arrangement. The detector is arranged to identify correct transitions in the clock signal using the PLL output signal, and to remove incorrect transitions due to unwanted signals from the clock signal so as to provide a filtered clock signal at an output of the circuit arrangement.

Abstract: The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

Abstract: The present invention discloses an electric signal outputting apparatus in a serial electric transmission system. The electric signal outputting apparatus includes a switching part for switchably generating high and low output signals in accordance with signal data and transmitting the output signals to a transmission path, an impedance matching part for matching an output impedance to the impedance of the transmission path, and an auxiliary switching part for subsidiarily supplying current to an output node in the transmission path and subsidiarily absorbing current from the output node in the transmission path when the switching part switches the generation between high and low output signals, wherein the auxiliary switching part conducts the supplying and the absorbing for a period shorter than a pulse width of a reference clock of the serial electric transmission system.

Abstract: An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2?. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.

Abstract: The present subject matter is directed to a high-speed high resolution and accuracy time interpolator circuit. The interpolator uses basic dual ramp time-to-digital converter architecture, but provides circuits and methodologies to improve the accuracy, reduce the effective intrinsic jitter, and reduce the measurement time. Improved aspects of the present subject matter correspond to the introduction of a current mirror for improved settling time, a high frequency clock for improved resolution and ADC sample processing to improve resolution and accuracy.

Abstract: Control systems and methods for independent control of power systems, particularly lighting network branches, and separate control of individual branch components. Multi-branch systems comprise independently controllable branches that inter-communicate via PLC communications. In each branch, components such as ballasts, local control units, sensors, actuators, and repeaters, may exchange commands and queries independently of a branch remote control unit (BRCU). Alternatively, a BRCU may manage or arbitrate communications, or interact with other BRCUs, other control units and external management systems. Ballasts include a multi-channel ballast that enables close-loop control of individual fixtures, or of individual dimmable or non-dimmable lamps within a fixture. The close-loop control is facilitated by sampling circuits/sensors co-located with each controlled fixture or lamp. All controllers are preferably implemented using an integrated digital controller.

Abstract: Clock regulation apparatus for preventing a logic switching mechanism from operating incorrectly. The apparatus has a supply voltage input that receives a supply voltage, which is also applied to the logic switching mechanism, a comparison unit that outputs an error signal if the supply voltage value drops below a reference value, a clock signal input that receives a clock signal from a clock generator, and a clock suppression unit, which is coupled to the clock signal input and to the comparison unit, that has a clock output for outputting the clock signal and that suppresses or delays the clock signal for a duration of at least one clock period if the error signal exists.

Abstract: A circuit for a parity tree is disclosed. In one embodiment, a circuit for a parity tree includes a pull-up circuit, a pull-down circuit, and a cross-couple circuit. The circuit, an XOR/XNOR circuit, includes both an output node and an inverted output node. For a given set of input signals, a pull-up path exists through the cross-couple circuit for one of the output node and the inverted output node, and wherein a pull-down path exists through the cross-couple circuit for the other one of the output node and the inverted output node.

Abstract: An output driver may reduce coupling noise. The output driver may include a first transistor, a second transistor, and/or a noise-eliminating portion. The first transistor may have a first terminal connected to a first voltage, a second terminal connected to a first node, and a gate to which data is applied. The second transistor may have a first terminal connected to the first node and a second terminal connected to an output node. The noise-eliminating portion may be connected between the gate of the first transistor and a gate of the second transistor. The noise-eliminating portion may be a capacitor. The capacitor may substantially eliminate coupling noise introduced at the gate of the second transistor, due to coupling capacitance between the gate of the second transistor and the output node and coupling capacitance between the gate of the second transistor and the first node, by using the data applied to the gate of the first transistor.

Abstract: A preferred embodiment includes a distributed network of a plurality of dynamically configurable bi-directional input/output (I/O) cells, each including a forward datapath having a first receiver, for receiving a first input signal from downstream driver on a first port of a signal line, coupled to a first driver for sending a first output signal to a first upstream receiver on a second port of the signal line; and a reverse datapath having a second receiver, for receiving a second input signal from a second downstream driver on the second port of the signal line, coupled to a second driver for sending a second output signal to a second upstream receiver on the first port of the signal line; wherein the first input signal and the second output signal are transmitted concurrently on the first port of the signal line.

Abstract: The present invention provides a semiconductor device a comprising: a delayed-signal-generating circuit for delaying a reference pulse signal by a delay time caused by a delay component on a critical path of a target circuit by a selector included in the delayed signal generating circuit and, thereby, generating a delayed pulse signal; a detection-signal-generating circuit, having the same delay component as the selector, for generating a detection pulse signal delayed in phase by one cycle of a clock signal Ck with respect to the reference pulse signal; a delay-difference-detecting circuit for detecting a phase difference between the delayed pulse signal and the detection pulse signal; and a control circuit for adjusting the magnitude of a power-supply voltage VDD supplied to the target circuit according to the-phase difference detected by the delay-difference-detecting circuit.

Abstract: Load-monitoring feedback is used to maintain the slew rate of a line driver circuit at a prescribed rate that is independent of the effective load of the line being driven. This load-monitoring feedback control makes it possible to drive the line with an amplified output signal that faithfully tracks the input signal and conforms with prescribed slew rate and rise/fall time specifications, irrespective of characteristics of the signal line, which may vary over a specified range of component values. In a first embodiment, slew rate control is effected by increasing or decreasing the amount of charge on a reference capacitor and thereby the drive current to an output driver FET, in accordance with the change in state of the output of an output terminal-monitoring voltage threshold comparator relative to termination of a prescribed (one-shot established) time window.

Abstract: A simultaneous bi-directional input/output (I/O) circuit (300) is disclosed. The I/O circuit (300) includes an output buffer (302) for driving a data bus line (306) high or low according to a data input signal (Din), and an input buffer (308) for sensing the voltage on the data bus line (306). The input buffer (308) drives a data output node (332) between logic levels by comparing the voltage on the data bus line (306) with a reference voltage (Vref1 or Vref2) that is determined by the data input signal (Din). To eliminate glitches at the data output node (332) caused by the reference voltages switching faster than the data bus line can be driven (306), a transition detector (314) is provided that generates a disable pulse when Din transitions between logic levels.

Abstract: Disclosed are a phase detector for detecting the phase difference between a data signal and a clock signal, and a timing extracting circuit for controlling the phase of the clock signal so that the phase relationship between the clock signal and the data signal is optimal by using the phase detector. The phase detector includes an edge detector for generating an edge signal at the rising edge and the falling edge of the data signal, and a D flip flop (D-FF) for storing and outputting the logical value of the clock signal at the time of generation of the edge signal, and holding the logical value until the generation of the next edge signal, thereby outputting a signal corresponding to the phase difference between the data signal and the clock signal. A clock generator in the timing extracting circuit having a PLL structure controls the phase of the clock signal so that the difference becomes optimal.

Abstract: In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is disposed in parallel with the CMOS logic circuit. The constant-voltage auxiliary circuit receives an output signal from the CMOS logic circuit. The constant-voltage auxiliary circuit consumes power when the output signal from the CMOS logic circuit is stable to maintain a potential difference between the power-source line and the ground line at a specified voltage and halts power consumption when the output signal from the CMOS logic circuit is inverted, i.e., when the potential difference is decreasing, thereby suppressing the decrease of the potential difference. Accordingly, voltage fluctuations on the power-source line are suppressed.

Abstract: A programmable delay circuit employs a comparator to control an output driver. The comparator compares a ramp signal to an error control signal derived from an error amplifier or in the alternative to a disable signal. The output of the comparator is latched on until a reset signal is received. The reset signal is produced when the ramp signal is discharged below a predetermined level. The programmable delay circuit is useful in a secondary side post regulator to control a totem pole driver. The totem pole driver in turn controls a switching device coupled to a voltage on a secondary winding.

Abstract: A programmable delay circuit employs a comparator to control an output driver. The comparator compares a ramp signal with a disable signal or an error control signal derived from an error amplifier. The comparator latches the output on until a reset signal is received. The reset signal is produced when the ramp signal is discharged below a predetermined level. The programmable delay circuit is useful in a secondary side post regulator to control a grounded totem pole driver. The totem pole driver in turn controls a switching device coupled to a voltage on a secondary winding.

Abstract: A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recover clock signal (34) from the phase locked loop (13) and a latching flip flop (26) is set to provide a lock indication output (30) as long as repeated samples, taken at a test time (38) continue to indicate a zero level (42) of the recover clock signal (34). The test time (38) is the leading edge (40) of a reference clock signal (36) provided from an external source at a reference clock input (28) to the integrated circuit (12).