Abstract: A VCO (voltage-controlled oscillator) that can realize stable oscillation operation over a broad frequency range with a low level of jitter. The VCO includes a plurality of basic cells having differential input/output, and a center frequency adjustment circuit. The plurality of basic cells are serially connected in a ring. Each basic cell includes a circuit constituted by two delay circuits and an adder circuit, the delay times of the two delay circuits being each independently determined by the center frequency adjustment circuit. The output amplitude of each of the basic cells is controlled to a fixed value. In the adder circuit, the output of one of the delay circuits is multiplied by an addition proportion coefficient, following which the outputs of both delay circuits are added. In this way, the delay time for each basic cell can be set over a broad range.

Abstract: The delay element consists of a differential amplifier (M15, M8, M2, M6, M5) in which the load transistors (M2, M5) are associated to respective gate biasing transistors (M21, M22) connected in a source follower configuration, and to feedback transistors (M3, M4), which implement a negative impedance in parallel to a positive impedance represented by each of the load transistors (M2, M5). The modulation of the delay is achieved by modulating the bias currents of the load transistors (M2, M5), the feedback transistors (M3. M4) and the gate biasing transistors (M21, M22).

Abstract: A time delay apparatus using a transfer conductance. The time delay apparatus using an all-band pass filter can constitute the all-band pass filter having a required time delay with maintaining a frequency gain of an input signal by using a transfer conductance and the low frequency pass filter and easily control an amount of the time delay by varying the transfer conductance of the MOS transistor from outside.

Abstract: A feedforward circuit structure with programmable zeros for synthesizing continuous-time filters, delay lines, and the like is described. The circuit comprises a first cell and a second cell which are cascade-connected. Each one of the first and second cells comprises first and second pairs of bipolar transistors. The emitter terminals of the first pair of transistors are connected to a first current source, and the emitter terminals of the second pair of transistors are connected to a second current source. A first high-impedance element is connected between the first and second pairs of transistors, and a second high-impedance element is connected at an output of the second pair of transistors. A fifth transistor is connected between the collector terminal of a first transistor of the first pair of transistors and the collector terminal of a second transistor of the second pair of transistors.

Abstract: An adjustable delay circuit, for a logic input signal, comprises circuitry for charging a capacitance at a first constant current when the logic signal switches to a first logic state; circuitry for discharging the capacitance at a second constant current when the logic signal switches to the second logic state; circuitry for stopping charging and discharging of the capacitance between the moment when the voltage across the capacitance reaches a high threshold or a low threshold and a subsequent switching of the logic signal; and a first comparator connected to switch the state of an output signal when the voltage across the capacitance crosses a third threshold included between the first and second thresholds.

Abstract: A speed path circuit includes a reference circuit and adjustable drive components that can be turned on or off to vary the speed path in order to meet minimum delay specification for the circuit. In an embodiment, one or more differential amplifiers are used to detect the strength of example circuit elements and generate a reference signal. An optional embodiment includes a mechanism for disconnecting the reference circuit to avoid any DC current drain. The invention may be used in a wide range of integrated circuits and may also be used in a programmable logic device (PLD). Reference circuits may be disconnected from a power source by using programmable logic elements.

Abstract: An apparatus and method for delaying a signal using a variable delay line circuit. A variable delay line circuit includes first and second delay lines, each including a plurality of delay elements. A multiplexer is coupled to respective outputs of the first and second delay lines and selectively couples the output of one of the first or second delay lines to an output of the multiplexer. A control circuit is coupled to the multiplexer and the first and second delay lines, and controls the multiplexer so as to produce a delayed signal at the multiplexer output using one of the first or second delay lines, and changes a delay factor of the other one of the first or second delay lines by varying a resistance and a current of one or more delay elements of the other one of the first or second delay lines.

Abstract: A CMOS delay circuit for differential signals is provided. By adjusting the amplitude of clamping voltages, the delay period may be adjusted to a desired level. By using a single constant current source to charge both output nodes, current consumption is reduced.

Abstract: A variable delay cell with a self-biasing load suitable for the implementation of a voltage controlled oscillator and other functions. Because the invention employs current steering between symmetric loads and fully differential voltage control, it is very fast relative to conventional methods and has reduced jitter and improved power supply noise rejection. Additionally, since the load is self-biasing, the need to externally generate a bias current for the load is eliminated. This significantly simplifies design. Also as the load readily self biases in response to changes in the bias current of the biasing transistor, desirable functionalities can be achieved merely by appropriately changing the bias current into the biasing transistor. Notably, the slew rate of both the rising and falling edge can be controlled in this way. Because the load provides a fully differential output, noise immunity as well as a 50% duty cycle is readily achieved.

Abstract: A variable delay circuit for a semiconductor memory device includes an input buffer for converting a digital input signal to an analog signal and buffering the resultant analog signal, an analog delay unit for delaying the analog signal outputted from the input buffer unit for a certain time, and an output buffer unit for converting the delayed analog signal to a digital signal and buffering the resultant digital signal. The analog delay unit is composed of a CMOS inverter, a plurality of operational transconductance amplifier-capacitor delay elements, and an output inverter, to form a second-order Bessel filter. An O.T.A and an inverter may be additionally provided between the plurality of O.T.A.'s for thereby decreasing a parasitic effect of the capacitors connected to the outputs of each of the plurality of O.T.A.'s in the analog delay unit.

Abstract: An analog delay circuit provide a current-dependent delay through two differential pairs of transistors operated in parallel, one with input resistors, the other without. Delay is varied through the delay stage by provision of complementary currents produced by a current DAC in response to digital code provided in a data bus. The complementary currents drive the differential pairs to various combinations of operations, which yields the desired variable delay.

Abstract: A ring oscillator comprising a cascade connection of two or several delay stages (31 to 33), wherein each delay stage comprises two differential pairs of two transistors (Q1, Q2; Q3, Q4; Q5, Q7). In the ring oscillator, the collector resistors and the emitter resistor of a traditional ring oscillator are replaced by coils (L1 to L6) in all stages.

Abstract: A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The differential amplifier provides a first output signal and a complementary second output signal at first and second nodes, respectively. The voltage clamping circuit is coupled between the first and second nodes to limit a peak-to-peak voltage swing of each of the first and second output signals. The current source is coupled to the differential amplifier and varies a bias current in accordance with a delay bias voltage.

Abstract: A composite load circuit for use within another circuit includes at least one amplifying transistor. The composite load circuit includes first and second transistors connected in parallel. Each load transistor has a gate that receives a common control voltage. Each load transistor also has a different turn-on threshold voltage. A resistor, connected in parallel with the load transistors, limits an effective impedance of the load transistors.

Abstract: A cascoded cmos differential delay element is described. The delay element provides a controlled delay useful in forming voltage controlled oscillators or other circuits. The delay element provides high gain enabling it to be useful in multistage delay element circuits. The circuit described includes cascoded complementary differential amplifiers and replicated bias clamps.

Abstract: A delay line having variable delay comprising apparatus for receiving an input clock signal and for providing an inverted and non-inverted version thereof, a plurality of serially connected inverter stages each for receiving and translating the inverted and non-inverted versions of the input clock signal, inverted and non-inverted outputs of each of the inverter stages except a last inverter stage in series being cross-connected to inputs of an immediately following inverter stage, and apparatus for shunting outputs of one of the inverter stages to a pair of output nodes.

Abstract: A GTL I/O transceiver circuit having a pulsed latch receiver. A pulse generator generates a first pulse and a second pulse within the first pulse in response to a rising edge of the bus clock. The first pulse turns on the differential amplifier of the receiver circuit just long enough to provide a valid amplifier output signal. The second pulse controls a tristate latch such that the value of the amplifier output signal is latched before the differential amplifier is turned off. The pulsed latch receiver turns the differential amplifier on for only a fraction of the period of the bus clock such that power dissipation of the pulsed latch receiver circuit is significantly reduced. By using the pulsed latch receiver in VLSI components having hundreds of I/Os, significant reduction in overall component power dissipation can be achieved and static DC power is eliminated. The GTL I/O transceiver is useful for interfacing VLSI CMOS components to a terminated bus.

Abstract: A delay circuit includes a first filter circuit responsive to an input signal and outputting a first output signal having first-order low pass characteristics with respect to the input signal, a second filter circuit responsive to the input signal and outputting a second output signal having first-order high pass characteristics with respect to the input signal, and a difference computing circuit responsive to the first and second output signals and outputting a difference signal therebetween as an output signal of the delay circuit. By the constitution, it is possible to reduce an attenuation factor irrespective of the input signal frequency and obtain a relatively long and easily changeable delay time in a wide frequency band.

Abstract: An array oscillator circuit is disclosed herein. The array oscillator circuit includes a plurality of ring oscillators, each ring oscillator having a plurality of buffer stages for generating output signals on a like plurality of oscillator output ports. Interconnections are provided between each of the plurality of ring oscillators and at least one other of the plurality of ring oscillators such that the plurality of ring oscillators oscillate at identical frequencies and such that the output signals on the each ring oscillator's plurality of oscillator output ports have a phase offset from the signals generated on corresponding ones of the other ring oscillator's oscillator output ports. A multiplexer provides an electrical connection to a selected one of the plurality of oscillator output ports of the plurality of ring oscillators.

Abstract: A control circuit for an insulated-gate semiconductor device (IGBT) 1 has a drive circuit 2, which is a series circuit constructed of an npn transistor 3 and a pnp transistor 4, and controls the switching operation of the IGBT 1 in response to an on/off signal 9S from a switching signal source 9. The control circuit includes a switching speed control means 10, a gate potential stabilizing npn transistor 20, and a stable operation extending means 30. The switching speed control means 10 gives predetermined slops to the rise and fall of the on/off signal 9S. The gate potential stabilizing npn transistor 20 is Darlington-connected to the pnp transistor 4 of the drive circuit 2 and has the emitter thereof connected to the source of the IGBT 1. The stable operation extending means 30 generates an on signal to the base of the gate potential stabilizing npn transistor 20 upon sensing a drop in the gate potential of the IGBT 1 to a threshold voltage thereof or less.

Abstract: A delay stage for a ring oscillator supplies a first output signal and a second output signal. Each of the first and second output signals has a peak-to-peak voltage swing. The first and second output signals are complementary to each other. The delay stage includes a differential amplifier for generating the first output signal and the second output signal and a voltage clamping circuit for limiting the peak-to-peak voltage swing of the first and second output signals. The voltage clamping circuit is coupled between the first output signal and the second output signal. The differential amplifier includes a first NMOS transistor and a second NMOS transistor for generating the first and second output signals. The differential amplifier also includes a first PMOS transistor and a second PMOS transistor coupled to (1) the first and second NMOS transistors and (2) the voltage clamping circuit for providing bias currents to the first and second NMOS transistors.

Abstract: A circuit and method for reducing voltage error when charging and discharging a storage capacitor (44) through a transmission gate (43). The storage capacitor (44) stores or holds a voltage coupled through the transmission gate (43) when the transmission gate (43) is disabled. The circuit comprises a clock generation circuit (47) providing complementary clock signals for enabling and disabling the transmission gate (43) and a charge negating transmission gate (46). The clock generation circuit (47) provides the complementary clock signals simultaneously to the transmission gates (43, 46). Alternate paths for dissipating channel charge of the transistors which comprise the transmission gate (43) are not formed by providing the complementary clock signals simultaneously. The channel charge is then canceled by the charge negating transmission gate (46) reducing voltage error on the storage capacitor (44).

Abstract: An inverter stage includes a supply voltage terminal and a reference potential terminal. An npn transistor has a base terminal for receiving an input signal, a collector terminal for supplying an output signal, and an emitter terminal. A controllable current source is connected between the emitter terminal of the transistor and the reference potential terminal. A series circuit of at least two diodes is connected between the supply voltage terminal and the collector terminal of the transistor. A symmetrical inverter stage assembly includes two of the inverter stages being connected in parallel with the emitters of the transistors of each of the inverter stages being connected to one another. A ring oscillator includes n (n.gtoreq.1) of the inverter stages connected in series. The inverter stages include first and last inverter stages, each of the inverter stages has an output and an input, and the output of the last inverter stage is connected to the input of the first inverter stage.

Abstract: First and second complementary input voltages control current flow through first and second switches (e.g. semiconductor devices) each respectively connected in first and second control circuits with a first constant current source. When the input voltages change, current starts to increase through one control circuit to produce increases in the voltage drop across an impedance (e.g. resistor) in such circuit. When a particular voltage difference is produced between the impedance voltage and an adjustable biasing voltage, a third switch (e.g. semiconductor device) closes to produce a first resultant voltage. The resultant delay in the third switch closure is dependent upon the adjustable magnitude of the biasing voltage. As the voltage increases across the impedance in the one control circuit, the voltage decreases across an impedance in the other control circuit, causing a second resultant voltage to be produced at a fourth switch (e.g. semiconductor device).

Abstract: In a semiconductor circuit device comprising a differential amplifier circuit, which is formed on a semiconductor substrate and which comprises first and second input terminals, and a circuit element formed on the semiconductor substrate and connected to one of the first and the second input terminals. A dummy circuit element is formed on the semiconductor substrate so as to adjoin the circuit element for forming between the dummy circuit element and the semiconductor substrate a dummy parasitic capacitor which is equivalent to a parasitic capacitor formed between the circuit element and the semiconductor substrate. The dummy circuit element is connected to another one of the first and the second input terminals.