Single Clock Output With Multiple Inputs Patents (Class 327/298)
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Patent number: 7043655Abstract: A clock architecture employing redundant clock synthesizers is disclosed. In one embodiment, a computer system includes first and second clock boards. The first clock board may act as a master, generating a system clock signal, while the second clock board acts as a slave. The first clock board may monitor a phase difference between a first crystal clock signal and a feedback clock signal. If the phase difference exceeds a limit, the first crystal clock signal may be inhibited, preventing the first clock board from generating the system clock signal. The second clock board may monitor the system clock board in reference to a feedback clock signal. If the second clock board detects a predetermined number of consecutive missing clock edges, it may enable a second crystal clock signal, which may be used to generate a system clock signal.Type: GrantFiled: November 6, 2002Date of Patent: May 9, 2006Assignee: Sun Microsystems, Inc.Inventor: Chung-Hsiao R. Wu
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Patent number: 7038520Abstract: A timing signal generating circuit receives a plurality of input signals of differing phases and generates a timing signal having a phase intermediate therebetween. The timing signal generating circuit has a plurality of current polarity switching circuits, and a voltage level correction circuit. Each of the current polarity switching circuits is provided between a plurality of current sources and acts to switch an output current polarity in accordance with a corresponding one of the input signals. The voltage level correction circuit corrects the voltage level of a phase-combined signal produced by combining weighted outputs of the plurality of current polarity switching circuits.Type: GrantFiled: November 26, 2003Date of Patent: May 2, 2006Assignee: Fujitsu LimitedInventors: Takaya Chiba, Hirotaka Tamura
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Patent number: 7009436Abstract: The present invention provides one pulsewidth control loop (PWCL) device with complementary signals. The PWCL device includes one control stage circuit, one buffer chain, one complementary circuit, two charge pumps, and one comparator. The control stage circuit is used to receive a clock signal and the control signal of the comparator, and output a signal to the buffer chain. The buffer chain is used to receive the output signal from the control stage circuit and output a signal to the complementary circuit. The complementary circuit is used to receive the output signal from the buffer chain and output two complementary signals. Each of the two charge pumps is used to receive one of the output signals from the complementary circuit and output a signal to be one of the inputs of the comparator. The comparator is used to receive the output signals from each of the two charge pumps. Then, the comparator outputs a signal and feedbacks to be one of the input signals of the control stage circuit.Type: GrantFiled: April 9, 2004Date of Patent: March 7, 2006Assignee: Pericom Technology (Shanghai) Co., Ltd.Inventors: Hong-Yi Huang, Wei-Ming Lin
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Patent number: 7009430Abstract: A circuit for generating a pixel clock for use in scanning a laser beam includes a high-frequency-clock generating circuit which generates a high-frequency clock having a higher frequency than the pixel clock, and a control circuit which generates the pixel clock while shifting a phase of the pixel clock by a shift step proportional to a clock cycle of the high-frequency clock in response to phase data indicative of timing and amounts of phase shifts.Type: GrantFiled: February 5, 2004Date of Patent: March 7, 2006Assignee: Ricoh Company, Ltd.Inventors: Yasuhiro Nihei, Masaaki Ishida, Atsufumi Omori, Dan Ozasa
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Patent number: 7005905Abstract: A circuit capable of providing stable timing clock includes: a step-down clamping circuit, an oscillating circuit, and a voltage potential-conversing circuit. The step-down clamping circuit that step down the input first voltage potential, and clamp to output second voltage, the oscillating circuit is coupled to the clamping circuit and is an oscillating circuit that takes the second voltage as a operating voltage to generate a first timing clock signal, which has a lower voltage potential. The voltage potential-conversing circuit is coupled to the oscillating circuit to convert the first timing clock signal into a second timing clock signal, which has a higher voltage potential. And it is a stable timing clock signal available for other system circuit.Type: GrantFiled: February 20, 2004Date of Patent: February 28, 2006Assignee: Holtek Semiconductor Inc.Inventors: Chi-Ho Hsu, Chi-Bing Chen, Hsan-Fong Lin, Chia-Lu Hsu
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Patent number: 7003683Abstract: A clock selection circuit for selecting between two clock sources. The clock selection circuit has two independent clock inputs, CLK1 and CLK2, where no assumptions are made regarding frequency or phase relationship between the two clocks inputs. Two asynchronous inputs, START1 and START2 (both active high), are used to start and stop the clocks. As long as one clock is active, the START signal of the other clock will not have any effect. The invention includes interlock circuitry that ensures that at any given time only one clock is enabled to the output. Disabling the corresponding START signal disables the clock signal.Type: GrantFiled: January 31, 2002Date of Patent: February 21, 2006Assignee: STMicroelectronics. Inc.Inventor: Srikanth R. Muroor
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Patent number: 6998883Abstract: A circuit and method are provided to enable the synchronization of an on-demand, synchronous signal with an asynchronous signal. The synchronous signal is activate only for a portion of the period of the asynchronous signal, thus providing beneficial power conservation. The synchronous signal is activated in response to a first edge of the asynchronous signal, and deactivated in response to a second edge of the asynchronous signal.Type: GrantFiled: February 25, 2004Date of Patent: February 14, 2006Assignee: Analog Devices, Inc.Inventor: Jonathan P. Skroch
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Patent number: 6982573Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.Type: GrantFiled: April 19, 2004Date of Patent: January 3, 2006Assignee: STMicroelectronics LimitedInventors: Matt Hutson, Andrew Dellow, Tom Ryan, Paul Elliott
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Patent number: 6975145Abstract: Described are glitchless clock control circuits capable of switching away from a failed clock. One embodiment supports three basic functions: clock select, clock enable, and clock ignore. The clock-select function provides a selected one of a plurality of clock signals on a clock-distribution node. The select signals used to switch between clock signals need to be synchronous with any of the clock signals. The clock-enable function allows the clock control circuit to synchronously block or pass a selected clock signal. Finally, the clock-ignore function allows the clock control circuit to ignore a selected clock if necessary, for example, to switch away from a failed clock.Type: GrantFiled: June 2, 2003Date of Patent: December 13, 2005Assignee: Xilinx, Inc.Inventors: Vasisht M. Vadi, Steven P. Young
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Patent number: 6967512Abstract: In a circuit block BL1, a PMOS transistor P1 and a PMOS transistor P1? are connected in series between a high-level potential HL and an output terminal U1; an NMOS transistor N1 and an NMOS transistor N1? are connected in series between a low-level potential LL and the output terminal U1. An inversion signal Ck1B of a clock signal Ck1 is inputted to the gate of the PMOS transistor P1; the inversion signal Ck1B of the clock signal Ck1 is inputted to the gate of the PMOS transistor P1? through an inverter IV1; a clock signal Ck2 is inputted to the gate of the NMOS transistor N1; and the clock signal Ck2 is inputted to the gate of the NMOS transister N1? through an inverter IV2.Type: GrantFiled: December 26, 2002Date of Patent: November 22, 2005Assignee: Seiko Epson CorporationInventor: Minoru Kozaki
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Patent number: 6960952Abstract: The pre-driver of an output driver is calibrated so as to generate output signals having a specified duty cycle. During calibration, a closed loop is utilized to decrease the differences between the common mode voltage of the output signal and a reference voltage. Calibration data is be stored in registers so that the output driver can be readily configured for one of a plurality of signaling types, each having a respective duty cycle. Additionally, a process, voltage and temperature (PVT) detector can be utilized so that calibration of the pre-driver tracks with process, voltage and temperature variations of the integrated circuit in which the output driver resides.Type: GrantFiled: September 11, 2003Date of Patent: November 1, 2005Assignee: Rambus, Inc.Inventors: Huy Nguyen, Benedict Lau, Chuen-Huei Chou
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Patent number: 6927604Abstract: A clock signal selector circuit is disclosed including a synchronizer circuit, two switching circuits, and a multiplexer. The synchronizer circuit synchronizes a first control signal to a first clock signal, thereby producing a second control signal. A first switching circuit produces the first clock signal at a first node when the second control signal is asserted. The multiplexer drives a second node with a signal at the first node when the second control signal is asserted. The second switching circuit forms an electrical connection between the first and second nodes when the second control signal is deasserted. The two switching circuits significantly reduce a probability of error at the second node due to metastability when the second control signal transitions from asserted to deasserted and the first clock signal is deselected. The second switching circuit provides electrical feedback from the second node to the first node.Type: GrantFiled: August 21, 2003Date of Patent: August 9, 2005Assignee: International Business Machines CorporationInventors: David W. Boerstler, Eskinder Hailu
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Patent number: 6927639Abstract: Method and related apparatus for realizing frequency-multiplication by generating a high frequency signal according to a plurality of low frequency signals. The method includes: according to a plurality output signals generated by a phase-locked loop (PLL) or a delay-locked loop (DLL), generating a plurality of reference signals with a same frequency and different phases; when a number of the reference signals with signal level high is greater than a number of the reference signals with signal level low, making a signal level of the output signal remains a first level; otherwise, making the signal level of the output signal remains a second level substantially different from the first level. Thus the frequency of the output signals is a multiplication of the frequency of the input signals.Type: GrantFiled: September 30, 2003Date of Patent: August 9, 2005Assignee: ALI CorporationInventor: Yu-Chen Chen
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Patent number: 6914852Abstract: An apparatus and method for generating a plurality of synchronizing signals for synchronizing operation of the device in which the apparatus is located, such as in semiconductor memory devices. The apparatus can generate a plurality of synchronizing signals based on a corresponding plurality of input clock signals and select one of the synchronizing signals to be provided as the synchronizing clock signal. Alternatively, the apparatus can generate a plurality of internal clock signals based on an input clock signal, and generate a corresponding plurality of synchronizing signals from the plurality of internal clock signals. One of the synchronizing signals is selected by the apparatus as the synchronizing clock signal. Alternatively, the apparatus can receive a clock signal, generate a synchronized clock signal therefrom, and generate a synchronizing pulse in response to number of periods of the synchronized clock signal, the number based on a selection signal provided to the apparatus.Type: GrantFiled: April 28, 2004Date of Patent: July 5, 2005Assignee: Micron Technology, Inc.Inventor: Joo S. Choi
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Patent number: 6891401Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.Type: GrantFiled: August 5, 2002Date of Patent: May 10, 2005Assignee: Altera CorporationInventors: Greg Starr, Edward Aung
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Patent number: 6882184Abstract: A clock switching circuit has a clock output circuit and clock signal transfer circuits. The output circuit provides a selected clock signal. The transfer circuits receive input clock signals and select signals, and output transfer signals to the output circuit. Each of the transfer circuits includes a transmitting circuit, a generating circuit and a passing circuit. The transmitting circuit is connected to the output circuit, and receives the select signal and provides the received select signal responsive to the selected clock signal. The generating circuit is connected to the transmitting circuit, and provides an internal select signal responsive to the received select signal and the input clock signal. The passing circuit is connected to the generating circuit and the output circuit, and provides the input clock signal to the output circuit responsive to the internal select signal.Type: GrantFiled: June 9, 2003Date of Patent: April 19, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Atsushi Yamazaki
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Patent number: 6879201Abstract: A glitchless T length pulse is generated by coupling a trigger signal and the latched output of a counter. The trigger signal initiates the start of the T length pulse, and the latched output of the counter initiates the end of the T length pulse after counting up a duration of T from a number of clock cycles of a clock signal. Latching the output of the counter prior to terminating the T length pulse eliminates glitches. Accuracy of the count determining the length of the T length pulse may be increased by latching the trigger signal with the clock signal to generated a synchronized trigger signal, and using the synchronized trigger signal to initiate the T length pulse.Type: GrantFiled: April 1, 2002Date of Patent: April 12, 2005Assignee: Xilinx, Inc.Inventor: Siuki Chan
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Patent number: 6867626Abstract: A clock synchronization circuit includes a first delay circuit for delaying a clock signal and outputting the delayed clock signal, first and second bidirectional delay circuit strings, a first pre-stage delay circuit and a first post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the first bidirectional delay circuit string (BDDA), a second pre-stage delay circuit and a second post-stage delay circuit of variable delay time type, arranged in a pre-stage and a post-stage of the second bidirectional delay circuit string (BDDB), and a multiplexer, supplied with and multiplexing outputs of the first and second post-stage delay circuits to output the resulting signals. An output signal of the first delay circuit is supplied in common to the first and second pre-stage delay circuits.Type: GrantFiled: July 22, 2003Date of Patent: March 15, 2005Assignee: Elpida Memory, Inc.Inventor: Yoji Idei
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Patent number: 6864735Abstract: An apparatus and method for regenerating reset and clock signals and a high-speed digital system using the apparatus and method are provided. In the regenerating circuit of the invention, a clock circuit receives an external clock signal and generates there from an internal clock signal, which is forwarded to a plurality of clocked circuits such as, for example, D flip-flops. A reset circuit receives an external reset signal and generates therefrom an internal reset signal, which is forwarded to the clocked circuits to reset the clock circuits. A clock masking circuit masks the internal clock signal for a masking period such that the clocked circuits are not clocked during the masking period. The high-speed digital system of the invention includes a plurality of function blocks coupled on a bus. The reset and clock regenerating circuit of the invention generates internal reset and clock signals from externally applied reset and clock signals.Type: GrantFiled: September 18, 2003Date of Patent: March 8, 2005Assignee: Samsung Electronics Co., Ltd.Inventor: Jin-tae Joo
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Patent number: 6865135Abstract: An apparatus and method for generating a plurality of synchronizing signals for synchronizing operation of the device in which the apparatus is located, such as in semiconductor memory devices. The apparatus can generate a plurality of synchronizing signals based on a corresponding plurality of input clock signals and select one of the synchronizing signals to be provided as the synchronizing clock signal. Alternatively, the apparatus can generate a plurality of internal clock signals based on an input clock signal, and generate a corresponding plurality of synchronizing signals from the plurality of internal clock signals. One of the synchronizing signals is selected by the apparatus as the synchronizing clock signal. Alternatively, the apparatus can receive a clock signal, generate a synchronized clock signal therefrom, and generate a synchronizing pulse in response to number of periods of the synchronized clock signal, the number based on a selection signal provided to the apparatus.Type: GrantFiled: March 12, 2003Date of Patent: March 8, 2005Assignee: Micron Technology, Inc.Inventor: Joo S. Choi
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Patent number: 6842052Abstract: A system for allowing an asynchronous clock signal to be selected from a plurality of asynchronous clock signals without causing glitches. In the system, a requestor is connected to control signals. The control signals indicate to the requestor which asynchronous clock signal, of the two or more clock signals, to request. The requestor informs a selector of the request. The selector determines which asynchronous clock signal was selected. The selected asynchronous clock is then detected by the detector. The detector feeds the selected asynchronous clock signal to a signal output. The signal output releases the selected asynchronous clock signal.Type: GrantFiled: June 11, 2002Date of Patent: January 11, 2005Assignee: VIA-Cyrix, Inc.Inventor: William V. Miller
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Patent number: 6832327Abstract: A processor-based system such as a workstation or server, using a system clock provided through a phase-locked loop (PLL) to a clock gate and then to a clock tree, which distributes the core system clock to components in the processor-based system, including a host bridge circuit. The host bridge distributes control signals to a receiving device such as a memory module, which may use a continued clocking signal when the system enters a low-power mode. A feedback clock for the PLL is provided to the receiving devices during low-power mode to ensure continued clocking, when the clock gate output is low and the clock tree is thereby disabled. A skew compensation circuit coordinates clocking in the continued clock and the core system clock.Type: GrantFiled: October 2, 2001Date of Patent: December 14, 2004Assignee: Advanced Micro Devices, Inc.Inventors: James R. Magro, Michael S. Quimby
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Publication number: 20040222836Abstract: One embodiment is a clock gater circuit comprising an inverter block for driving an output clock signal responsive at least in part to an input clock signal that is selectively driven via a clock generator circuit to an input node of the inverter block responsive to a qualifier signal. Also included is circuitry for restoring a logic level at the input node of the inverter block to a particular value, the circuitry operating responsive to the qualifier signal.Type: ApplicationFiled: June 15, 2004Publication date: November 11, 2004Inventor: Erin Dean Francom
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Patent number: 6809556Abstract: A glitch free self-correcting clock switching mechanism operative to switch between two clocks in a glitch free manner while compensating for the ambiguity inherent in the switching operation. During the switching from fast to slow clock domains the mechanism measures the uncertainty or ambiguity of the first slow clock cycle duration during the switching operation and stores this value. At some time later, during the slow to fast clock switching the clock switch mechanism compensates for the metastability of the first slow clock cycle during fast to slow switching using the ambiguity value previously measured. In this manner the fast and slow clocks are switched between each other in a glitch-free and self compensating manner.Type: GrantFiled: September 4, 2003Date of Patent: October 26, 2004Assignee: Texas Instruments IncorporatedInventors: Alexander Bronfer, Svetlana Slotzkin
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Patent number: 6806755Abstract: A technique for glitchless switching among different frequency input clocks in a circuit includes monitoring each of the clocks and determining when the relative phases of the respective clocks are within a predetermined maximum of phase difference. Once the relative phases of the respective clocks are within an acceptable range, the system switches from one clock to another.Type: GrantFiled: April 10, 2003Date of Patent: October 19, 2004Assignee: Quantum 3DInventor: Alan Christopher Simmonds
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Patent number: 6803796Abstract: The present invention is to provide a multiple phases switching circuit which is operable with a multiple phase signal generator and a succeeding circuit. The multiple-phase signal generator generates N multiple-phase clock signals. Phases of the multiple-phase clock signals are different. The multiple phases switching circuit comprises an alternative signal generator and a multiplexer. The alternative signal generator outputs an alternative signal according to an up/down switching signal. The multiplexer is coupled to the alternative signal generator for receiving the multiple-phase clock signals and proceeding a glitch/spike preventing process according to the alternative signal so as to output a target clock signal to the succeeding circuit.Type: GrantFiled: May 28, 2002Date of Patent: October 12, 2004Assignee: Realtek Semiconductor Corp.Inventors: Chen-Chih Huang, Pao-Cheng Chiu
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Patent number: 6801074Abstract: A clock switching circuit is provided for switching from a first clock signal being output to a freely selected second clock signal among a plurality of clock signals having different frequencies and phases while preventing generation of a hazard. The switching circuit has a plurality of unit circuits for respectively receiving as an input the clock signals, selection signals of the clock signals and enabling signals and controls supplying and stopping of the clock signals in accordance with the selection signals and the enabling signals. A feedback circuit monitors output conditions of the plurality of unit circuits and, when outputting of all clock signals of the plurality of unit circuits was stopped as a result of stopping the first clock signal, giving a plurality of the unit circuits the enabling signal for approving starting of a supply of the second clock signal.Type: GrantFiled: July 15, 2003Date of Patent: October 5, 2004Assignee: Sony CorporationInventor: Tetsumasa Meguro
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Patent number: 6794910Abstract: The invention relates to a method and circuit for synchronizing two signals triggered by clocks of different frequencies, which samples the lower frequency write-enable signal at both positive and negative edges of the higher frequency clock. If the sampling result at the positive or negative edge of the higher frequency clock is “1”, the state is recorded to be a “lock state” and no sampling is taken from the next opposite edge. If the sampling result at the positive or negative edge is “0”, the state is recorded to be a “sampling state” and the next opposite edge will be sampled. Finally, the sampling results taken at the positive and negative edges are joined to output a synchronized write-enable signal.Type: GrantFiled: July 10, 2003Date of Patent: September 21, 2004Assignee: Cheerteck, Inc.Inventor: Chia-yow Yeh
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Patent number: 6788127Abstract: A circuit for variably delaying a serial digital data signal delays a parallel data clock rather than the serial digital data signal directly. A delay circuit receives the parallel data clock to provide a delayed parallel data clock, the delay being a function of a control signal. A phase-locked loop receives the delayed parallel data clock to generate a serial data clock in phase with the delayed parallel data clock. A parallel-to-serial converter reads an n-bit parallel digital data signal from a memory using the delayed parallel data clock, and converts the parallel digital data signal to the serial digital data signal using the serial data clock. By changing the control signal continuously, the delay of the delayed parallel data clock and of the serial digital data signal also changes continuously so the serial digital data signal appears to have jitter.Type: GrantFiled: May 28, 2003Date of Patent: September 7, 2004Assignee: Tektronix International Sales GmbHInventor: Norihiko Sato
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Patent number: 6784716Abstract: A clock generation circuit for generating clocks having a plurality of frequencies by which a suitable frequency for each task can be supplied such that the power consumption is reduced. A clock generation unit is provided for generating a clock with a constant frequency, with a counter operating in synchronization with the clock for counting pulses of the clock, a comparator for comparing a counter value of the counter with the number of pulses of a clock having a desired frequency, and an output gate for controlling the supply and stopping of pulses of the clock input from the clock generation unit based on a comparison result of the comparator.Type: GrantFiled: May 6, 2003Date of Patent: August 31, 2004Assignee: Sony CorporationInventor: Tetsumasa Meguro
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Patent number: 6784709Abstract: A clock generator to produce internal clock signals with a controlled pulse width in a synchronous semiconductor memory device. The clock generator includes a clock input circuit receiving an external clock signal, a reference voltage signal and an option signal, and outputting first and second clock signals; a clock driver receiving the first clock signal and outputting an internal clock signal in response to the option signal; and a detector receiving the second clock signal and outputting the option signal in response to a control signal.Type: GrantFiled: July 22, 2002Date of Patent: August 31, 2004Assignee: Hynix Semiconductor Inc.Inventor: Je-Hun Ryu
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Patent number: 6774681Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.Type: GrantFiled: May 29, 2002Date of Patent: August 10, 2004Assignee: STMicroelectronics LimitedInventors: Andrew Dellow, Paul Elliott
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Patent number: 6750693Abstract: A clock generator circuit includes a counter which counts edges of a received clock signal and a comparator which compares divide ratio control data with a count generated by the counter and generates an active state of a control signal in response. An output flip-flop toggles in response to the control signal and a selected edge of the received dock signal to toggle a state of an output clock signal.Type: GrantFiled: April 4, 2003Date of Patent: June 15, 2004Assignee: Cirrus Logic, Inc.Inventor: Bruce Eliot Duewer
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Patent number: 6745338Abstract: An apparatus comprising a circuit configured to automatically select a clock mode in response to a state of a clock input.Type: GrantFiled: September 12, 2000Date of Patent: June 1, 2004Assignee: Cypress Semiconductor Corp.Inventor: Timothy J. Williams
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Patent number: 6737904Abstract: A method of producing a clock signal with reduced electromagnetic interference spectral components includes providing a first clock signal; producing a second clock signal by delaying the first clock signal; and generating a jittered clock signal by switching between the first clock signal and the second clock signal at times selected responsive to a random number generator.Type: GrantFiled: November 12, 1999Date of Patent: May 18, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Remi Butaud, Bernard Ginetti
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Patent number: 6724231Abstract: A semiconductor integrated circuit including a clock signal propagation gate capable of reducing clock signal skew and controlling a clock signal is provided. The clock signal inputted at a clock origin propagates through buffers (30, 31) to a clock propagation control gate (32). The two-level clock propagation control gate (32) includes an inverter at the first level, and a NAND gate at the second level. The clock signal passed through the clock propagation control gate (32) propagates through buffers (33, 34) to reach a sequential circuit (35) at an end point. The NAND gate (39) at the second level of the clock propagation control gate (32) includes nMOS transistors (42, 43) and pMOS transistors (40, 41). The inverter (36) at the first level includes a pMOS transistor (37) and an nMOS transistor (38).Type: GrantFiled: January 14, 2003Date of Patent: April 20, 2004Assignee: Renesas Technology Corp.Inventor: Atsushi Yoshikawa
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Publication number: 20040036520Abstract: A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.Type: ApplicationFiled: August 29, 2003Publication date: February 26, 2004Applicant: Intel CorporationInventors: Mark A. Anders, Ram K. Krishnamurthy, Krishnamurthy Soumyanath
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Patent number: 6696876Abstract: A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.Type: GrantFiled: January 12, 2001Date of Patent: February 24, 2004Assignee: Sun Microsystems, Inc.Inventors: Robert J. Drost, Robert J. Bosnyak
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Patent number: 6693477Abstract: A clock circuit comprises an analog clock element, a digital clock element, and a controller. The analog clock element is configured to generate an oscillating output. The digital clock element is configured to generate a digital clock output. The controller is configured to switch between the analog clock element and the digital clock element. The oscillating output and the digital clock output have substantially equivalent frequencies.Type: GrantFiled: October 22, 2001Date of Patent: February 17, 2004Assignee: Research in Motion LimitedInventors: Mark A. J. Carragher, John W. Wynen
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Patent number: 6671220Abstract: A semiconductor device includes input circuits which capture respective data pieces from an exterior of the device in synchronization with respective clock signals supplied from the exterior of the device, a pulse signal generation circuit which generates a pulse signal, and drive circuits which supplies the respective data pieces captured by the input circuits to internal circuitry at a unified timing corresponding to the pulse signal.Type: GrantFiled: March 13, 2002Date of Patent: December 30, 2003Assignee: Fujitsu LimitedInventors: Akira Kikutake, Satoshi Eto
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Patent number: 6661269Abstract: The present invention provides a mechanism for combining programming signals to provide an output signal, the properties of which depend only on selected properties of the programming signals. An embodiment of the invention includes first and second edge-to-pulse converters. The first edge-to-pulse converter generates an intermediate signal having a width determined by received initiation and termination signals. The second edge-to-pulse converter generates an output signal, responsive to the intermediate signal and the termination signal. The output signal has a width determined by a first edge of the initiation signal and a first edge of the termination signal.Type: GrantFiled: February 23, 2001Date of Patent: December 9, 2003Assignee: Intel CorporationInventors: Thomas D. Simon, Rajeevan Amirtharajah
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Patent number: 6653867Abstract: An apparatus and method is disclosed for providing a smooth transition between a first clock signal at a first frequency and a second clock signal at a lower second frequency. A pulse is generated that indicates whether the logic levels of the first and the second clock signals are similar or are different. The rising/falling edges of the pulse are synchronized with the rising/falling edges of the first clock signal. When a change in a logic level of a command signal for switching between the clock signals is detected, a first time period is identified in which the logic levels of the first and the second clock signals are different. The transition between the first clock signal and the second clock signal is allowed immediately after the first time period has ended.Type: GrantFiled: April 11, 2002Date of Patent: November 25, 2003Assignee: Advanced Micro Devices, Inc.Inventor: Elias Shihadeh
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Patent number: 6650160Abstract: A method (and structure) of generating a two step variable length delay, including passing an input clock signal through a plurality of serially-interconnected delay elements, each delay element having a delay time interval dtc, thereby generating a corresponding plurality delayed signals. A set of m (where m is an integer greater than 2) of the plurality of delayed signals is switably selected. The selected m delayed signals form a first to an mth coarse adjustment delay signals. An nth coarse adjustment delay signal leads an (n+1)th coarse adjustment delay signal in phase by a time interval dtc (n is an integer being 1 or more and (m−1) or less). From the first to mth coarse adjustment delay signals, 2m fine adjustment delay signals are generated, where a jth fine adjustment delay signal leads a (j+1)th fine adjustment delay signal in a phase by a time interval dtc′, where time interval dtc′ is finer than the time interval dtc.Type: GrantFiled: January 31, 2002Date of Patent: November 18, 2003Assignee: NEC CorporationInventor: Toshio Tanahashi
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Patent number: 6608528Abstract: A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.Type: GrantFiled: October 22, 2001Date of Patent: August 19, 2003Assignee: Intel CorporationInventors: Simon M. Tam, Stefan Rusu
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Patent number: 6606361Abstract: A circuit (10) for producing a single output data (DOUT) stream and a corresponding single clock signal (CLKOUT). This circuit comprises an input for receiving a single input data stream (DIN), where the input data stream has data words at a first frequency. This circuit further includes a plurality of clock inputs for receiving a plurality of corresponding clock signals (CLK0, CLK1), where each of the plurality of corresponding clock signals is synchronized to a corresponding plurality of the data words. This circuit still further includes an input for receiving a fast clock signal (CLKF), where the fast clock signal has a fast frequency greater than the first frequency. The circuit also includes various circuitry. This circuitry includes circuitry for sampling (L20, L21) the input data stream at the fast frequency, circuitry for outputting (M, LM) the sampled data as the single output data stream, and circuitry for outputting (CG) the single clock cycle in response to the fast clock signal.Type: GrantFiled: September 28, 1999Date of Patent: August 12, 2003Inventor: Anthony S. Rowell
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Patent number: 6600345Abstract: A clock selection circuit for selecting one of a plurality of clocks as an output clock. When the selection circuit switches between two of the plurality of clocks for output, the currently output clock is removed from the output. The removal of the currently output clock is performed synchronously to the currently selected clock. The newly selected clock is then coupled to the output. Coupling of the newly selected clock is performed synchronously to the newly selected clock.Type: GrantFiled: November 15, 2001Date of Patent: July 29, 2003Assignee: Analog Devices, Inc.Inventor: Frederic Boutaud
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Patent number: 6600354Abstract: A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.Type: GrantFiled: January 8, 2001Date of Patent: July 29, 2003Assignee: NEC CorporationInventor: Takanori Saeki
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Patent number: 6600355Abstract: A clock generator circuit accepts phased input clock signals having an input clock frequency, and generates from the phased signals an output clock signal having low jitter and a clock frequency created by dividing or multiplying the input clock frequency. In exemplary embodiments having four phased input signals and a duty cycle correction feature, a clock generator circuit provides output clock frequencies of the input clock frequency divided by X/2, where X is an integer. In other embodiments not having duty cycle correction, a clock generator circuit provides output clock frequencies of the input clock frequency divided by X/4. The delay through the clock generator circuit is minimal, and is independent of the divisor. Variations include programmable divisors and multipliers and optional phase shifting.Type: GrantFiled: June 10, 2002Date of Patent: July 29, 2003Assignee: Xilinx, Inc.Inventor: Andy T. Nguyen
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Patent number: 6597213Abstract: A digital frequency doubler circuit employs a stable reference clock signal, delayed by a reference delay line, to obtain information related to delay characteristics of a matching input delay line. An input clock signal is delayed by the input delay line, which provides a plurality of variously delayed input clock signals based upon the input clock signal. The reference delay line provides a plurality of variously delayed reference clock signals based upon the stable reference clock signal; the delayed reference clock signals convey information related to the operating characteristics of both delay lines. In response to such information, one of the delayed input clock signals can be selected as a delayed clock output. The reference and input delay lines are configured such that the delay circuit consistently generates a delayed clock output having an actual delay that falls within a specified range of delay.Type: GrantFiled: April 3, 2002Date of Patent: July 22, 2003Assignee: Applied Micro Circuits CorporationInventor: Sharon Lynn Weintraub
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Patent number: 6593791Abstract: A digital delay circuit employs a stable reference clock signal, delayed by a reference delay line, to obtain information related to delay characteristics of a matching input delay line. An input clock signal is delayed by the input delay line, which provides a plurality of variously delayed input clock signals based upon the input clock signal. The reference delay line provides a plurality of variously delayed reference clock signals based upon the stable reference clock signal; the delayed reference clock signals convey information related to the operating characteristics of both delay lines. In response to such information, one of the delayed input clock signals can be selected as a delayed clock output. The reference and input delay lines are configured such that the delay circuit consistently generates a delayed clock output having an actual delay that falls within a specified range of delay.Type: GrantFiled: April 3, 2002Date of Patent: July 15, 2003Assignee: Applied Micro Circuits CorporationInventor: Sharon Lynn Weintraub