Clock Or Pulse Waveform Generating Patents (Class 327/291)
  • Patent number: 10777118
    Abstract: A shift register and a method for driving the same, a gate driving circuit, and a display device, the shift register includes: a pull-up node control circuit allowing a potential of a pull-up node to become high according to a first input signal and a second input signal; a first capacitor coupled between a signal output terminal and the pull-up node of the shift register; a pull-down node control circuit controlling a potential of the pull-down node according to the second clock signal and the third clock signal and the potential of the pull-up node; an output circuit controlling an output of a gate driving signal at the signal output terminal; and a pull-down circuit allowing the potential of the pull-up node and a potential of the signal output terminal to become low.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 15, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xueguang Hao
  • Patent number: 10770003
    Abstract: A transfer circuit includes an input circuit, a reset circuit, an output circuit, and an output stabilizer circuit, and obtains an input signal at an input terminal, holds the input signal, and outputs the input signal from an output terminal as an output signal in synchronization with a clock signal. The transfer circuit includes an inverter circuit that has an input terminal connected to at least one of the input and output terminals of the transfer circuit, and outputs, from an output terminal, an inverted signal having an inverted polarity of at least one of the input and output signals. The reset circuit includes a first transistor having a control signal end connected to the output terminal of the inverter circuit, the first transistor switching continuity and discontinuity of a signal path between one end of a first capacitor that holds the input signal and a first power supply.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 8, 2020
    Assignee: JOLED INC.
    Inventor: Tetsuro Yamamoto
  • Patent number: 10727906
    Abstract: A near-field communication device includes an oscillating circuit, a rectifying bridge configured to rectify a voltage across the oscillating circuit, and a voltage-controlled oscillator configured to supply a reference frequency. The voltage-controlled oscillator is powered and controlled by a voltage that is a function of an output voltage of the rectifying bridge.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 28, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Tramoni
  • Patent number: 10712767
    Abstract: According to one embodiment, there is provided a clock generator including a frequency divider configured to generate a divided frequency clock of a frequency lower than that of a source clock by performing mask processing on part of a pulse train of the source clock.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: July 14, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Satoshi Kamiya
  • Patent number: 10715122
    Abstract: An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Guolei Yu, Ajay Kumar Kosaraju, Marko Koski
  • Patent number: 10690721
    Abstract: A glitch detector includes an input flip-flop clocked by a clock signal and having a non-inverting data output, an inverting data output, and a data input receiving input from the inverting data output, the input flip-flop generating a divided version of the clock signal at the non-inverting data output. A configurable delay chain receives the divided version of the clock signal and generates a delayed version of the divided version of the clock signal as a delay output. An intermediate flip-flop clocked by the clock signal has a data input receiving the delay output, the intermediate flip-flop generating an intermediate output as a function of the delay output. A logic circuit receives the divided version of the clock signal and the intermediate output, and generates a glitch detect signal by performing a logical operation on the divided version of the clock signal and the intermediate output.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 23, 2020
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventor: Beng-Heng Goh
  • Patent number: 10684671
    Abstract: Adaptively controlling drive strength of multiplexed power from supply power rails in a power multiplexing system to a powered circuit is disclosed. A power multiplexing circuit in the power multiplexing system includes a plurality of supply selection circuits (e.g., head switches) each coupled between a respective supply power rail and an output power rail coupled to the powered circuit. The power multiplexing circuit is configured to activate a selected supply selection circuit to switch coupling of an associated supply power rail to the output power rail to power the powered circuit. In one example, the supply selection circuits each include a plurality of power switch selection circuits coupled to an associated supply power rail. The power switch selection circuits are configured to be activated and deactivated by a control circuit to adjust drive strength of a multiplexed supply power rail based on operational conditions, which can account for performance variations.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: June 16, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Shraddha Sridhar, Yeshwant Nagaraj Kolla, Neel Shashank Natekar
  • Patent number: 10686457
    Abstract: A circuit device includes an oscillation signal generation circuit for generating an oscillation signal with an oscillation frequency set by frequency control data, and a processing circuit. The processing circuit includes a counter for performing a count process based on the oscillation signal, and a latch circuit for holding a count value of the counter based on a reference signal. The processing circuit performs a loop filter process on a phase comparison result based on output data of the latch circuit to output the frequency control data, holds information based on the phase comparison result when the holdover is detected, and outputs the frequency control data based on the information held, in a holdover period.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: June 16, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Kentaro Seo
  • Patent number: 10673478
    Abstract: According to one embodiment of an asynchronous communication device, the transmitter circuit includes a signal generation circuit to output a first pulse signal and a delay compensation circuit to receive the first pulse signal, perform delay compensation processing on the pulse width of the first pulse signal, and output a second pulse signal obtained by the delay compensation processing. The delay unit receives the second pulse signal, causes delay in the rising or falling edge of the second pulse signal, and outputs a third pulse signal in which the delay is caused. The receiver circuit receives the third pulse signal and performs signal processing based on the third pulse signal. The delay compensation circuit, while maintaining the pulse period of the first pulse signal, performs pre-compensation processing on the first pulse signal based on a delay value of the delay to be caused by the delay unit.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 2, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kyoji Harada, Ryouta Niwa, Katsumichi Katou
  • Patent number: 10644713
    Abstract: A method of enhancing SAR ADC performance includes employing PVT processor to correct process, voltage and temperature (PVT) variation. The PVT processor senses process, supply voltage and temperature information then maximize the time for SAR binary search process. The PVT processor first applies coarse optimization to correct process and voltage variation then applies fine optimization to correct the temperature variation. The SAR ADC is operated at its optimized PVT condition and its performance is enhanced after PVT optimization.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 5, 2020
    Assignee: IPGREAT INCORPORATED
    Inventor: Yuan-Ju Chao
  • Patent number: 10622041
    Abstract: A semiconductor device includes: a clock generation circuit suitable for generating first and second write clocks that correspond respectively to a rising clock and a falling clock of an external clock during a write leveling operation, and for generating an input clock based on a delay of a write command by a delay time based on the rising clock during a write operation; a first transmission line suitable for transmitting the first write clock or the input clock as a first transmission clock; and a second transmission line suitable for transmitting the second write clock as a second transmission clock.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: April 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Young-Hoon Kim
  • Patent number: 10606306
    Abstract: A method and circuit are provided to reduce power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes series and shunt reactive circuit elements, such as series inductive reactance and a shunt inductive susceptance, configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: March 31, 2020
    Assignee: INPHI CORPORATION
    Inventor: Tomas Alexander Dusatko
  • Patent number: 10594521
    Abstract: Apparatuses and methods for performing asynchronous multicarrier communications are provided. One such method involves generating, at a first wireless device, a waveform including one or more carriers, shaping the waveform to reduce interference between the waveform and adjacent waveforms, and transmitting, on a spectrum, the shaped waveform asynchronously.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 17, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Joseph Binamira Soriaga, Tingfang Ji, John Edward Smee, Naga Bhushan, Peter Gaal, Krishna Kiran Mukkavilli, Alexei Yurievitch Gorokhov
  • Patent number: 10548665
    Abstract: A sub-microsecond pulsed electric field generator is disclosed. The field generator includes a controller, which generates a power supply control signal and generates a pulse generator control signal, and a power supply, which receives the power supply control signal and generates one or more power voltages based on the received power supply control signal. The field generator also includes a pulse generator which receives the power voltages and the pulse generator control signal, and generates one or more pulses based on the power voltages and based on the pulse generator control signal. The controller receives feedback signals representing a value of a characteristic of or a result of the pulses and generates at least one of the power supply control signal and the pulse generator control signal based on the received feedback signals.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: February 4, 2020
    Assignee: PULSE BIOSCIENCES, INC.
    Inventors: Shu Xiao, Brian G. Athos, Mark P. Kreis, David J. Danitz, Darrin R. Uecker
  • Patent number: 10547414
    Abstract: A transmitter broadcasts a signal having a different code characteristic for each of several directions. A receiver receives the broadcast signal from one of the directions and generates an expected signal for that direction based on the code characteristic for that direction. The receiver detects the broadcast signal from the direction based on the expected signal for that direction.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: January 28, 2020
    Assignee: Greenwich Technologies Associates
    Inventor: Carl M. Elam
  • Patent number: 10517469
    Abstract: An endoscopic system for use a controlled light environment is disclosed. In an implementation, the system may include an endoscope having an image sensor, an emitter, and a control circuit. The control circuit controls a frequency of the emitter in response to signals that correspond to the frequency of the emitter. The image sensor has input and output pads, where a pad count is reduced by not having a dedicated input synchronization clock pad. A frame period is divided into three defined states: a rolling-readout state during which image data is output through the pads, a service-line state during which non-image data is output through the pads, and a configuration state during which instruction data is received by the image sensor through the pads. Signal transitions are encoded within output data from the image sensor and correspond with defined states.
    Type: Grant
    Filed: March 15, 2014
    Date of Patent: December 31, 2019
    Assignee: DePuy Synthes Products, Inc.
    Inventors: Laurent Blanquart, Donald M. Wichern
  • Patent number: 10505559
    Abstract: A method of enhancing SAR ADC performance includes employing PVT processor to correct process, voltage and temperature (PVT) variation. The PVT processor senses process, supply voltage and temperature information then maximize the time for SAR binary search process. The PVT processor first applies coarse optimization to correct process and voltage variation then applies fine optimization to correct the temperature variation. The SAR ADC is operated at its optimized PVT condition and its performance is enhanced after PVT optimization.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: December 10, 2019
    Assignee: IPGreat Incorporated
    Inventor: Yuan-Ju Chao
  • Patent number: 10396812
    Abstract: A register and an analog-digital converter capable of detecting signal distortion in high-radiation environments are provided. The register includes: a signal input terminal receiving a digital signal; and a digital single event transient (DSET) detection unit detecting whether information of the digital signal input through the signal input terminal is distorted, wherein the DSET detection unit includes a first output terminal through which a first detection signal is output, the first detection signal being used to determine whether at least one of rising edge timing information and falling edge timing information of the digital signal is distorted.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 27, 2019
    Assignees: KOREA ATOMIC ENERGY RESEARCH INSTITUTE, KOREA UNIVERSITY RESEARCH & BUSINESS FOUNDATION
    Inventors: In Yong Kwon, Yong Seok Lee, Jung Yeol Yeom, Chang Hwoi Kim
  • Patent number: 10340021
    Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: July 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Amano, Kouhei Toyotaka, Hiroyuki Miyake, Aya Miyazaki, Hideaki Shishido, Koji Kusunoki
  • Patent number: 10320509
    Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 11, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Yunteng Huang, Adam B. Eldredge, Gregory J. Richmond
  • Patent number: 10319422
    Abstract: A decoder according to one embodiment of the invention includes a set of lines, a resonator circuit, a set of input leads for receiving input signals, and a set of switches for coupling some of the lines within the set of lines to the resonator circuit in response to the input signals while the other lines within the set of lines are at a first binary voltage. The lines are coupled to a set of pointer circuits. The pointer circuits perform logic functions on the signals on the lines when the resonating signal is at a second binary voltage opposite the first binary voltage to thereby decode the input signals. Because the lines are driven high and low by a resonator circuit, the decoder circuit power consumption is less than it would be if the lines were pulled up and down by a set of pullup and pulldown transistors.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 11, 2019
    Inventor: David A. Huffman
  • Patent number: 10320286
    Abstract: The absorption circuit of the present invention is applied in a feed circuit, wherein the absorption circuit comprises a comparison unit and a regulation unit, and the comparison unit is employed to receive a voltage of a transformer primary dotted terminal of the feed circuit, and to compare the voltage with a first preset voltage and a second preset voltage and to output a comparison result, and the regulation unit is employed to regulate a resistor and a capacitor coupled to the transformer according to the comparison result, wherein the first preset voltage is larger than the second preset voltage. Therefore, the present invention can control the resistor and the capacitor coupled to the transformer according to the leakage inductance (i.e. the voltage) of the transformer, and then to adaptively restrain the corresponding voltage peak and EMI.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 11, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Dan Cao
  • Patent number: 10303200
    Abstract: A method for implementing clock dividers includes providing, in response to detecting a voltage drop at a processor core, an input clock signal to a transmission gate multiplexer for selecting between one of two stretch-enable signals. In some embodiments, selecting between the one of two stretch-enable signals includes inputting a set of core clock enable signals into a clock divider circuit, and modifying the set of core clock enable signals to generate the stretch-enable signals. An output clock signal is generated based on the selected stretch-enable signal.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: May 28, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Deepesh John, Steven Kommrusch, Vibhor Mittal
  • Patent number: 10283176
    Abstract: Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: May 7, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hun-dae Choi, Young-kwon Jo
  • Patent number: 10234892
    Abstract: A method and circuit are provided to reduce power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes series and shunt reactive circuit elements, such as series inductive reactance and a shunt inductive susceptance, configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: March 19, 2019
    Assignee: INPHI CORPORATION
    Inventor: Tomas Alexander Dusatko
  • Patent number: 10224721
    Abstract: A switch control circuit to switch off communication channels between a baseboard management controller (BMC) and a backplane chip when not needed includes a logic component and a switch circuit. The switch circuit is configured for coupling between the BMC and the backplane chip in a device. The logic component obtains a logic control signal from the BMC, and outputs a switch signal to the switch circuit to turn on or turn off the switch circuit according to the logic control signal. An electronic device including the switch control circuit is also provided.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 5, 2019
    Assignee: HONGFUJIN PRECISION ELECTRONICS (TIANJIN) C
    Inventor: Fei Luo
  • Patent number: 10200192
    Abstract: Apparatus and method for enacting data security in a data storage device, such as by protecting against a differential power analysis (DPA) attack. In some embodiments, a dithered clock signal is generated having a succession of clock pulse segments. Each of the clock pulse segments has a different respective frequency selected in response to a first random number and a different overall duration selected in response to a second random number. The different segment frequencies are selected by supplying the first random number to a lookup table, and the different segment durations are obtained by initializing a timer circuit using the second random number. The dithered clock signal is used to clock a programmable processor during execution of a cryptographic function.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: February 5, 2019
    Assignee: Seagate Technology LLC
    Inventor: Bruce D. Buch
  • Patent number: 10162379
    Abstract: A system clock signal distributed to electronic configurable and reconfigurable computing devices within a distributed computing system. The distributed computing devices, which may be dual-die chip carriers (DDCC), include input addressable data/clock ports on which system clock signals are accepted and may be propagated on one or more data/clock output ports. The input and/or output ports of various distributed computing devices may be configured and reconfigured according to system preferences or requirements.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: December 25, 2018
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edumund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 10127875
    Abstract: The present disclosure provides a shift register unit. The shift register unit includes a pre-charge reset module; a pull-up module; a pull-down module; a first pull-down control module; and a second pull-down control module. The pre-charge reset module is connected to a forward scanning control signal input terminal, a reverse scanning control signal input terminal, a first signal input terminal, a second signal input terminal, and a pull-up control node. The pull-up module is connected to the pull-up control node, an input terminal of a first clock signal, and a signal output terminal. The first pull-down control module is connected to a pull-down control node, the forward scanning control signal input terminal, the reverse scanning control signal input terminal, the first signal input terminal, and the second signal input terminal.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: November 13, 2018
    Assignees: BOE TECHNOLOGY CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Bo Wu, Xiaojing Qi, Wen Tan
  • Patent number: 10042383
    Abstract: A clock calibration method of a navigation system is provided. The clock calibration method includes: entering a calibration mode; sequentially issuing, by a host, a count start signal and a count end signal separated by a time interval; counting a local oscillation frequency of a local oscillator when a navigation device receives the count start signal from the host; disabling the counting when the navigation device receives the count end signal from the host and generating a current count; generating a calibration signal according to the current count and a predetermined count corresponding to the time interval; and calibrating the local oscillation frequency of the local oscillator according to the calibration signal.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: August 7, 2018
    Assignee: PIXART IMAGING INC.
    Inventors: Kevin Len-Li Lim, Zi-Hao Tan
  • Patent number: 10027382
    Abstract: Circuit connectors for establishing EHF communication include a receiver configured to receive a transmitted EHF electromagnetic signal, and an output circuit coupled to the receiver. The output circuit has two states of operation that correspond to enabling a signal output and disabling the signal output. The output circuit is also configured to change its state of operation responsive to a state of a control signal, and a controller is coupled to the receiver and configured to produce the control signal. The control signal has two states that correspond to a first condition when the received signal exceeds a first threshold and a second condition when the received signal is less than a second threshold.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: July 17, 2018
    Assignee: Keyssa, Inc.
    Inventors: Ian A. Kyles, Gary D. McCormack, Norbert Seitz
  • Patent number: 9998102
    Abstract: A phase and frequency control circuit may be provided. The phase and frequency control circuit may include a division circuit configured to generate a plurality of divided signals by dividing an input signal. The phase and frequency control circuit may include a timing control circuit configured to generate a plurality of timing control signals by sampling the plurality of divided signals according to a phase control code and a sampling reference signal.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: June 12, 2018
    Assignee: SK hynix Inc.
    Inventor: In Hwa Jung
  • Patent number: 9960620
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: May 1, 2018
    Assignee: Navitas Semiconductor, Inc.
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
  • Patent number: 9959185
    Abstract: A memory system includes a memory device, a switch device, and a built-in self-test circuit. The memory device is for storing data and toggling a notification signal whenever a read operation or a write operation is completed. The switch device has a first input terminal for receiving an external clock signal, a second input terminal coupled to the memory device for receiving the notification signal, a select terminal for receiving a selection signal, and an output terminal for outputting a memory clock signal to the memory device. The memory clock signal is one of the external clock signal and the notification signal. The built-in self-test circuit is for outputting a control signal required by the memory device to perform the read operation or the write operation and check whether the memory device functions normally.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 1, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Hsin-Wen Chen
  • Patent number: 9939841
    Abstract: A method and circuit are provided to reduce the power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes a series inductive reactance and a shunt inductive susceptance configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: April 10, 2018
    Assignee: INPHI CORPORATION
    Inventor: Tomas Alexander Dusatko
  • Patent number: 9887696
    Abstract: A semiconductor device includes a boot-up start signal generation unit configured to generate a boot-up start signal which is enabled in synchronization with a time at which a preset delay period has passed from a time point at which an initialization signal is enabled after a power-up period is ended, and a boot-up period signal generation unit configured to generate a boot-up period signal which is enabled according to a set pulse generated in synchronization with a time point at which the boot-up start signal is enabled.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: February 6, 2018
    Assignee: SK hynix Inc.
    Inventor: Tae Kyun Shin
  • Patent number: 9887691
    Abstract: A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 6, 2018
    Assignee: SK hynix Inc.
    Inventors: Myeong Jae Park, Kyung Hoon Kim, Woo Yeol Shin, Han Kyu Chi
  • Patent number: 9881576
    Abstract: The present disclosure provides a shift register, a gate driving circuit and a display panel and a display device. The shift register comprises an input module, a reset module, a pull-up module, a first pull-down module, a second pull-down module, an output control module, and an output denoising module. The output denoising module feeds the scanning signal back to the first control terminal of the output control module when the scanning signal output terminal outputs the scanning signal, thereby reducing noise of the signal of the first control terminal of the output control module and further reducing noise of the scanning signal outputted by the scanning signal output terminal.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: January 30, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventor: Fei Huang
  • Patent number: 9847113
    Abstract: Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: December 19, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hun-dae Choi, Young-kwon Jo
  • Patent number: 9825755
    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A configurable clock tree includes a delay matrix that may be configured such that each the timing of clocks for each of a plurality of data lanes can be optimized for minimum skew. Selections between different versions of a base clock signal and different paths available to the selected version may provide a root clock used for transmitting data on a communications link. The versions of the one or more clock signals may include three versions of a first clock signal. Each version of the first clock signal may be subject to a different delay with respect to the clock signal.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventor: Yaxin Shui
  • Patent number: 9817071
    Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: November 14, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9820256
    Abstract: Systems and methods are directed to use of a neighbor list for wireless indoor navigation. The neighbor list may include related information regarding all neighboring access points (APs). The neighbor list can be transmitted, at least partially, to include the related information of a desired number of or all APs in the neighbor list from one AP to a wireless device. The neighbor list can be transmitted in a Neighbor Report Response (NRR) or a time-of-flight (ToF) Response and allow the wireless device to scan for minimal number of APs for ToF measurements. By using the neighbor list, power consumption and time can be significantly reduced during wireless indoor navigation.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: November 14, 2017
    Assignee: INTEL CORPORATION
    Inventors: Uri Schatzberg, Yuval Amizur, Leor Banin, Alexander Sirotkin
  • Patent number: 9800243
    Abstract: A clock circuit includes a buffer module, N multiplexers, and N clock gating cells. The buffer module includes an input end and N output ends, and is configured to enhance a driving capability of a clock signal received by the input end, and output the clock signal from the N output ends, and the N output ends are connected to data ends of the N clock gating cells one to one. Output ends of the N first multiplexers are connected to enabling ends of the N clock gating cells one to one. Each clock gating cell outputs a clock signal from an output end according to a frequency division logic signal or a gating logic signal received by an enabling end from an output end of a corresponding multiplexer and the clock signal received by a data end from an output end of the buffer module.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: October 24, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Shengli Yang, Xing Huang
  • Patent number: 9735759
    Abstract: A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: August 15, 2017
    Assignee: MOTOROLA SOLUTIONS, INC.
    Inventors: Edward A. Diaz, Johnny R. Ferreira, Ricardo Franco, Charles R. Ruelke, Richard S. Young
  • Patent number: 9690319
    Abstract: According to one embodiment, a semiconductor device includes: a clock generation circuit configured to receive a first clock signal and to generate a second clock signal from the first clock signal; a first phase adjustment circuit configured to generate a first control signal using the first clock signal and the second clock signal; and a second phase adjustment circuit configured to receive data and to add a first delay value based on the first control signal to the data.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: June 27, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobutaka Kitagawa
  • Patent number: 9660627
    Abstract: Techniques and devices for differential signal repeating are described. A differential signal repeating method may include receiving an input differential signal pair including first and second input signals received at first and second input terminals, respectively, and generating an output signal at an output terminal. Generating the output signal may include: based on a determination, at a first time, that the first and second input signals represent complementary values, setting a level of the output signal to represent an inverse of the value represented by the first input signal, and based on a determination, at a second time, that the first and second input signals do not represent complementary values, placing the output terminal in a high-impedance state.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: May 23, 2017
    Assignees: Bitfury Group Limited
    Inventor: Valerii Nebesnyi
  • Patent number: 9638754
    Abstract: A semiconductor apparatus includes a test entry control block configured to generate a plurality of trigger signals and a reset signal according to a test setting command and addresses; and a test entry signal generation block configured to enable a test entry signal when the plurality of trigger signals are sequentially enabled.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: May 2, 2017
    Assignee: SK hynix Inc.
    Inventor: Soo Young Jang
  • Patent number: 9609712
    Abstract: The present disclosure provides a signal generating method and a circuit for controlling dimming of an LED. The method comprises generating a first pulse signal, the first pulse signal comprising information of P bits gray levels, P being an integer, wherein the minimum pulse-width of the first pulse is N, N is an integer; generating a second pulse signal after the first pulse signal, the second pulse signal comprising information of Q bits gray levels, Q being an integer, wherein the amplitude of the second pulse signal is different from the amplitude of the first pulse signal, the minimum pulse-width of the second pulse is the same as the minimum pulse-width of the first pulse; and utilizing the first pulse signal and the second pulse signal to represent gray levels information of the LED.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: March 28, 2017
    Assignee: SILICON TOUCH TECHNOLOGY INC.
    Inventors: Chi-Yuan Chin, Kuei-Jyun Chen
  • Patent number: 9595943
    Abstract: A method and circuit for implementing a broadband resonator for resonant clock distribution, and a design structure on which the subject circuit resides are provided. The circuit includes a pair of first inductors, and a second inductor and a capacitor coupled between a respective first end of the respective first inductors. An opposite free end of the respective first inductors is connected to a respective clock transmission line and connected in parallel to a load capacitance. A frequency response of the circuit includes two poles and a zero in a frequency band of the resonant clock distribution system.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: March 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Santhosh Madhavan, Giri N. K. Rangan, Patrick I. Rosno, Timothy J. Schmerbeck
  • Patent number: 9543934
    Abstract: In an approach for determining multiplier values and divisor values for programming frequency multiplier and divider circuits in a clock network, respective requested frequency values and respective tolerance levels relative to the requested frequency values for a plurality of clocked circuit blocks are used. Multiple solution sets are generated, with each solution set including a multiplier value and an associated set of values of divisors, such that resulting actual frequencies satisfy the respective tolerance levels. Respective sets of clocked error values are determined for the plurality of solution sets, with each clocked error value corresponding to a clocked circuit block. Solution-set-error values are determined as a function of the respective sets of clocked error values, and the solution set having the least solution-set-error value is selected and stored.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: January 10, 2017
    Assignee: XILINX, INC.
    Inventors: Somdutt Javre, Pradeep Kumar Mishra, Gangadhar Budde, Siddharth Rele