Clock Or Pulse Waveform Generating Patents (Class 327/291)
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Patent number: 12348232Abstract: A delay control circuit provided herein includes a DLL control circuit, a delay line circuit, and an N-value detection circuit. The DLL control circuit determines the delay amount based on the phase difference between the input and output clock signals. The delay line circuit delays the input clock signal based on the delay amount to generate an output clock signal. The N-value detection circuit performs an N-value detection operation for detecting the number of delayed clock cycles from the input clock signal to the output clock signal. When it is determined to be in an overflow state, the DLL control circuit outputs a signal indicating an overflow state to the N-value detection circuit. When the signal indicating the overflow state is received, the N-value detection circuit does not perform the N-value detection operation, but instead sets the number of delayed clock cycles to a predetermined value.Type: GrantFiled: July 6, 2023Date of Patent: July 1, 2025Assignee: WINDBOND ELECTRONICS CORP.Inventor: Shinya Okuno
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Patent number: 12341515Abstract: Provided are a delay-locked loop (DLL), a delay locking method, a clock synchronization circuit, and a memory. The DLL includes: a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal; a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal; a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals.Type: GrantFiled: August 16, 2023Date of Patent: June 24, 2025Assignee: Changxin Memory Technologies, Inc.Inventors: Siman Li, Yoonjoo Eom
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Patent number: 12316336Abstract: A system includes a first phase interpolator, a second phase interpolator, and a circuit. The circuit is configured to receive a first signal and a second signal provided by the first phase interpolator and a third signal and a fourth signal provided by the second phase interpolator. The first circuit is configured to provide at least eight phase signals, each of the eight phase signals being at a respective phase angle in response to the first signal, the second signal, the third signal and the fourth signal.Type: GrantFiled: June 7, 2023Date of Patent: May 27, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Yonghyun Shim, Yu-Ming Ying, Guansheng Li, Delong Cui, Jun Cao
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Patent number: 12268508Abstract: A method for assessing peripheral nerve stimulation (PNS) for a coil geometry includes retrieving a PNS Huygens' P-matrix for a body model. The PNS Huygens' P-matrix is defined on a Huygens' surface enclosing the body model. The method further includes generating a coil specific PNS P-matrix for the coil geometry based on at least the PNS Huygens' P-matrix for the body model, determining at least one PNS threshold for the coil geometry based on the coil specific PNS P-matrix, and storing the at least one PNS threshold in a storage device.Type: GrantFiled: December 10, 2020Date of Patent: April 8, 2025Assignee: The General Hospital CorporationInventors: Mathias Davids, Lawrence L. Wald, Bastien Guerin
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Patent number: 12272981Abstract: A method to enhance the functionality of a battery through the use of a pulsing apparatus. The pulsing apparatus configured to improve cell conditioning, maintain battery cells, and overall cell function through pulsing a selected current into and out of a battery. The pulsing selected to deliver a predetermined number of pulses to the battery. The pulses having a slew rate of at least 0.1 A/?s, a pulse width between 1 ?s and 10 ms with a pulse rise time of at least 1 ?s to alter a current of the battery. Preferably the predetermined number of pulses is between 100 pulses per second and 1 pulse per minute.Type: GrantFiled: June 30, 2020Date of Patent: April 8, 2025Inventors: Bill Burger, Michael Schlicht
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Patent number: 12265885Abstract: Apparatus and method for scalable representations of arbitrary quantum computing rotations. For example, one embodiment of an apparatus comprises: a memory to store a first waveform; and a base envelope generator to implement a base envelope, the base envelope applied to the first waveform to generate a second waveform usable to cause quantum rotation of a specified angle on a target quantum bit (qubit) of a quantum processor, and wherein the base envelope is selected out of a first plurality of envelopes based one or more characteristics specific to the target qubit on which the quantum rotation is performed.Type: GrantFiled: December 29, 2022Date of Patent: April 1, 2025Assignee: Intel CorporationInventors: Xiang Zou, Shavindra Premaratne
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Patent number: 12254917Abstract: The disclosure provides a power supply circuit, a memory, a testing device, a memory system and an electronic device, relates to the memory technologies, and may reduce the testing time of the memory and the footprint occupation of the memory. The power supply circuit can include a voltage adjusting circuit and an oscillation circuit. A first voltage output terminal of the voltage adjusting circuit is coupled with a power supply input terminal of a delay chain circuit in the memory and coupled with a power supply input terminal of the oscillation circuit. The voltage adjusting circuit is configured to output a first voltage to the delay chain circuit and the oscillation circuit via the first voltage output terminal. The oscillation circuit is configured to generate a clock signal corresponding to the first voltage. The voltage adjusting circuit is also configured to receive an adjusting signal for adjust the first voltage.Type: GrantFiled: December 28, 2022Date of Patent: March 18, 2025Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yu Wang, BiRuo Song
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Patent number: 12181910Abstract: A timing margin sensor circuit includes one or more time-to-digital converters (TDCs), a predictor, and a translation circuit. The TDC(s) measure(s) progress of a clock signal through one or more chains of delay stages. The progress depends on sense conditions acting upon the delay chain, such as the supply voltage and the temperature. The predictor receives the measured progress. If the delay chain becomes slower, the predictor extrapolates a predicted progress value. If the delay chain becomes faster, the predictor outputs the actual progress value. The translator translates the predictor output value to sense information that can be used in a clock stretcher circuit. The timing margin sensor may further have an averager/selector to average or select from the results of multiple TDCs. The timing margin sensor may further have a calibrator to compensate for nominal sense conditions, and one or more tunable delays circuits.Type: GrantFiled: January 31, 2023Date of Patent: December 31, 2024Assignee: SambaNova Systems, Inc.Inventors: Mahmood Khayatzadeh, Satyajit Sarkar, Jinuk Shin
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Patent number: 12181914Abstract: A real-time clock module includes: a timing circuit configured to measure a time to generate time data; a selection circuit configured to select at least one of a plurality of types of event data as target event data to be stored and select, as target time data to be stored, data corresponding to at least a part of time digits of the time data in response to generation of an event; and a memory circuit configured to store the target time data and the target event data.Type: GrantFiled: April 25, 2023Date of Patent: December 31, 2024Assignee: SEIKO EPSON CORPORATIONInventor: Yasuhiro Sudo
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Patent number: 12147264Abstract: A clock distribution circuit includes a global distribution circuit, a first local distribution circuit and a second local distribution circuit. The global distribution circuit receives external clock signals and generates internal clock signals and primary reference clock signal set according to the external clock signals. The first local distribution circuit receives the internal clock signals and the primary reference clock signal set and generates a secondary reference clock signal set according to the internal clock signals and the primary reference clock signal set. The second local distribution circuit receives the internal clock signals and the secondary reference clock signal set and generates a thirdly reference clock signal set according to the internal clock signals and the secondary reference clock signal set.Type: GrantFiled: March 14, 2023Date of Patent: November 19, 2024Assignee: SK hynix Inc.Inventors: Ji Hyo Kang, Kyung Hoon Kim, Jae Hyeok Yang, Sang Yeon Byeon, Gang Sik Lee, Joo Hyung Chae
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Patent number: 12131226Abstract: Methods, systems, and apparatus for implementing a unitary quantum gate on one or more qubits. In one aspect, a method includes the actions designing a control pulse for the unitary quantum gate, comprising: defining a universal quantum control cost function, wherein the control cost function comprises a qubit leakage penalty term representing i) coherent qubit leakage, and ii) incoherent qubit leakage across all frequency components during a time dependent Hamiltonian evolution that realizes the unitary quantum gate; adjusting parameters of the time dependent Hamiltonian evolution to vary a control cost according to the control cost function such that leakage errors are reduced; generating the control pulse using the adjusted parameters; and applying the control pulse to the one or more qubits to implement the unitary quantum gate.Type: GrantFiled: May 3, 2023Date of Patent: October 29, 2024Assignee: Google LLCInventors: Yuezhen Niu, Hartmut Neven, Vadim Smelyanskiy, Sergio Boixo Castrillo
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Patent number: 12056596Abstract: Disclosed herein are staged oscillators for neural computing, as well as related methods and assemblies. In some embodiments, neural computing circuitry may include a first oscillator set, a second oscillator set, and an averaging structure coupled between the first oscillator set and the second oscillator set.Type: GrantFiled: August 10, 2020Date of Patent: August 6, 2024Assignee: Intel CorporationInventors: Dmitri E. Nikonov, Hai Li, Ian A. Young
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Patent number: 12015403Abstract: A semiconductor apparatus includes a clock distribution network, a data output circuit, and a data input circuit. The clock distribution network receives a system clock signal and drives the system clock signal to a CMOS level and a CML level to signal in different manners. The data output circuit outputs data based on the clock signal driven to the CMOS level. The data input circuit receives data based on the clock signal driven to the CML level.Type: GrantFiled: December 19, 2022Date of Patent: June 18, 2024Assignee: SK hynix Inc.Inventors: Ji Hyo Kang, Kyung Hoon Kim
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Patent number: 11985295Abstract: The present invention relates to a method for generating control signals for an image capture device, the method being performed in a communication device comprising a first slave time generator and a second slave time generator, the communication device being connected to a first remote time server and a second remote time server, the method comprising: synchronizing the first slave time generator with the first remote time server; synchronizing the second slave time generator with the second remote time server; generating a first control signal based on the first clock, and sending the first control signal to the image capture device; and upon detecting a loss of synchronization between the first slave time generator and the first remote time server, generating a second control signal based on the second clock, and sending the second control signal to the image capture device.Type: GrantFiled: January 20, 2022Date of Patent: May 14, 2024Assignee: Canon Kabushiki KaishaInventors: Yacine El Kolli, Romain Guignard, Tristan Halna Du Fretay, Lionel Tocze
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Patent number: 11942947Abstract: A system comprises pulse generation and measurement circuitry comprising a plurality of pulse generator circuits and a plurality of ports, and management circuitry. The management circuitry is operable to analyze a specification of a controlled system and controlled elements that comprises a definition of a controlled element of the control system, and a definition of one or more pulses available for transmission by the control system. The management circuitry is operable to configure, based on the specification, the pulse generation and measurement circuitry to: generate the one or more pulses via one or more of the plurality of pulse generator circuits; and output the one or more pulses to the controlled element via one or more of the plurality of ports.Type: GrantFiled: April 26, 2023Date of Patent: March 26, 2024Assignee: Quantum MachinesInventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan, Tal Shani
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Patent number: 11936386Abstract: A clock transfer circuit includes a first stage circuit configured to produce an output signal that uses a second signaling technology from an input signal that uses a first signaling technology; and a second stage circuit configured to produce a clock signal by delaying the output signal; wherein the first stage circuit includes a semiconductor device configured to compensate for delay fluctuation caused by fluctuation of power supply voltage between a first power source and a second power source.Type: GrantFiled: April 10, 2023Date of Patent: March 19, 2024Assignees: SK hynix Inc., Seoul National University R&DB FoundationInventors: Soyeong Shin, Yongjae Lee, Jiheon Park, Deog-Kyoon Jeong
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Patent number: 11903564Abstract: The disclosure extends to systems and methods for reducing the area of an image sensor by reducing the imaging sensor pad count used for data transmission and clock generation.Type: GrantFiled: May 31, 2022Date of Patent: February 20, 2024Assignee: DePuy Synthes Products, Inc.Inventors: Laurent Blanquart, Donald M. Wichern
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Patent number: 11868193Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.Type: GrantFiled: April 6, 2021Date of Patent: January 9, 2024Assignee: Marvell Asia Pte LtdInventors: Rabin Sugumar, Bharath Upputuri, Bruce Kauffmann, Novinder Waraich, Bivraj Koradia, Paul Sebata
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Patent number: 11848644Abstract: A resistor-capacitor oscillation circuit includes a first group of inverters, a second group of inverters, a latch, a delay circuit, and a third group of inverters. The first group of the inverters is connected to the delay circuit and is configured to generate a first signal A and a second signal B. An input end of the second group of the inverters is connected to an enable signal EN. An output end of the second group of the inverters is connected to the latch. An output end of the delay circuit is connected to the latch. The latch is connected to the third group of the inverters and includes a first output end and a second output end. After a first clock signal FB is driven by the third group of the inverters, an output signal CLK is output by an output end of the third group.Type: GrantFiled: April 7, 2023Date of Patent: December 19, 2023Assignee: LANSUS TECHNOLOGIES INC.Inventors: Xiaojiao Ren, Jiashuai Guo
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Patent number: 11848679Abstract: The present application discloses a circuit for generating spread-spectrum synchronous clock signal. The circuit includes a frequency detector comprising a fraction controller configured to compare an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback to generate a first control signal and a second control signal alternately for determining a control word to track the first frequency and a phase-shift controller configured to register n levels for the first control signal and the second control signal to introduce n phase delays for changing a fraction part of the control word randomly to provide a broadened boundary. The circuit also includes a digitally controlled oscillator configured to generate a synthesized periodic signal based on a base time unit, the first frequency, and the control word, with the second frequency being locked within the broadened boundary of the first frequency.Type: GrantFiled: October 9, 2019Date of Patent: December 19, 2023Assignees: Beijing BOE Technology Development Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Xiangye Wei, Liming Xiu
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Patent number: 11838026Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.Type: GrantFiled: June 29, 2021Date of Patent: December 5, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITEDInventors: Huaixin Xian, Liu Han, Jing Ding, Qingchao Meng
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Patent number: 11677389Abstract: A system comprises pulse generation and measurement circuitry comprising a plurality of pulse generator circuits and a plurality of ports, and management circuitry. The management circuitry is operable to analyze a specification of a controlled system and controlled elements that comprises a definition of a controlled element of the control system, and a definition of one or more pulses available for transmission by the control system. The management circuitry is operable to configure, based on the specification, the pulse generation and measurement circuitry to: generate the one or more pulses via one or more of the plurality of pulse generator circuits; and output the one or more pulses to the controlled element via one or more of the plurality of ports.Type: GrantFiled: August 24, 2022Date of Patent: June 13, 2023Inventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan, Tal Shani
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Patent number: 11625062Abstract: Devices for reducing power consumption and skew for transmission of signals in a clock distribution circuit are described. A global distribution circuit is configured to divide external clock signals to generate first divided multiphase clock signals and divide one of the first divided multiphase clock signals to generate a reference clock signal. A local distribution circuit is configured to generate second divided multiphase clock signals according to a portion of the first divided multiphase clock signals and the reference clock signal.Type: GrantFiled: April 9, 2021Date of Patent: April 11, 2023Assignee: SK hynix Inc.Inventors: Ji Hyo Kang, Kyung Hoon Kim, Jae Hyeok Yang, Sang Yeon Byeon, Gang Sik Lee, Joo Hyung Chae
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Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions
Patent number: 11614770Abstract: A configurable semiconductor device (“CSD”) is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.Type: GrantFiled: September 16, 2020Date of Patent: March 28, 2023Assignee: GOWIN SEMICONDUCTOR CORPORATIONInventors: Jianhua Liu, Jinghui Zhu, Ning Song, Tianping Wang, Chienkuang Chen, Diwakar Chopperla, Tianxin Wang, Zhenyu Gu, Xiaozhi Lin -
Patent number: 11573593Abstract: A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.Type: GrantFiled: April 16, 2018Date of Patent: February 7, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Richard Martin Born, Stephen Victor Kosonocky, Miguel Rodriguez
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Patent number: 11569821Abstract: One example describes a superconducting XOR-gate system. The system includes a pulse generator configured to generate a decision pulse. The system also includes an input superconducting XOR-2 gate that receives a first superconducting logic input signal and a second superconducting logic input signal and is configured to perform a logic XOR function based on the decision pulse on a given phase of a clock signal to provide an intermediate superconducting logic output signal. The system also includes an output superconducting XOR-2 gate that receives the intermediate superconducting logic output signal and a third superconducting logic input signal and is configured to perform a logic XOR function based on the decision pulse on the given phase of the clock signal to provide a superconducting logic output signal.Type: GrantFiled: June 22, 2021Date of Patent: January 31, 2023Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATIONInventors: Alexander Louis Braun, Josh Lance Puckett
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Patent number: 11557963Abstract: A charge-pump control circuit includes an oscillator which supplies a clock for driving a charge pump driver to supply a first gate voltage to a discharging transistor in order to control discharge from a battery, and driving a charge pump driver to supply a second gate voltage to a charging transistor in order to control charge to the battery, respectively; and a drive control circuit which sets a control target voltage as one of the first gate voltage and the second gate voltage having a lower voltage in order to control generation of the clock by the oscillator according to the control target voltage.Type: GrantFiled: June 10, 2020Date of Patent: January 17, 2023Assignee: ABLIC INC.Inventor: Ryoichi Anzai
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Patent number: 11463075Abstract: A system comprises pulse generation and measurement circuitry comprising a plurality of pulse generator circuits and a plurality of ports, and management circuitry. The management circuitry is operable to analyze a specification of a controlled system and controlled elements that comprises a definition of a controlled element of the control system, and a definition of one or more pulses available for transmission by the control system. The management circuitry is operable to configure, based on the specification, the pulse generation and measurement circuitry to: generate the one or more pulses via one or more of the plurality of pulse generator circuits; and output the one or more pulses to the controlled element via one or more of the plurality of ports.Type: GrantFiled: August 27, 2021Date of Patent: October 4, 2022Inventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan, Tal Shani
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Patent number: 11387404Abstract: An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.Type: GrantFiled: September 13, 2018Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Huichu Liu, Tanay Karnik, Sasikanth Manipatruni, Daniel Morris, Kaushik Vaidyanathan, Ian Young
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Patent number: 11295790Abstract: A memory interface circuit includes a first output buffer circuit, a second output buffer circuit, a switching element, and a control circuit. The first output buffer circuit includes a first output node. The second output buffer circuit includes a second output node. The switching element is electrically connected to the first output node and the second output node, and is controlled to switch electrical connection states between the first output node and the second output node. The control circuit controls the switching element.Type: GrantFiled: September 3, 2020Date of Patent: April 5, 2022Assignee: KIOXIA CORPORATIONInventor: Shuuji Matsumoto
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Patent number: 11296120Abstract: The power consumption of a shift register or a display device including the shift register is reduced. A clock signal is supplied to a shift register by a plurality of wirings, not by one wiring. Any one of the plurality of wirings supplies a clock signal in only part of the operation period of the shift register, not during the whole operation period of the shift register. Therefore, the capacity load caused with the supply of clock signals can be reduced, leading to reduction in power consumption of the shift register.Type: GrantFiled: November 8, 2017Date of Patent: April 5, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Jun Koyama
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Patent number: 11290113Abstract: A clock stretcher includes a digital DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. The digital DLL corrects its delay speed at discrete times, during which it may be active. If the DLL delay line becomes slower while it is active, the modified clock signal would incur a glitch. The clock stretcher corrects for this glitch by using an increased hop code when a speed change occurs. The clock stretcher may operate from a sensed power supply without intervening voltage regulation.Type: GrantFiled: June 3, 2021Date of Patent: March 29, 2022Assignee: SAMBANOVA SYSTEMS, INC.Inventors: Fahim ur Rahman, Sang-Min Lee, Jin-Uk Shin
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Patent number: 11290114Abstract: A clock stretcher includes a DLL that derives delayed versions of an input clock signal. The clock stretcher has passive and stretching modes. It operates from a sensed power supply without intervening voltage regulation. In passive mode, it forwards input clock pulses to the clock stretcher output. The input clock pulses are delayed by fewer than 10 DLL delay line delay stages. In stretching mode, a combiner cyclically selects the delayed versions of the input clock signal to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. To enter passive mode, the clock stretcher tests if a passive mode entry threshold is met. The threshold includes two conditions: the hop code must be zero, and phase selection must have reached a wraparound point that may have been corrected for a delay line offset.Type: GrantFiled: June 3, 2021Date of Patent: March 29, 2022Assignee: SAMBANOVA SYSTEMS, INC.Inventors: Fahim ur Rahman, Mahmood Khayatzadeh, Jin-Uk Shin
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Patent number: 11270751Abstract: A pseudo static random access memory and a method for writing data thereof are provided. In the method, a basic clock signal having a basic cycle is provided. A chip enable signal is enabled to perform a write operation and write data is received during an enabled time interval of the chip enable signal. A plurality of internal clock signals is generated sequentially at intervals of the basic cycle according to a write command enable signal. A refresh conflict signal is received and it is determined whether the refresh conflict signal is enabled. When the refresh conflict signal is enabled, the internal clock signals are delayed, and the write data is written to a selected sensing amplifier according to the delayed internal clock signals.Type: GrantFiled: April 24, 2020Date of Patent: March 8, 2022Assignee: Winbond Electronics Corp.Inventor: Yuji Nakaoka
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Patent number: 11256286Abstract: The electronic circuit for multiphase clock skew calibration of at least one example embodiment provides a novel low power solution to detect clock skew errors with very high accuracy, of the order of a few femto seconds, and corrects clock skew errors and decreases and/or minimizes high frequency jitter in a data path of the electronic circuit.Type: GrantFiled: April 5, 2021Date of Patent: February 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sethu Mathavan Meikanda Muthu Ayyanar, Tamal Das, Avneesh Singh Verma
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Patent number: 11228279Abstract: Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.Type: GrantFiled: December 14, 2020Date of Patent: January 18, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Cheng-Hsiang Hsieh
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Patent number: 11218151Abstract: A system for performing a phase control operation includes: an internal clock generation circuit configured to generate an internal clock by delaying a clock by a first delay variation, and generate a reference clock by delaying the clock by a second delay variation, wherein the internal clock generation circuit generates the internal clock by delaying the clock by the first delay variation which is controlled according to a phase difference between the internal clock and the reference clock; and a data input/output circuit configured to input/output data in synchronization with the internal clock.Type: GrantFiled: August 27, 2020Date of Patent: January 4, 2022Assignee: SK hynix Inc.Inventor: Geun Ho Choi
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Patent number: 11169564Abstract: A timing circuit can include: a low-precision clock source configured to generate a low-precision clock signal; a high-precision clock source configured to intermittently generate a high-precision clock signal; and a cycle conversion circuit configured to count the pulses of the high-precision clock signal and the low-precision clock signal during a same period, and to obtain a conversion cycle according to count results and a rated cycle of the high-precision clock signal.Type: GrantFiled: August 31, 2020Date of Patent: November 9, 2021Assignee: Nanjing Silergy Micro Technology Co., Ltd.Inventors: Xingyue Wang, Ran Li, Junjie Qiao
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Patent number: 11169563Abstract: A semiconductor circuit apparatus of the present disclosure includes a control circuit controlling a clock signal externally input, a drive circuit performing a switching operation according to a pulse signal provided by the control circuit, a series connection circuit including an inductor element, a switch element, and a capacitive element connected in series between a signal line and a fixed potential node, the series connection circuit forming an LC resonance circuit, and a level detection circuit having an input end connected to the signal line. An output from the level detection circuit is fed back to the control circuit.Type: GrantFiled: August 9, 2019Date of Patent: November 9, 2021Assignee: Sony Semiconductor Solutions CorporationInventors: Takanori Saeki, Masayuki Katakura, Tatsuya Shirakawa, Yoshinori Tanaka
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Patent number: 11171659Abstract: Techniques for reliable clock speed change and associated circuits and methods are disclosed. Internal voltage supplies of semiconductor devices may include oscillators and charge pump circuits. The oscillator may include at least two clock paths for generating clock signals having different clock frequencies, which can be provided to the charge pump circuit. Further, the oscillator may generate a reset signal configured to activate one clock path over the other (e.g., changing clock speeds). In some embodiments, the oscillator includes a flip-flop to align the reset signal with respect to an edge of an input clock signal supplied to the oscillator such that unintentional (undesired, unexpected) features in the output signal of the oscillator can be avoided when the oscillator changes clock speeds.Type: GrantFiled: January 5, 2021Date of Patent: November 9, 2021Assignee: Micron Technology, Inc.Inventors: Pu Yang, Yantao Ma
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Patent number: 11119554Abstract: A power management integrated circuit (PMIC) modeling system for a power distribution network (PDN) analysis, includes a power supply configured to supply a source current for driving a load, a resistance setting unit configured to monitor a load current being supplied to the load, and generate a current comparison value by comparing a first current value of the load current at a current time with a second current value of the load current at a previous time, and a controller configured to, based on the current comparison value generate a control signal for changing a variable resistance of the resistance setting unit, and control the power supply to change the source current. The resistance setting unit is further configured to, based on the control signal, change a resistance value of the variable resistance.Type: GrantFiled: April 10, 2019Date of Patent: September 14, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Soon Keol Ryu
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Patent number: 11121851Abstract: A system includes a differential clock source configured to provide a reference clock signal and an inverted version of the reference clock signal. The system also includes a quadrature clock source configured to provide a quadrature clock signal that is phase-shifted relative to the reference clock signal. The system also includes a differential sensing circuit coupled to the differential clock source and the quadrature clock source. The differential sensing circuit is configured to determine skew of the quadrature clock signal based on the reference clock signal, the inverted version of the reference clock signal, and the quadrature clock signal.Type: GrantFiled: January 15, 2020Date of Patent: September 14, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Manu Basil, Mohan Yang, Yongseon Koh, Roland Ribeiro
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Patent number: 11115011Abstract: A system comprises pulse generation and measurement circuitry comprising a plurality of pulse generator circuits and a plurality of ports, and management circuitry. The management circuitry is operable to analyze a specification of a controlled system and controlled elements that comprises a definition of a controlled element of the control system, and a definition of one or more pulses available for transmission by the control system. The management circuitry is operable to configure, based on the specification, the pulse generation and measurement circuitry to: generate the one or more pulses via one or more of the plurality of pulse generator circuits; and output the one or more pulses to the controlled element via one or more of the plurality of ports.Type: GrantFiled: November 4, 2020Date of Patent: September 7, 2021Inventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan, Tal Shani
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Patent number: 11101108Abstract: A nanosecond pulser system is disclosed. In some embodiments, the nanosecond pulser system may include a nanosecond pulser having a nanosecond pulser input; a plurality of switches coupled with the nanosecond pulser input; one or more transformers coupled with the plurality of switches; and an output coupled with the one or more transformers and providing a high voltage waveform with a amplitude greater than 2 kV and a frequency greater than 1 kHz based on the nanosecond pulser input. The nanosecond pulser system may also include a control module coupled with the nanosecond pulser input; and an control system coupled with the nanosecond pulser at a point between the transformer and the output, the control system providing waveform data regarding an high voltage waveform produced at the point between the transformer and the output.Type: GrantFiled: April 14, 2020Date of Patent: August 24, 2021Assignee: EAGLE HARBOR TECHNOLOGIES INC.Inventors: Ilia Slobodov, John Carscadden, Kenneth Miller, Timothy Ziemba, Huatsern Yeager, Eric Hanson, TaiSheng Yeager, Kevin Muggli
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Patent number: 10996738Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.Type: GrantFiled: December 18, 2018Date of Patent: May 4, 2021Assignee: Marvell Asia Pte, Ltd.Inventors: Rabin Sugumar, Bharath Upputuri, Bruce Kauffman, Novinder Waraich, Bivraj Koradia, Paul Sebata
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Patent number: 10996709Abstract: A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.Type: GrantFiled: August 30, 2019Date of Patent: May 4, 2021Assignee: Intel CorporationInventors: Gururaj Shamanna, Mitesh Goyal, Jagadeesh Chandra Salaka, Purna C. Nayak, Abhishek Sharma, Harishankar Sahu
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Patent number: 10980406Abstract: The disclosure extends to systems and methods for reducing the area of an image sensor by reducing the imaging sensor pad count used for data transmission and clock generation.Type: GrantFiled: December 30, 2019Date of Patent: April 20, 2021Assignee: DePuy Synthes Products, Inc.Inventors: Laurent Blanquart, Donald M. Wichern
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Patent number: 10887134Abstract: A circuit device includes a first terminal, a second terminal, a receiving circuit configured to receive the differential signals via the first terminal and the second terminal, a first signal line connecting a first input terminal of the receiving circuit and the first terminal, a second signal line connecting a second input terminal of the receiving circuit and the second terminal, a first capacitor circuit having one end connected to the first signal line, a second capacitor circuit having one end connected to the second signal line, and a detection circuit configured to detect a duty cycle of an output signal that is output from the receiving circuit.Type: GrantFiled: November 27, 2019Date of Patent: January 5, 2021Assignee: SEIKO EPSON CORPORATIONInventors: Yoshihito Miyashita, Akira Morita
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Patent number: 10860051Abstract: A clock gating system (CGS) includes a digital power estimator configured to generate indications of a predicted energy consumption per cycle of a clock signal and a maximum energy consumption per cycle of the clock signal. The CGS further includes a voltage-clock gate (VCG) circuit coupled to the digital power estimator. The VCG circuit is configured to gate and un-gate the clock signal based on the indications prior to occurrence of a voltage droop event and using hardware voltage model circuitry of the VCG circuit. The VCG circuit is further configured to gate the clock signal based on an undershoot phase associated with the voltage droop event and to un-gate the clock signal based on an overshoot phase associated with the voltage droop event.Type: GrantFiled: September 6, 2019Date of Patent: December 8, 2020Assignee: Qualcomm IncorporatedInventors: Vijay Kiran Kalyanam, Eric Wayne Mahurin
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Patent number: 10862465Abstract: A system comprises pulse generation and measurement circuitry comprising a plurality of pulse generator circuits and a plurality of ports, and management circuitry. The management circuitry is operable to analyze a specification of a controlled system and controlled elements that comprises a definition of a controlled element of the control system, and a definition of one or more pulses available for transmission by the control system. The management circuitry is operable to configure, based on the specification, the pulse generation and measurement circuitry to: generate the one or more pulses via one or more of the plurality of pulse generator circuits; and output the one or more pulses to the controlled element via one or more of the plurality of ports.Type: GrantFiled: December 10, 2019Date of Patent: December 8, 2020Inventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan, Tal Shani