Clock Or Pulse Waveform Generating Patents (Class 327/291)
  • Patent number: 11119554
    Abstract: A power management integrated circuit (PMIC) modeling system for a power distribution network (PDN) analysis, includes a power supply configured to supply a source current for driving a load, a resistance setting unit configured to monitor a load current being supplied to the load, and generate a current comparison value by comparing a first current value of the load current at a current time with a second current value of the load current at a previous time, and a controller configured to, based on the current comparison value generate a control signal for changing a variable resistance of the resistance setting unit, and control the power supply to change the source current. The resistance setting unit is further configured to, based on the control signal, change a resistance value of the variable resistance.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Soon Keol Ryu
  • Patent number: 11121851
    Abstract: A system includes a differential clock source configured to provide a reference clock signal and an inverted version of the reference clock signal. The system also includes a quadrature clock source configured to provide a quadrature clock signal that is phase-shifted relative to the reference clock signal. The system also includes a differential sensing circuit coupled to the differential clock source and the quadrature clock source. The differential sensing circuit is configured to determine skew of the quadrature clock signal based on the reference clock signal, the inverted version of the reference clock signal, and the quadrature clock signal.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: September 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manu Basil, Mohan Yang, Yongseon Koh, Roland Ribeiro
  • Patent number: 11115011
    Abstract: A system comprises pulse generation and measurement circuitry comprising a plurality of pulse generator circuits and a plurality of ports, and management circuitry. The management circuitry is operable to analyze a specification of a controlled system and controlled elements that comprises a definition of a controlled element of the control system, and a definition of one or more pulses available for transmission by the control system. The management circuitry is operable to configure, based on the specification, the pulse generation and measurement circuitry to: generate the one or more pulses via one or more of the plurality of pulse generator circuits; and output the one or more pulses to the controlled element via one or more of the plurality of ports.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: September 7, 2021
    Inventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan, Tal Shani
  • Patent number: 11101108
    Abstract: A nanosecond pulser system is disclosed. In some embodiments, the nanosecond pulser system may include a nanosecond pulser having a nanosecond pulser input; a plurality of switches coupled with the nanosecond pulser input; one or more transformers coupled with the plurality of switches; and an output coupled with the one or more transformers and providing a high voltage waveform with a amplitude greater than 2 kV and a frequency greater than 1 kHz based on the nanosecond pulser input. The nanosecond pulser system may also include a control module coupled with the nanosecond pulser input; and an control system coupled with the nanosecond pulser at a point between the transformer and the output, the control system providing waveform data regarding an high voltage waveform produced at the point between the transformer and the output.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: August 24, 2021
    Assignee: EAGLE HARBOR TECHNOLOGIES INC.
    Inventors: Ilia Slobodov, John Carscadden, Kenneth Miller, Timothy Ziemba, Huatsern Yeager, Eric Hanson, TaiSheng Yeager, Kevin Muggli
  • Patent number: 10996738
    Abstract: A system includes a controller configured to receive a signal indicating whether a droop event has occurred. The system also includes a plurality of delay elements where each delay element of the plurality of delay elements responsive to a signal from the controller receives an input signal and outputs an output signal that is a delayed version of the input signal. At least one delay element of the plurality of delay elements receives a clocking signal as its input signal. The system also includes a selector configured to select rising edges and falling edges of output signals from the plurality of delay elements to form a modified clocking signal. The modified clocking signal is a modified version of the clocking signal.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: May 4, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Rabin Sugumar, Bharath Upputuri, Bruce Kauffman, Novinder Waraich, Bivraj Koradia, Paul Sebata
  • Patent number: 10996709
    Abstract: A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Gururaj Shamanna, Mitesh Goyal, Jagadeesh Chandra Salaka, Purna C. Nayak, Abhishek Sharma, Harishankar Sahu
  • Patent number: 10980406
    Abstract: The disclosure extends to systems and methods for reducing the area of an image sensor by reducing the imaging sensor pad count used for data transmission and clock generation.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: April 20, 2021
    Assignee: DePuy Synthes Products, Inc.
    Inventors: Laurent Blanquart, Donald M. Wichern
  • Patent number: 10887134
    Abstract: A circuit device includes a first terminal, a second terminal, a receiving circuit configured to receive the differential signals via the first terminal and the second terminal, a first signal line connecting a first input terminal of the receiving circuit and the first terminal, a second signal line connecting a second input terminal of the receiving circuit and the second terminal, a first capacitor circuit having one end connected to the first signal line, a second capacitor circuit having one end connected to the second signal line, and a detection circuit configured to detect a duty cycle of an output signal that is output from the receiving circuit.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: January 5, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Yoshihito Miyashita, Akira Morita
  • Patent number: 10860051
    Abstract: A clock gating system (CGS) includes a digital power estimator configured to generate indications of a predicted energy consumption per cycle of a clock signal and a maximum energy consumption per cycle of the clock signal. The CGS further includes a voltage-clock gate (VCG) circuit coupled to the digital power estimator. The VCG circuit is configured to gate and un-gate the clock signal based on the indications prior to occurrence of a voltage droop event and using hardware voltage model circuitry of the VCG circuit. The VCG circuit is further configured to gate the clock signal based on an undershoot phase associated with the voltage droop event and to un-gate the clock signal based on an overshoot phase associated with the voltage droop event.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 8, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Vijay Kiran Kalyanam, Eric Wayne Mahurin
  • Patent number: 10862465
    Abstract: A system comprises pulse generation and measurement circuitry comprising a plurality of pulse generator circuits and a plurality of ports, and management circuitry. The management circuitry is operable to analyze a specification of a controlled system and controlled elements that comprises a definition of a controlled element of the control system, and a definition of one or more pulses available for transmission by the control system. The management circuitry is operable to configure, based on the specification, the pulse generation and measurement circuitry to: generate the one or more pulses via one or more of the plurality of pulse generator circuits; and output the one or more pulses to the controlled element via one or more of the plurality of ports.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 8, 2020
    Inventors: Yonatan Cohen, Nissim Ofek, Itamar Sivan, Tal Shani
  • Patent number: 10838636
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller—such as a non-volatile memory (NVM) controller—to adaptively and hierarchically scale clock signals distributed to its internal components. In various examples described herein, the data storage controller is configured to downscale the internal clocks of the controller for all processing sub-blocks that are in an Active Idle state (or in similar idle states where a component is active but has no tasks to perform). When an entire hierarchy of components is idle, the clock signal applied to the entire hierarchy is downscaled. By downscaling the clock for an entire hierarchy of components, power consumed by the corresponding clock tree is also reduced. In specific examples, clock signals are downscaled by a factor of thirty-two to reduce power consumption. NVMe examples are provided herein.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: November 17, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shay Benisty, Tal Sharifie, Leonid Minz
  • Patent number: 10841021
    Abstract: The present disclosure relates to a circuit for calibrating a baud rate. The circuit includes: a first counter connected to a receiving module of a serial port chip and configured to record a first low level duration of a data frame received by the receiving module; a second counter configured to: receive a bit sampling pulse generated from sampling the data frame according to a current baud rate of the receiving module, and record a quantity of the bit sampling pulse in the first low level duration; a divider, connected to the first counter and the second counter and calculate a calibration baud rate according to the first low level duration and the quantity of the bit sampling pulse in the first low level duration; and a selector, connected to the receiving module and the divider and configured to output the calibration baud rate to the receiving module.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 17, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Huizhao Wang
  • Patent number: 10817684
    Abstract: A semiconductor device, a non-contact electronic device, and a period detection method are provided. The semiconductor device includes an edge detection unit that detects edges of one of rises and falls of a data signal received via radio waves, a counting unit that counts a number of N-divided clock signals having a frequency which is 1/N (N is an integer equal to or greater than 2) of a frequency of a reference clock signal having a predetermined frequency according to the data signal in a section of the adjacent edges, a fraction counting unit that counts fractions of the N-divided clock signals determined according to a phase difference between the edge and the N-divided clock signal, and a first addition unit that adds a value obtained by multiplying the counted number by N to the fractions, and outputs a resultant value as a period of the data signal.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: October 27, 2020
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Yuki Imatoh
  • Patent number: 10803923
    Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita
  • Patent number: 10790834
    Abstract: A semiconductor device includes a delay code generation circuit configured to adjust a shifting code for delaying a first internal clock, by comparing phases of a second internal clock and a delayed clock, the delayed clock generated by delaying the first internal clock, and configured to generate a first delay code and a second delay code from the shifting code.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: September 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Jayoung Kim
  • Patent number: 10777118
    Abstract: A shift register and a method for driving the same, a gate driving circuit, and a display device, the shift register includes: a pull-up node control circuit allowing a potential of a pull-up node to become high according to a first input signal and a second input signal; a first capacitor coupled between a signal output terminal and the pull-up node of the shift register; a pull-down node control circuit controlling a potential of the pull-down node according to the second clock signal and the third clock signal and the potential of the pull-up node; an output circuit controlling an output of a gate driving signal at the signal output terminal; and a pull-down circuit allowing the potential of the pull-up node and a potential of the signal output terminal to become low.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 15, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xueguang Hao
  • Patent number: 10770003
    Abstract: A transfer circuit includes an input circuit, a reset circuit, an output circuit, and an output stabilizer circuit, and obtains an input signal at an input terminal, holds the input signal, and outputs the input signal from an output terminal as an output signal in synchronization with a clock signal. The transfer circuit includes an inverter circuit that has an input terminal connected to at least one of the input and output terminals of the transfer circuit, and outputs, from an output terminal, an inverted signal having an inverted polarity of at least one of the input and output signals. The reset circuit includes a first transistor having a control signal end connected to the output terminal of the inverter circuit, the first transistor switching continuity and discontinuity of a signal path between one end of a first capacitor that holds the input signal and a first power supply.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: September 8, 2020
    Assignee: JOLED INC.
    Inventor: Tetsuro Yamamoto
  • Patent number: 10727906
    Abstract: A near-field communication device includes an oscillating circuit, a rectifying bridge configured to rectify a voltage across the oscillating circuit, and a voltage-controlled oscillator configured to supply a reference frequency. The voltage-controlled oscillator is powered and controlled by a voltage that is a function of an output voltage of the rectifying bridge.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: July 28, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Alexandre Tramoni
  • Patent number: 10712767
    Abstract: According to one embodiment, there is provided a clock generator including a frequency divider configured to generate a divided frequency clock of a frequency lower than that of a source clock by performing mask processing on part of a pulse train of the source clock.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: July 14, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Satoshi Kamiya
  • Patent number: 10715122
    Abstract: An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Guolei Yu, Ajay Kumar Kosaraju, Marko Koski
  • Patent number: 10690721
    Abstract: A glitch detector includes an input flip-flop clocked by a clock signal and having a non-inverting data output, an inverting data output, and a data input receiving input from the inverting data output, the input flip-flop generating a divided version of the clock signal at the non-inverting data output. A configurable delay chain receives the divided version of the clock signal and generates a delayed version of the divided version of the clock signal as a delay output. An intermediate flip-flop clocked by the clock signal has a data input receiving the delay output, the intermediate flip-flop generating an intermediate output as a function of the delay output. A logic circuit receives the divided version of the clock signal and the intermediate output, and generates a glitch detect signal by performing a logical operation on the divided version of the clock signal and the intermediate output.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 23, 2020
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventor: Beng-Heng Goh
  • Patent number: 10684671
    Abstract: Adaptively controlling drive strength of multiplexed power from supply power rails in a power multiplexing system to a powered circuit is disclosed. A power multiplexing circuit in the power multiplexing system includes a plurality of supply selection circuits (e.g., head switches) each coupled between a respective supply power rail and an output power rail coupled to the powered circuit. The power multiplexing circuit is configured to activate a selected supply selection circuit to switch coupling of an associated supply power rail to the output power rail to power the powered circuit. In one example, the supply selection circuits each include a plurality of power switch selection circuits coupled to an associated supply power rail. The power switch selection circuits are configured to be activated and deactivated by a control circuit to adjust drive strength of a multiplexed supply power rail based on operational conditions, which can account for performance variations.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: June 16, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Shraddha Sridhar, Yeshwant Nagaraj Kolla, Neel Shashank Natekar
  • Patent number: 10686457
    Abstract: A circuit device includes an oscillation signal generation circuit for generating an oscillation signal with an oscillation frequency set by frequency control data, and a processing circuit. The processing circuit includes a counter for performing a count process based on the oscillation signal, and a latch circuit for holding a count value of the counter based on a reference signal. The processing circuit performs a loop filter process on a phase comparison result based on output data of the latch circuit to output the frequency control data, holds information based on the phase comparison result when the holdover is detected, and outputs the frequency control data based on the information held, in a holdover period.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: June 16, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Kentaro Seo
  • Patent number: 10673478
    Abstract: According to one embodiment of an asynchronous communication device, the transmitter circuit includes a signal generation circuit to output a first pulse signal and a delay compensation circuit to receive the first pulse signal, perform delay compensation processing on the pulse width of the first pulse signal, and output a second pulse signal obtained by the delay compensation processing. The delay unit receives the second pulse signal, causes delay in the rising or falling edge of the second pulse signal, and outputs a third pulse signal in which the delay is caused. The receiver circuit receives the third pulse signal and performs signal processing based on the third pulse signal. The delay compensation circuit, while maintaining the pulse period of the first pulse signal, performs pre-compensation processing on the first pulse signal based on a delay value of the delay to be caused by the delay unit.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 2, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kyoji Harada, Ryouta Niwa, Katsumichi Katou
  • Patent number: 10644713
    Abstract: A method of enhancing SAR ADC performance includes employing PVT processor to correct process, voltage and temperature (PVT) variation. The PVT processor senses process, supply voltage and temperature information then maximize the time for SAR binary search process. The PVT processor first applies coarse optimization to correct process and voltage variation then applies fine optimization to correct the temperature variation. The SAR ADC is operated at its optimized PVT condition and its performance is enhanced after PVT optimization.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 5, 2020
    Assignee: IPGREAT INCORPORATED
    Inventor: Yuan-Ju Chao
  • Patent number: 10622041
    Abstract: A semiconductor device includes: a clock generation circuit suitable for generating first and second write clocks that correspond respectively to a rising clock and a falling clock of an external clock during a write leveling operation, and for generating an input clock based on a delay of a write command by a delay time based on the rising clock during a write operation; a first transmission line suitable for transmitting the first write clock or the input clock as a first transmission clock; and a second transmission line suitable for transmitting the second write clock as a second transmission clock.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: April 14, 2020
    Assignee: SK hynix Inc.
    Inventor: Young-Hoon Kim
  • Patent number: 10606306
    Abstract: A method and circuit are provided to reduce power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes series and shunt reactive circuit elements, such as series inductive reactance and a shunt inductive susceptance, configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: March 31, 2020
    Assignee: INPHI CORPORATION
    Inventor: Tomas Alexander Dusatko
  • Patent number: 10594521
    Abstract: Apparatuses and methods for performing asynchronous multicarrier communications are provided. One such method involves generating, at a first wireless device, a waveform including one or more carriers, shaping the waveform to reduce interference between the waveform and adjacent waveforms, and transmitting, on a spectrum, the shaped waveform asynchronously.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 17, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Joseph Binamira Soriaga, Tingfang Ji, John Edward Smee, Naga Bhushan, Peter Gaal, Krishna Kiran Mukkavilli, Alexei Yurievitch Gorokhov
  • Patent number: 10548665
    Abstract: A sub-microsecond pulsed electric field generator is disclosed. The field generator includes a controller, which generates a power supply control signal and generates a pulse generator control signal, and a power supply, which receives the power supply control signal and generates one or more power voltages based on the received power supply control signal. The field generator also includes a pulse generator which receives the power voltages and the pulse generator control signal, and generates one or more pulses based on the power voltages and based on the pulse generator control signal. The controller receives feedback signals representing a value of a characteristic of or a result of the pulses and generates at least one of the power supply control signal and the pulse generator control signal based on the received feedback signals.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: February 4, 2020
    Assignee: PULSE BIOSCIENCES, INC.
    Inventors: Shu Xiao, Brian G. Athos, Mark P. Kreis, David J. Danitz, Darrin R. Uecker
  • Patent number: 10547414
    Abstract: A transmitter broadcasts a signal having a different code characteristic for each of several directions. A receiver receives the broadcast signal from one of the directions and generates an expected signal for that direction based on the code characteristic for that direction. The receiver detects the broadcast signal from the direction based on the expected signal for that direction.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: January 28, 2020
    Assignee: Greenwich Technologies Associates
    Inventor: Carl M. Elam
  • Patent number: 10517469
    Abstract: An endoscopic system for use a controlled light environment is disclosed. In an implementation, the system may include an endoscope having an image sensor, an emitter, and a control circuit. The control circuit controls a frequency of the emitter in response to signals that correspond to the frequency of the emitter. The image sensor has input and output pads, where a pad count is reduced by not having a dedicated input synchronization clock pad. A frame period is divided into three defined states: a rolling-readout state during which image data is output through the pads, a service-line state during which non-image data is output through the pads, and a configuration state during which instruction data is received by the image sensor through the pads. Signal transitions are encoded within output data from the image sensor and correspond with defined states.
    Type: Grant
    Filed: March 15, 2014
    Date of Patent: December 31, 2019
    Assignee: DePuy Synthes Products, Inc.
    Inventors: Laurent Blanquart, Donald M. Wichern
  • Patent number: 10505559
    Abstract: A method of enhancing SAR ADC performance includes employing PVT processor to correct process, voltage and temperature (PVT) variation. The PVT processor senses process, supply voltage and temperature information then maximize the time for SAR binary search process. The PVT processor first applies coarse optimization to correct process and voltage variation then applies fine optimization to correct the temperature variation. The SAR ADC is operated at its optimized PVT condition and its performance is enhanced after PVT optimization.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: December 10, 2019
    Assignee: IPGreat Incorporated
    Inventor: Yuan-Ju Chao
  • Patent number: 10396812
    Abstract: A register and an analog-digital converter capable of detecting signal distortion in high-radiation environments are provided. The register includes: a signal input terminal receiving a digital signal; and a digital single event transient (DSET) detection unit detecting whether information of the digital signal input through the signal input terminal is distorted, wherein the DSET detection unit includes a first output terminal through which a first detection signal is output, the first detection signal being used to determine whether at least one of rising edge timing information and falling edge timing information of the digital signal is distorted.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 27, 2019
    Assignees: KOREA ATOMIC ENERGY RESEARCH INSTITUTE, KOREA UNIVERSITY RESEARCH & BUSINESS FOUNDATION
    Inventors: In Yong Kwon, Yong Seok Lee, Jung Yeol Yeom, Chang Hwoi Kim
  • Patent number: 10340021
    Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: July 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiko Amano, Kouhei Toyotaka, Hiroyuki Miyake, Aya Miyazaki, Hideaki Shishido, Koji Kusunoki
  • Patent number: 10319422
    Abstract: A decoder according to one embodiment of the invention includes a set of lines, a resonator circuit, a set of input leads for receiving input signals, and a set of switches for coupling some of the lines within the set of lines to the resonator circuit in response to the input signals while the other lines within the set of lines are at a first binary voltage. The lines are coupled to a set of pointer circuits. The pointer circuits perform logic functions on the signals on the lines when the resonating signal is at a second binary voltage opposite the first binary voltage to thereby decode the input signals. Because the lines are driven high and low by a resonator circuit, the decoder circuit power consumption is less than it would be if the lines were pulled up and down by a set of pullup and pulldown transistors.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 11, 2019
    Inventor: David A. Huffman
  • Patent number: 10320509
    Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 11, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Yunteng Huang, Adam B. Eldredge, Gregory J. Richmond
  • Patent number: 10320286
    Abstract: The absorption circuit of the present invention is applied in a feed circuit, wherein the absorption circuit comprises a comparison unit and a regulation unit, and the comparison unit is employed to receive a voltage of a transformer primary dotted terminal of the feed circuit, and to compare the voltage with a first preset voltage and a second preset voltage and to output a comparison result, and the regulation unit is employed to regulate a resistor and a capacitor coupled to the transformer according to the comparison result, wherein the first preset voltage is larger than the second preset voltage. Therefore, the present invention can control the resistor and the capacitor coupled to the transformer according to the leakage inductance (i.e. the voltage) of the transformer, and then to adaptively restrain the corresponding voltage peak and EMI.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 11, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Dan Cao
  • Patent number: 10303200
    Abstract: A method for implementing clock dividers includes providing, in response to detecting a voltage drop at a processor core, an input clock signal to a transmission gate multiplexer for selecting between one of two stretch-enable signals. In some embodiments, selecting between the one of two stretch-enable signals includes inputting a set of core clock enable signals into a clock divider circuit, and modifying the set of core clock enable signals to generate the stretch-enable signals. An output clock signal is generated based on the selected stretch-enable signal.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: May 28, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Deepesh John, Steven Kommrusch, Vibhor Mittal
  • Patent number: 10283176
    Abstract: Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: May 7, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hun-dae Choi, Young-kwon Jo
  • Patent number: 10234892
    Abstract: A method and circuit are provided to reduce power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes series and shunt reactive circuit elements, such as series inductive reactance and a shunt inductive susceptance, configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: March 19, 2019
    Assignee: INPHI CORPORATION
    Inventor: Tomas Alexander Dusatko
  • Patent number: 10224721
    Abstract: A switch control circuit to switch off communication channels between a baseboard management controller (BMC) and a backplane chip when not needed includes a logic component and a switch circuit. The switch circuit is configured for coupling between the BMC and the backplane chip in a device. The logic component obtains a logic control signal from the BMC, and outputs a switch signal to the switch circuit to turn on or turn off the switch circuit according to the logic control signal. An electronic device including the switch control circuit is also provided.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 5, 2019
    Assignee: HONGFUJIN PRECISION ELECTRONICS (TIANJIN) C
    Inventor: Fei Luo
  • Patent number: 10200192
    Abstract: Apparatus and method for enacting data security in a data storage device, such as by protecting against a differential power analysis (DPA) attack. In some embodiments, a dithered clock signal is generated having a succession of clock pulse segments. Each of the clock pulse segments has a different respective frequency selected in response to a first random number and a different overall duration selected in response to a second random number. The different segment frequencies are selected by supplying the first random number to a lookup table, and the different segment durations are obtained by initializing a timer circuit using the second random number. The dithered clock signal is used to clock a programmable processor during execution of a cryptographic function.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: February 5, 2019
    Assignee: Seagate Technology LLC
    Inventor: Bruce D. Buch
  • Patent number: 10162379
    Abstract: A system clock signal distributed to electronic configurable and reconfigurable computing devices within a distributed computing system. The distributed computing devices, which may be dual-die chip carriers (DDCC), include input addressable data/clock ports on which system clock signals are accepted and may be propagated on one or more data/clock output ports. The input and/or output ports of various distributed computing devices may be configured and reconfigured according to system preferences or requirements.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: December 25, 2018
    Assignee: Advanced Processor Architectures, LLC
    Inventors: Louis Edumund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 10127875
    Abstract: The present disclosure provides a shift register unit. The shift register unit includes a pre-charge reset module; a pull-up module; a pull-down module; a first pull-down control module; and a second pull-down control module. The pre-charge reset module is connected to a forward scanning control signal input terminal, a reverse scanning control signal input terminal, a first signal input terminal, a second signal input terminal, and a pull-up control node. The pull-up module is connected to the pull-up control node, an input terminal of a first clock signal, and a signal output terminal. The first pull-down control module is connected to a pull-down control node, the forward scanning control signal input terminal, the reverse scanning control signal input terminal, the first signal input terminal, and the second signal input terminal.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: November 13, 2018
    Assignees: BOE TECHNOLOGY CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Bo Wu, Xiaojing Qi, Wen Tan
  • Patent number: 10042383
    Abstract: A clock calibration method of a navigation system is provided. The clock calibration method includes: entering a calibration mode; sequentially issuing, by a host, a count start signal and a count end signal separated by a time interval; counting a local oscillation frequency of a local oscillator when a navigation device receives the count start signal from the host; disabling the counting when the navigation device receives the count end signal from the host and generating a current count; generating a calibration signal according to the current count and a predetermined count corresponding to the time interval; and calibrating the local oscillation frequency of the local oscillator according to the calibration signal.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: August 7, 2018
    Assignee: PIXART IMAGING INC.
    Inventors: Kevin Len-Li Lim, Zi-Hao Tan
  • Patent number: 10027382
    Abstract: Circuit connectors for establishing EHF communication include a receiver configured to receive a transmitted EHF electromagnetic signal, and an output circuit coupled to the receiver. The output circuit has two states of operation that correspond to enabling a signal output and disabling the signal output. The output circuit is also configured to change its state of operation responsive to a state of a control signal, and a controller is coupled to the receiver and configured to produce the control signal. The control signal has two states that correspond to a first condition when the received signal exceeds a first threshold and a second condition when the received signal is less than a second threshold.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: July 17, 2018
    Assignee: Keyssa, Inc.
    Inventors: Ian A. Kyles, Gary D. McCormack, Norbert Seitz
  • Patent number: 9998102
    Abstract: A phase and frequency control circuit may be provided. The phase and frequency control circuit may include a division circuit configured to generate a plurality of divided signals by dividing an input signal. The phase and frequency control circuit may include a timing control circuit configured to generate a plurality of timing control signals by sampling the plurality of divided signals according to a phase control code and a sampling reference signal.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: June 12, 2018
    Assignee: SK hynix Inc.
    Inventor: In Hwa Jung
  • Patent number: 9960620
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: May 1, 2018
    Assignee: Navitas Semiconductor, Inc.
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
  • Patent number: 9959185
    Abstract: A memory system includes a memory device, a switch device, and a built-in self-test circuit. The memory device is for storing data and toggling a notification signal whenever a read operation or a write operation is completed. The switch device has a first input terminal for receiving an external clock signal, a second input terminal coupled to the memory device for receiving the notification signal, a select terminal for receiving a selection signal, and an output terminal for outputting a memory clock signal to the memory device. The memory clock signal is one of the external clock signal and the notification signal. The built-in self-test circuit is for outputting a control signal required by the memory device to perform the read operation or the write operation and check whether the memory device functions normally.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 1, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Hsin-Wen Chen
  • Patent number: 9939841
    Abstract: A method and circuit are provided to reduce the power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes a series inductive reactance and a shunt inductive susceptance configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: April 10, 2018
    Assignee: INPHI CORPORATION
    Inventor: Tomas Alexander Dusatko