Abstract: A receiver circuit that includes a pair of pre-stage amplifier circuits and a post-stage amplifier circuit is introduced. The pre-stage amplifier circuits are configured to receive an input signal and a reference voltage signal, output first pre-stage amplifying signals through a first connection node and a second connection node separately, and output second pre-stage amplifying signals through a third connection node and a fourth connection node separately. The post-stage amplifier circuit is configured to receive the first pre-stage amplifying signals and the second pre-stage amplifying signals from the pair of pre-stage amplifier circuits through the first connection node, the second connection node, the third connection node and the fourth connection node separately, and output a post amplifying signal according to the first pre-stage amplifying signals and the second pre-stage amplifying signals.

Abstract: A bit line sense amplifier includes: a first inverter having an input terminal connected to a first sensing node and an output terminal connected to a second inner bit line; a second inverter having an input terminal connected to a second sensing node and an output terminal connected to a first inner bit line; a first capacitor connected between the first sensing node and the first inner bit line; a second capacitor connected between the second sensing node and the second inner bit line; an isolation unit configured to cut off a connection between the first inner bit line and a second bit line; and an offset cancellation unit configured to connect the first sensing node to the second inner bit line, the first inner bit line to the first bit line, the second sensing node to the first inner bit line, and the second inner bit line to the second bit line.

Abstract: A semiconductor device including a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n?1 first signals having two signal levels. The device includes a jitter compensation circuit configured to receive the n?1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n?1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n?1 first signals transitions from the second signal level to the first signal level, to output n?1 second signals.

Abstract: A photosensitive device includes a peripheral circuit semiconductor region, a photosensitive circuit semiconductor region including at least one group of at least two photosensitive elements configured to generate a photoelectric signal on a node called critical node. The device further includes an integrator circuit per group of photosensitive elements, each including: a differential circuit for each photosensitive element of the group, in the photosensitive circuit semiconductor region, an amplification circuit, in the peripheral circuit semiconductor region, and a feedback circuit for each photosensitive element of the group, comprising a capacitive element located in the photosensitive circuit semiconductor region coupled between the output node of the amplification circuit and the respective critical node.

Abstract: An image sensor includes a first amplifier comparing and amplifying a first voltage signal received from a first column line, and a ramp signal; a second amplifier amplifying an output of the first amplifier; a third amplifier comparing and amplifying a second voltage signal received from a second column line, and the ramp signal; and a fourth amplifier amplifying an output of the third amplifier, wherein the second amplifier and the fourth amplifier output a decision signal at different points in time by dummy switch control split.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and an offset voltage storage unit electrically connected to the amplification module; wherein, in an offset cancellation stage of the sense amplifier, the sense amplifier is configured to comprise a current mirror structure to store an offset voltage of the amplification module in an offset voltage storage unit. The present disclosure can realize the offset cancellation of the sense amplifier.

Abstract: The present disclosure provides a readout circuit, a memory, and a method of reading out data of a memory. The readout circuit includes: a sense amplifier and an isolation unit, the sense amplifier being connected to a bit line and a complementary bit line through the isolation unit, the bit line being connected to a memory cell and the complementary bit line being connected to a memory cell, and the isolation unit being configured to disconnect the sense amplifier from the bit line and the complementary bit line in response to an isolation signal; and an offset canceling unit, configured to perform an offset cancellation on the sense amplifier in response to an offset canceling signal, at least a part of a stage of a charge sharing being performed at the same time as at least a part of a stage of an operation of the offset canceling unit.

Abstract: To enable preferable signal transmission between a plurality of daisy-chained devices at low cost. A transmission device generates a plurality of signals having different voltage levels and outputs the signals to a communication line at different timings. For example, the plurality of signals having different voltage levels is generated by a plurality of drivers or one driver. A receiving side can immediately determine whether or not it is information to be passed to the subsequent stage on the basis of only a difference in voltage level without logically analyzing contents of a signal, and cost of components such as a memory, verification cost, or the like are unnecessary so that the cost can be reduced.

Abstract: In some examples, this description provides for an apparatus. The apparatus includes a power switch having a power switch source configured to receive an input voltage, a power switch drain, and a power switch gate. The apparatus also includes a current sense component coupled to the power switch. The apparatus also includes a current limiting circuit coupled to the power switch gate, the power switch drain, and the current sense component. The apparatus also includes an over-current protection (OCP) circuit coupled to the power switch source, the power switch drain, and the power switch gate. The apparatus also includes an output voltage (VOUT) clamp coupled to the power switch drain and the power switch gate.

Abstract: A multichannel magnetic field sensor including a plurality of magnetic field sensing elements includes a multiplexed signal path. A front end amplifier is coupled to receive a first magnetic field signal during a first time interval and a second magnetic field signal during a second time interval. A first low pass filter processes the amplified signal during the first time interval and a second low pass filter processes the amplified signal during the second time interval. A sinc filter is coupled to receive the first low pass filtered signal during the first time interval and the second low pass filtered signal during the second time interval. A Schmitt trigger circuit includes a comparator to process the sinc filter output signal and to generate a first comparator output signal during the first time interval and a second comparator output signal is provided during the second time interval.

Abstract: A structure for magnetic flux sensor conditioning is presented which partitions an input analog signal of unknown integrity into two: susceptible and insusceptible. The structure scrutinizes the susceptible signal partition, in view of additional guard sensor information, through a mixed-signal processing side-chain that employs a non-invasive physical magnetic attack detection algorithm. The side-chain either validates, or replaces with a best estimate, the susceptible signal partition, depending upon the absence or presence of attack, respectively. The structure finally recombines the scrutinized susceptible signal partition with the insusceptible signal partition. The result is an analog magnetic flux sensor signal that is robust against skillful, surreptitious, spoofing attacks. If unmitigated, such attacks may induce catastrophic consequences into systems relying upon the magnetic flux sensor.

Abstract: There may be provided a radiation sensing device that includes a first TMOS with temperature dependent electrical parameters; wherein the first TMOS is exposed to radiation, and a second TMOS transistor that is sheltered from radiation. The radiation sensing device performs a differential measurement, and applied various measures for noise reduction, and maintaining the stability of the radiation sensing device.

Abstract: Provided is a comparison circuit to which a negative voltage to be compared can be input directly. The comparison circuit includes a first input terminal, a second input terminal, a first output terminal, and a differential pair. The comparison circuit compares a negative voltage and a negative reference voltage and outputs a first output voltage from the first output terminal in response to the comparison result. The negative voltage is input to the first input terminal. A positive reference voltage is input to the second input terminal. The positive reference voltage is determined so that comparison is performed. The differential pair includes a first n-channel transistor and a second n-channel transistor each having a gate and a backgate. The first input terminal is electrically connected to the backgate of the first n-channel transistor. The second input terminal is electrically connected to the gate of the second n-channel transistor.

Abstract: A circuit includes an input impedance, an operational amplifier, a voltage-adjusting circuit, a pulse-generating circuit, and a drive circuit. The input impedance is coupled to an input terminal of the operational amplifier, receives an input voltage, and outputs an input current. The operational amplifier is coupled to a first power voltage and outputs an amplified signal according to an input operating voltage and a feedback signal. The voltage-adjusting circuit adjusts the input operating voltage of the operational amplifier. The pulse-generating circuit generates a pulse width modulation signal according to the amplified signal. The drive circuit is coupled to a second power voltage and generates a driving signal according to the pulse width modulation signal. The feedback signal is correlated with the driving signal.

Abstract: A receiving circuit and an optical receiver including the receiving circuit are disclosed. The receiving circuit includes first and second input terminals, a FET, first and second TIA circuits, and a control circuit. The first and second input terminals each receive a current signal. The FET has first and second current terminals respectively connected to the first and second input terminals, and a control terminal. The first and second TIA circuits respectively are connected to the first and second current terminals, and convert the current signals to first and second voltage signals. The control circuit generates a control signal for application to the FET control terminal in accordance with a difference between the first and second voltage signals. The optical receiver includes the receiving circuit and each of first and second photodetectors for respectively supplying first and second current signals to the first and second input terminals of the receiver.

Abstract: The present disclosure provides an offset voltage correction circuit and an offset voltage correction method, including: a data obtaining module, configured to receive a data signal and a reference signal, and obtain a data indicator signal based on a comparison result of the reference signal and an offset data signal, the offset data signal being a data signal superimposed with an offset signal; a trimming enable module, configured to receive the data signal, the reference signal, the data indicator signal and an enable signal, obtain a theoretical indicator signal based on a comparison result of the data signal and the reference signal if the enable signal is of a high level, and generate an enable flag signal based on a comparison result of the theoretical indicator signal and the data indicator signal; and an offset correction module, configured to cancel the offset signal based on the enable flag signal.

Abstract: For converting analog audio signals captured by a microphone into digital audio data, the analog audio signals are first amplified in a pre-amplifier and then fed to an analog-to-digital converter (ADC). For better utilizing the dynamic range of the ADC, a DC coupled dual amplifier circuit may be used herein that automatically switches between two amplifier branches with different gain factors. To avoid switching noise, both signals must have the same DC component before the analog-to-digital conversion. To achieve this, the amplifier arrangement comprises a first amplifier branch having a higher first gain factor (G1) and providing a first output voltage (VOUT1) and a second amplifier branch having a lower second gain factor (G2) and providing a second output voltage (VOUT2). Both amplifier branches are DC coupled and receive as a common input signal an audio signal with a predetermined DC component (Vk).

Abstract: The disclosure describes soft limiting electrical signals generated by a transducer before amplification, buffering or other signal conditioning in a microphone assembly, circuits and methods therefor. The soft limiting circuit includes a first circuit portion that limits a first portion of the electrical signal with reduced distortion when the first portion of the signal exceeds a threshold. A second circuit portion of the soft limiting circuit similarly limits a second portion of the electrical signal. In this way, overloading of an amplifier is avoided without excessive distortion.

Abstract: A current source circuit can include a first amplifier circuit and a second amplifier circuit. Each of the first and second amplifier circuits can be configured to generate respective amplifier output voltages based on a corresponding input voltage and respective feedback voltage. The current source circuit can further include a cross-coupling circuit that can include a first set of resistors and a second set of resistors. The first set of resistors can be configured to establish a first cross-coupling voltage based on the first amplifier output voltage and the second set of resistors can be configured to establish a second cross-coupling voltage based on the second amplifier output voltage. The first and second amplifier circuits can be configured to maintain the first and second cross-coupling voltage at a given voltage amplitude to provide a constant current at an output node of the current source circuit.

Abstract: An analog front-end circuit for self-calibrating a comparator, the circuit comprising a comparator in a comparator measurement path; a preamplifier coupled to the comparator by a set of switches; and an amplifier coupled to the preamplifier, the preamplifier receiving a reference signal as a first input and a user-definable reference as a second input, the user-definable reference generating a user-definable value chosen to create a known condition at an output of the preamplifier, the preamplifier determines a residual value that represents a measurement error in a signal path comprising the comparator and is used to adjust the user-definable reference value to calibrate the signal path such that threshold boundaries for the comparator can be adjusted to tighten a comparator specification.

Abstract: According to an embodiment, a comparator circuit includes first and second PMOS transistors that compose a differential pair, a first switching transistor with a main current path that is connected between an input terminal and a gate of the first PMOS transistor, a voltage source that applies a reference voltage to a gate of the second PMOS transistor, and a first bias circuit that applies a first bias voltage to a control electrode of the first switching transistor.

Abstract: A power converter with ground fault protection (PCGFP) circuit includes an input stage, a first voltage converter, and an output stage. The input stage is connected to a power bus to receive an input direct current (DC) voltage. The first voltage converter converts the input DC voltage to a second voltage and switches between an open and closed state to regulate power present on the power bus. The output stage includes a second voltage converter circuit to generate an output voltage having a different voltage level from the input DC voltage. A controller controls operation of the first and second voltage converters and is also capable of detecting a ground fault on the power bus. The controller operates the first and second voltage converts in a fault isolation mode in response to detecting the ground fault such that the first and second voltage converters isolate the ground fault.

Abstract: Implementations provide a receiver circuit that includes: an alternate current (AC)-coupling network to filter an input signal, the AC-coupling network including a first RC filter connected between a first input node and a first common node and a second RC filter connected between a second input node and the first common node; a differential amplifier coupled to the AC-coupling network and configured to receive a filtered input signal from the AC-coupling network and generate an output signal, the differential amplifier including a differential pair of transistors and a common-mode measurement network coupled to source terminals of a first and a second transistors in the differential pair; and a first operational amplifier having an input coupled to output terminal of the common-mode measurement network and an output coupled to the first common node.

Abstract: A switched capacitor amplifier circuit includes an operational amplifier, a first capacitor and a second capacitor each having one end connected to a negative input terminal of the operational amplifier, a first switching circuit configured to connect the other end of the first capacitor and a signal source during a first operation, a second switching circuit configured to connect the other end of the second capacitor and the output terminal of the operational amplifier so as to connect the output terminal and the negative input terminal of the operational amplifier through the second capacitor during the second operation, and an impedance converter circuit configured to convert an output impedance of the signal source into a specified impedance, the impedance converter circuit being connected between the first switching circuit and the other end of the first capacitor.

Abstract: An amplifier circuit comprises a differential input stage configured to receive a differential input signal, wherein the differential input stage is susceptible to an offset error that includes a linear offset error portion and a nonlinear offset error portion; and an offset error correction circuit coupled to the differential input stage and configured to apply a second order error correction signal to the differential input stage to reduce the nonlinear portion of the offset error.

Abstract: A preamplifier comprises an input stage and a capacitive coupling stage. The input stage is arranged to receive a differential signal from a magnetic resistor which indicates a magnetic field sensed on a magnetic disk of a hard disk drive (HDD) when the preamplifier is powered on from an off state. The capacitive coupling stage has an input arranged to receive the differential signal from the input stage, a filter comprising a first resistor, a second resistor, a first capacitor, a second capacitor, and switches arranged in parallel with respective resistors, where the switches are closed when the preamplifier is powered on from the off state to an on state. A switch control is arranged to determine that an offset of the differential signal has settled and open the switches based on the determination.

Abstract: An apparatus comprises an amplifier circuit and a bias circuit. The bias circuit is generally configured to dynamically adjust a bias voltage reference at a bias node connected to one or more input transistors of the amplifier circuit to maintain a low baseband impedance.

Abstract: An inertial measurement unit includes a sensor and a heat preservation system. The heat preservation system includes a heat preservation body and a heat source. The sensor is positioned on the heat preservation body. The heat source is configured to generate heat. The heat preservation body is configured to transfer the heat from the heat source to the sensor to maintain a preset temperature in a space surrounding the sensor.

Abstract: An amplifier circuit with novel design is provided. The amplifier circuit includes an input stage, a resistor, an output stage, an intermediate stage and a gm circuit. The input stage is coupled to a first supply voltage, and is arranged to receive an input voltage and a feedback current. The resistor is coupled between the input voltage and the input stage. The output stage is coupled to a second supply voltage, and is arranged to provide an output voltage for driving a load. The intermediate stage is coupled between the input stage and the output stage, and includes a level shifter. The gm circuit is coupled to the input stage, and is arranged to compare the input voltage with a common mode voltage, and thereby generates a compensate current for the input stage.

Abstract: A device for determining a DC component in a zero-IF radio receiver comprises an input configured to receive a complex baseband signal; and an analyzer configured to analyze the complex baseband signal to determine a DC component in the complex baseband signal by selecting at least three samples of the complex baseband signal and determining the intersection of at least two perpendicular bisectors of at least two straight lines, each straight line running through a different pair of two of said selected samples, said intersection representing the DC component. Further, a corresponding method, a radar device and a radar method are disclosed.

Abstract: The present disclosure illustrates a demodulation circuit disposed in a wireless charging device. The demodulation circuit comprises a detection unit, a delay unit, a demodulation unit, a switch unit, an amplifier, an ADC, a control unit and a digital demodulation unit. The detection unit detects a pulse width modulation signal received by a coil, and outputs a modulation signal. The delay unit delays the modulation signal to generate a delay signal. The demodulation unit compares the modulation signal with the delay signal to generate a first demodulation signal. When the control unit detects the first demodulation signal is lower than a demodulation success rate in a time period, the control unit outputs a first switch signal to the switch unit. When the control unit detects a second demodulation signal is lower than the demodulation success rate in the time period, the control unit outputs a second switch signal to the switch unit.

Abstract: An amplifier circuit comprising: a first amplifier, comprising a voltage input terminal and a voltage output terminal; a voltage offset providing circuit, comprising a first terminal coupled to a first predetermined voltage source, a second terminal coupled to the voltage output terminal, and a third terminal, wherein a voltage at the third terminal is higher than a voltage at the second terminal by an offset voltage; and a voltage control capacitor, comprising a fourth terminal coupled to the third terminal, and a fifth terminal coupled to the voltage input terminal, wherein a capacitance value of the voltage control capacitor corresponds to a voltage difference between a voltage at the fifth terminal and a voltage at the fourth terminal. A better compensation for the amplifier circuit can be acquired since a voltage control capacitor having a capacitance value corresponding to the output voltage of the amplifier is applied.

Abstract: A voltage regulator and a power supply are provided. The voltage regulator includes an operational amplifier and an offset voltage control module. The operational amplifier includes an input terminal and an output terminal, and is configured to generate an output voltage to be output from the output terminal based on a reference voltage received from the input terminal. The offset voltage control module includes one stage of regulation branch or more stages of regulation branches connected in parallel, and is configured to control an offset voltage of the operational amplifier based on selection of the regulation branch to regulate the output voltage. Since sine each stage of regulation branch in the offset voltage control module is based on a transistor structure, as compared with the voltage dividing resistor in the related art, the transistor has lower power consumption, and thus power consumption of the voltage regulator is lowered.

Abstract: Methods and apparatus for digitally controlling a common-mode voltage of a comparator. An example comparator circuit generally includes a first comparator and a sensing circuit configured to digitally track a common-mode voltage of the first comparator. The comparator circuit may further include a first capacitive array having a common terminal coupled to a first input of the first comparator and selectively coupled to an input of the sensing circuit. The comparator circuit may further include a second capacitive array having a common terminal coupled to a second input of the first comparator and selectively coupled to the input of the sensing circuit.

Abstract: A sample hold circuit includes at least one capacitor CS and at least one complementary metal-oxide semiconductor (CMOS) switch. The CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel. A high level of a gate signal VGN of the NMOS transistor is adjusted to a voltage level VREG lower than a power supply voltage VDD of a chip on which the CMOS switch is integrated.

Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.

Abstract: A signal transmission circuit includes a primary element configured to receive differential signals which are generated from a transmission signal and contain alternating-current (AC) components, a secondary element magnetically or capacitively coupled with the primary element and configured to output AC signals containing the AC components of the differential signals, a secondary circuit including a pair of transmission lines configured to propagate the AC signals. The secondary circuit is electrically connected to the secondary element and extracts the transmission signal from the AC signals. The feedback circuit feedbacks an intermediate voltage between voltages of the pair of transmission lines such that the intermediate voltage is converged to a reference voltage. This signal transmission circuit prevents the secondary circuit from malfunctioning due to noise.

Abstract: The present disclosure is directed to a system that includes a sensor and a signal conditioner coupled to the sensor. The signal conditioner includes signal processing circuitry coupled to the sensor and offset cancellation circuitry. The offset cancellation circuitry includes a sign detector configured to output a high signal or a low signal based on a sign of an output signal from the signal processing circuitry, an integrator coupled to the sign detector, and a divider coupled to the integrator and to an input of the signal processing circuitry.

Abstract: The present disclosure describes aspects of a capacitance-to-voltage modulation circuit. In some aspects, the circuit is used in touch sensing. In some aspects, a modulation circuit comprises a first pair of switches having one switch connected between a voltage source and a capacitor, and another switch connected between ground and the input of the circuit. The circuit also includes a second pair of switches having one switch connected between the voltage source and the input of the circuit, and another switch connected between ground and the capacitor. A third pair of the circuit's switches comprise one switch connected between the capacitor and an input of an analog-to-digital converter (ADC) and another switch connected between the input of the circuit and the input of the ADC. The third pair of switches may enable charge sharing of signals modulated by the first and second pairs of switches, a result of which can be used to sense touch input based on capacitance at the input of the circuit.

Abstract: A regulator converting an input voltage into a supply voltage includes a first differential amplifier, a second differential amplifier, a pass element, and a feedback voltage divider. The first differential amplifier includes a reference voltage with a feedback voltage to generate a first output voltage and a first inverse output voltage. The second differential amplifier compares the first output voltage and the first inverse output voltage to generate a second output voltage. The pass element passes an output current from the input voltage to the supply voltage according to the second output voltage. The feedback voltage divider divides the supply voltage by a feedback factor to generate the feedback voltage.

Abstract: Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.

Abstract: A method and apparatus for adjusting the slope of insertion loss of digital step attenuator (DSA). The DSA is implemented on an integrated circuit. The DSA has two series inductances that are introduced between the input of DSA cell and a resistor in the cell, and the output of DSA cell and another resistor in the cell. In one embodiment, adjustment in the value of the series inductances is as achieved by altering the locations of the input port and the output ports. In another embodiment, adjustment in the value of the inductances is achieved by tailoring the length and width of the conductor trace used to connect the input and output ports to the series resistors. The adjustment in the values of the inductances provides a means by which the roll-off of the insertion loss as a function of frequency in the attenuation state can be controlled.

Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.

Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to compensating for integrated circuit manufacturing process variation with correlated electron switch devices.

Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.

Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.

Abstract: Comparators include (among other components) two inputs, an output, and two pairs of transistors (each connected to a different one of the inputs). Both pairs of transistors are connected to the output. Additionally, a first signal generator is connected to the first transistor in each of the pairs of transistors, and a second signal generator is connected to the second transistor in each of the pairs of transistors. The first signal generator and the second signal generator output on/off control signals that have timing patterns that are inverted relative to one another, and this causes only the first transistor or the second transistor in each of the pairs of transistors to be active at any given time. Thus, the single active transistor in the first pair of transistors and the single active transistor in the second pair of transistors amplify the difference between the two inputs, through the output.

Abstract: An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.

Abstract: A semiconductor device that can rapidly stabilize a control voltage for controlling an electric current source is provided. A semiconductor device includes a filter circuit that is provided between a control voltage generation circuit and an electric current source and removes noise of the control voltage. The filter circuit includes a first resistive element that is provided between the control voltage generation circuit and an output node that outputs the control voltage, a first capacitive element that is provided between the output node and a first voltage, a second capacitive element that is coupled between the output node and the first voltage via a first switch element. The second capacitive element is coupled between the first voltage and a second voltage when the first switch element is non-conductive. The second capacitive element is coupled with the first capacitive element through the output node when the first switch element is conductive.

Abstract: A low power 1-tap decision feedback equalizer (DFE) is disclosed. The DFE can include a plurality of AC-coupling networks, each having an input coupled to an output of a continuous time linear equalizer (CTLE) within an active stage of a receiver to receive a corresponding pair of differential signals of data, and an output coupled to a respective one of a plurality of data samplers to present a high frequency component of the corresponding pair of differential signals to the respective data sampler. The DFE can further include a plurality of transport paths, each transport path coupled to a respective AC-coupling network to receive the corresponding pair of differential signals. Each transport path can include one of the data sampler and an injection element to passively inject an offset into the high frequency component at an input of the respective data sampler.