Baseline Or Dc Offset Correction Patents (Class 327/307)
  • Patent number: 10803890
    Abstract: A preamplifier comprises an input stage and a capacitive coupling stage. The input stage is arranged to receive a differential signal from a magnetic resistor which indicates a magnetic field sensed on a magnetic disk of a hard disk drive (HDD) when the preamplifier is powered on from an off state. The capacitive coupling stage has an input arranged to receive the differential signal from the input stage, a filter comprising a first resistor, a second resistor, a first capacitor, a second capacitor, and switches arranged in parallel with respective resistors, where the switches are closed when the preamplifier is powered on from the off state to an on state. A switch control is arranged to determine that an offset of the differential signal has settled and open the switches based on the determination.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 13, 2020
    Assignee: Marvell Asia Pte., Ltd.
    Inventors: Xiaowei Huang, Ma Lin, Niviya Chacko, Sheng Ming Lai, Chee Guan Tan
  • Patent number: 10804858
    Abstract: An apparatus comprises an amplifier circuit and a bias circuit. The bias circuit is generally configured to dynamically adjust a bias voltage reference at a bias node connected to one or more input transistors of the amplifier circuit to maintain a low baseband impedance.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: October 13, 2020
    Assignee: Integrated Device Technology, Inc.
    Inventors: Samet Zihir, Himanshu Khatri, Tumay Kanar
  • Patent number: 10788508
    Abstract: An inertial measurement unit includes a sensor and a heat preservation system. The heat preservation system includes a heat preservation body and a heat source. The sensor is positioned on the heat preservation body. The heat source is configured to generate heat. The heat preservation body is configured to transfer the heat from the heat source to the sensor to maintain a preset temperature in a space surrounding the sensor.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: September 29, 2020
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventors: Guoxiu Pan, Yonggen Wang, Yun Yu, Peng Zhang
  • Patent number: 10771017
    Abstract: An amplifier circuit with novel design is provided. The amplifier circuit includes an input stage, a resistor, an output stage, an intermediate stage and a gm circuit. The input stage is coupled to a first supply voltage, and is arranged to receive an input voltage and a feedback current. The resistor is coupled between the input voltage and the input stage. The output stage is coupled to a second supply voltage, and is arranged to provide an output voltage for driving a load. The intermediate stage is coupled between the input stage and the output stage, and includes a level shifter. The gm circuit is coupled to the input stage, and is arranged to compare the input voltage with a common mode voltage, and thereby generates a compensate current for the input stage.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: September 8, 2020
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventor: Shao-Ming Sun
  • Patent number: 10763977
    Abstract: A device for determining a DC component in a zero-IF radio receiver comprises an input configured to receive a complex baseband signal; and an analyzer configured to analyze the complex baseband signal to determine a DC component in the complex baseband signal by selecting at least three samples of the complex baseband signal and determining the intersection of at least two perpendicular bisectors of at least two straight lines, each straight line running through a different pair of two of said selected samples, said intersection representing the DC component. Further, a corresponding method, a radar device and a radar method are disclosed.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: September 1, 2020
    Assignee: SONY CORPORATION
    Inventors: Rolf Noethlings, Norihito Mihota
  • Patent number: 10637455
    Abstract: The present disclosure illustrates a demodulation circuit disposed in a wireless charging device. The demodulation circuit comprises a detection unit, a delay unit, a demodulation unit, a switch unit, an amplifier, an ADC, a control unit and a digital demodulation unit. The detection unit detects a pulse width modulation signal received by a coil, and outputs a modulation signal. The delay unit delays the modulation signal to generate a delay signal. The demodulation unit compares the modulation signal with the delay signal to generate a first demodulation signal. When the control unit detects the first demodulation signal is lower than a demodulation success rate in a time period, the control unit outputs a first switch signal to the switch unit. When the control unit detects a second demodulation signal is lower than the demodulation success rate in the time period, the control unit outputs a second switch signal to the switch unit.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: April 28, 2020
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventor: Chih-Ning Chen
  • Patent number: 10601383
    Abstract: An amplifier circuit comprising: a first amplifier, comprising a voltage input terminal and a voltage output terminal; a voltage offset providing circuit, comprising a first terminal coupled to a first predetermined voltage source, a second terminal coupled to the voltage output terminal, and a third terminal, wherein a voltage at the third terminal is higher than a voltage at the second terminal by an offset voltage; and a voltage control capacitor, comprising a fourth terminal coupled to the third terminal, and a fifth terminal coupled to the voltage input terminal, wherein a capacitance value of the voltage control capacitor corresponds to a voltage difference between a voltage at the fifth terminal and a voltage at the fourth terminal. A better compensation for the amplifier circuit can be acquired since a voltage control capacitor having a capacitance value corresponding to the output voltage of the amplifier is applied.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: March 24, 2020
    Assignee: PixArt Imaging Inc.
    Inventors: Balasubramaniam Shammugasamy, Kei Tee Tiew
  • Patent number: 10599173
    Abstract: A voltage regulator and a power supply are provided. The voltage regulator includes an operational amplifier and an offset voltage control module. The operational amplifier includes an input terminal and an output terminal, and is configured to generate an output voltage to be output from the output terminal based on a reference voltage received from the input terminal. The offset voltage control module includes one stage of regulation branch or more stages of regulation branches connected in parallel, and is configured to control an offset voltage of the operational amplifier based on selection of the regulation branch to regulate the output voltage. Since sine each stage of regulation branch in the offset voltage control module is based on a transistor structure, as compared with the voltage dividing resistor in the related art, the transistor has lower power consumption, and thus power consumption of the voltage regulator is lowered.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: March 24, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Wei Du, Junjun Zhang
  • Patent number: 10594308
    Abstract: Methods and apparatus for digitally controlling a common-mode voltage of a comparator. An example comparator circuit generally includes a first comparator and a sensing circuit configured to digitally track a common-mode voltage of the first comparator. The comparator circuit may further include a first capacitive array having a common terminal coupled to a first input of the first comparator and selectively coupled to an input of the sensing circuit. The comparator circuit may further include a second capacitive array having a common terminal coupled to a second input of the first comparator and selectively coupled to the input of the sensing circuit.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 17, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Lei Sun, Ganesh Kiran, Seyed Arash Mirhaj, Dinesh Jagannath Alladi
  • Patent number: 10586605
    Abstract: A sample hold circuit includes at least one capacitor CS and at least one complementary metal-oxide semiconductor (CMOS) switch. The CMOS switch includes an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor connected in parallel. A high level of a gate signal VGN of the NMOS transistor is adjusted to a voltage level VREG lower than a power supply voltage VDD of a chip on which the CMOS switch is integrated.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 10, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Naohiro Nomura, Takatoshi Manabe
  • Patent number: 10530308
    Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shyamsunder Balasubramanian, Wenxiao Tan, Mayank Garg, Toru Tanaka
  • Patent number: 10476489
    Abstract: A signal transmission circuit includes a primary element configured to receive differential signals which are generated from a transmission signal and contain alternating-current (AC) components, a secondary element magnetically or capacitively coupled with the primary element and configured to output AC signals containing the AC components of the differential signals, a secondary circuit including a pair of transmission lines configured to propagate the AC signals. The secondary circuit is electrically connected to the secondary element and extracts the transmission signal from the AC signals. The feedback circuit feedbacks an intermediate voltage between voltages of the pair of transmission lines such that the intermediate voltage is converged to a reference voltage. This signal transmission circuit prevents the secondary circuit from malfunctioning due to noise.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: November 12, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Minoru Kumahara, Richard Visee, Gerrit Van Der Horn, Ronny Van Rooij, Pooyan Sakian Dezfuli
  • Patent number: 10473691
    Abstract: The present disclosure is directed to a system that includes a sensor and a signal conditioner coupled to the sensor. The signal conditioner includes signal processing circuitry coupled to the sensor and offset cancellation circuitry. The offset cancellation circuitry includes a sign detector configured to output a high signal or a low signal based on a sign of an output signal from the signal processing circuitry, an integrator coupled to the sign detector, and a divider coupled to the integrator and to an input of the signal processing circuitry.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 12, 2019
    Assignee: STMicroelectronics, Inc.
    Inventor: Fabio Romano
  • Patent number: 10353511
    Abstract: The present disclosure describes aspects of a capacitance-to-voltage modulation circuit. In some aspects, the circuit is used in touch sensing. In some aspects, a modulation circuit comprises a first pair of switches having one switch connected between a voltage source and a capacitor, and another switch connected between ground and the input of the circuit. The circuit also includes a second pair of switches having one switch connected between the voltage source and the input of the circuit, and another switch connected between ground and the capacitor. A third pair of the circuit's switches comprise one switch connected between the capacitor and an input of an analog-to-digital converter (ADC) and another switch connected between the input of the circuit and the input of the ADC. The third pair of switches may enable charge sharing of signals modulated by the first and second pairs of switches, a result of which can be used to sense touch input based on capacitance at the input of the circuit.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: July 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Bo-Ren Wang, Lennart Mathe, Sameer Wadhwa, Nathan Altman, Sandeep D'Souza
  • Patent number: 10326438
    Abstract: A regulator converting an input voltage into a supply voltage includes a first differential amplifier, a second differential amplifier, a pass element, and a feedback voltage divider. The first differential amplifier includes a reference voltage with a feedback voltage to generate a first output voltage and a first inverse output voltage. The second differential amplifier compares the first output voltage and the first inverse output voltage to generate a second output voltage. The pass element passes an output current from the input voltage to the supply voltage according to the second output voltage. The feedback voltage divider divides the supply voltage by a feedback factor to generate the feedback voltage.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 18, 2019
    Assignee: Delta Electronics, Inc.
    Inventors: Ting-Chieh Lin, Chang-Jing Yang
  • Patent number: 10305461
    Abstract: Disclosed is a method of comparing two or more signals which may include: for each of the two or more signals, charging to a fixed voltage a compensation capacitor associated with a sense path of the signal, discharging each of the charged capacitors to a threshold voltage of a transistor in its respective sense path and integrating a discharge current from each capacitor with the signal sensed on the respective sense path.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: May 28, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Alexander Kushnarenko, Yoram Betser
  • Patent number: 10291208
    Abstract: A method and apparatus for adjusting the slope of insertion loss of digital step attenuator (DSA). The DSA is implemented on an integrated circuit. The DSA has two series inductances that are introduced between the input of DSA cell and a resistor in the cell, and the output of DSA cell and another resistor in the cell. In one embodiment, adjustment in the value of the series inductances is as achieved by altering the locations of the input port and the output ports. In another embodiment, adjustment in the value of the inductances is achieved by tailoring the length and width of the conductor trace used to connect the input and output ports to the series resistors. The adjustment in the values of the inductances provides a means by which the roll-off of the insertion loss as a function of frequency in the attenuation state can be controlled.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: May 14, 2019
    Assignee: pSemi Corporation
    Inventors: Ravindranath D. Shrivastava, Raul Inocencio Alidio
  • Patent number: 10267831
    Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to compensating for integrated circuit manufacturing process variation with correlated electron switch devices.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 23, 2019
    Assignee: ARM Ltd.
    Inventors: Vikas Chandra, Mudit Bhargava
  • Patent number: 10270403
    Abstract: A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: April 23, 2019
    Assignee: INPHI CORPORATION
    Inventors: Rahul Shringarpure, Tom Peter Edward Broekaert, Gaurav Mahajan
  • Patent number: 10236050
    Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, George F. Paulik, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Patent number: 10224916
    Abstract: Comparators include (among other components) two inputs, an output, and two pairs of transistors (each connected to a different one of the inputs). Both pairs of transistors are connected to the output. Additionally, a first signal generator is connected to the first transistor in each of the pairs of transistors, and a second signal generator is connected to the second transistor in each of the pairs of transistors. The first signal generator and the second signal generator output on/off control signals that have timing patterns that are inverted relative to one another, and this causes only the first transistor or the second transistor in each of the pairs of transistors to be active at any given time. Thus, the single active transistor in the first pair of transistors and the single active transistor in the second pair of transistors amplify the difference between the two inputs, through the output.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Thomas G. McKay
  • Patent number: 10224089
    Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, George F. Paulik, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Patent number: 10211832
    Abstract: An example apparatus according to an embodiment of the disclosure includes first and second voltage terminals, and first, second, and third circuit nodes. A potential of the first circuit node is changed based on an input signal. A flip-flop circuit includes first and second inverters cross-coupled to each other. The first inverter is coupled between the first voltage terminal and the second circuit node. A first transistor is coupled between the second and third circuit nodes, and the first transistor has a control electrode coupled to the first circuit node. A first current control circuit is coupled between the third circuit node and the second voltage terminal, and an amount of current flowing through the first current control circuit being controlled based on a first code signal.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: February 19, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Hiroyuki Matsuno, Shuichi Tsukada
  • Patent number: 10157679
    Abstract: A semiconductor device that can rapidly stabilize a control voltage for controlling an electric current source is provided. A semiconductor device includes a filter circuit that is provided between a control voltage generation circuit and an electric current source and removes noise of the control voltage. The filter circuit includes a first resistive element that is provided between the control voltage generation circuit and an output node that outputs the control voltage, a first capacitive element that is provided between the output node and a first voltage, a second capacitive element that is coupled between the output node and the first voltage via a first switch element. The second capacitive element is coupled between the first voltage and a second voltage when the first switch element is non-conductive. The second capacitive element is coupled with the first capacitive element through the output node when the first switch element is conductive.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 18, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Masayuki Kawae, Takafumi Noguchi, Atsuo Yoneyama
  • Patent number: 10135644
    Abstract: A low power 1-tap decision feedback equalizer (DFE) is disclosed. The DFE can include a plurality of AC-coupling networks, each having an input coupled to an output of a continuous time linear equalizer (CTLE) within an active stage of a receiver to receive a corresponding pair of differential signals of data, and an output coupled to a respective one of a plurality of data samplers to present a high frequency component of the corresponding pair of differential signals to the respective data sampler. The DFE can further include a plurality of transport paths, each transport path coupled to a respective AC-coupling network to receive the corresponding pair of differential signals. Each transport path can include one of the data sampler and an injection element to passively inject an offset into the high frequency component at an input of the respective data sampler.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Todd Morgan Rasmus, Joseph Natonio
  • Patent number: 10128830
    Abstract: A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: November 13, 2018
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Rong-Bin Hu, Guang-Bing Chen, Gang-Yi Hu, Yong-Lu Wang, Zheng-Ping Zhang, Can Zhu, Rong-Ke Ye, Lei Zhang, Yu-Han Gao
  • Patent number: 10126177
    Abstract: A remote diode temperature sensing circuit for use in a burn-in system to sense a temperature of a semiconductor device under test includes a temperature sense circuit and an adapter circuit. The temperature sense circuit is configured to output temperature sense currents (Is) during a temperature sense routine. The adapter circuit is configured to drive mirrored sense currents (Ims), which mirror the temperature sense currents, through a diode of the semiconductor device that is connected to an input/output package pin, and present voltage differences across the diode responsive to the mirrored sense currents to the temperature sense circuit. The temperature sense circuit is configured to discharge a temperature output signal that is indicative of the temperature of the diode based on the voltage differences.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: November 13, 2018
    Assignee: Micro Control Company
    Inventors: Donald Robert Olson, Daniel Aaron Haapala
  • Patent number: 10084333
    Abstract: A charging method, a power adapter, a mobile terminal, and a charging system are provided. The power adapter communicates with the mobile terminal bidirectionally to obtain current state parameters of a battery of the mobile terminal, and adjust a charging parameter of the power adapter in real time based on the current state parameters of the battery.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 25, 2018
    Assignee: Guangdong Oppo Mobile Telecommunications Corp., Ltd.
    Inventors: Yuanqing Zeng, Zhihua Hu
  • Patent number: 10079698
    Abstract: Aspects of the disclosure are directed to determining an offset calibration step size of a sample latch. In accordance with one aspect, the disclosure relate to a Decision Feedback Equalizer (DFE) input section including a E sample latch to output a target signal sample; a E sample digital to analog converter coupled to the E sample latch to input a target voltage to the E sample latch; a sample latch to output a signal sample; and a voltage digital to analog converter coupled to the E sample latch and the sample latch to generate a bias voltage, wherein the bias voltage is inputted to the E sample latch and the sample latch. The DFE input section may further include a latch offset decoder to scale the bias voltage and a summing amplifier to receive an analog input waveform to the DFE input section.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: September 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Minhan Chen
  • Patent number: 10043568
    Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, George F. Paulik, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Patent number: 10037792
    Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, George F. Paulik, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann
  • Patent number: 10001515
    Abstract: A phase shift detector comprises a comparator for detecting phase information of a signal and an offset calibration circuit. In order to prevent input offset voltage of the comparator from affecting phase detection accuracy, bulk voltage is inputted to the comparator from the offset calibration circuit to adjust threshold voltage of transistor in the comparator for compensating input offset voltage of the comparator and improving accuracy of the phase shift detector.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: June 19, 2018
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Chua-Chin Wang, Deng-Shian Wang, Yu-Ting Tu
  • Patent number: 9960713
    Abstract: An impact producing actuator can vary energy to be applied to a shape memory alloy, depending on, for example, an ambient temperature. The impact producing actuator has a drive signal generation unit that generates a drive signal based on a single pulse signal generated in response to an input operation and outputs the drive signal, a switching element whose switching operation is controlled by the drive signal, and a shape memory alloy through which electric current passes for a period of time during which the switching element is turned on or off. The impact producing actuator is configured such that the period of time during which the switching element is turned on or off varies depending on the ambient temperature.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: May 1, 2018
    Assignee: SMK Corporation
    Inventors: Yuki Akita, Yoshinori Watanabe, Katsuhito Fujii, Takeshi Matsuda
  • Patent number: 9941852
    Abstract: A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 10, 2018
    Assignee: NXP USA, Inc.
    Inventor: Firas N. Abughazaleh
  • Patent number: 9941790
    Abstract: A method and an apparatus for DC-to-DC conversion are provided. The apparatus is a DC-to-DC converter including a first feedback current control circuit coupled to a first voltage output of the DC-to-DC converter. The first feedback current control circuit is configured to generate a first control current based on a voltage difference between a first reference voltage and the first voltage output of the DC-to-DC converter. The apparatus further includes a constant charge comparator coupled to the first feedback current control circuit and configured to compare an integrated error signal to a threshold to generate a comparison result, the integrated error signal comprising an integration of a first error signal over time, the first error signal based on the first control current.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: April 10, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Vijayakumar Dhanasekaran
  • Patent number: 9923601
    Abstract: A subsea data communication interface unit for enabling data communication over a subsea data transmission line is disclosed. The subsea data communication interface unit includes at least an electrical interface for providing an electrical connection to the subsea data transmission line and a transmitter adapted to generate a data signal corresponding to the data to be transmitted. To obtain stable, robust and reliable communication, it is proposed that the subsea data communication interface unit includes a first voltage amplifier connected between the transmitter and the electrical interface. The first voltage amplifier is configured to convert the data signal generated by the transmitter from a lower voltage signal to a higher voltage signal.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 20, 2018
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Karstein Kristiansen
  • Patent number: 9859878
    Abstract: A control circuit for use with a four terminal sensor, such as a glucose sensor. The Glucose sensor is a volume product and typically its manufacture will want to make it as inexpensively as possible. This may give rise to variable impedances surrounding the active cell of the sensor. Typically the sensor has first and second drive terminals and first and second measurement terminals, so as to help overcome the impedance problem. The control circuit is arranged to drive at least one of the first and second drive terminals with an excitation signal, and control the excitation signal such that a voltage difference between the first and second measurement terminals is within a target range of voltages. To allow the control circuit to work with a variety of measurement cell types the control circuit further comprises voltage level shifters for adjusting a voltage at one or both of the drive terminals, or for adjusting a voltage received from one or both of the measurement terminals.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: January 2, 2018
    Assignee: Analog Devices Global
    Inventors: Colin G. Lyden, Donal Bourke
  • Patent number: 9847842
    Abstract: An optical reception circuit includes a first photodetector, a first transimpedance amplifier, a level shift circuit, a second photodetector, a second transimpedance amplifier, a peak hold circuit, and a comparator. The first transimpedance amplifier converts a first light current from the first photodetector to a first voltage. The level shift circuit generates a signal voltage from the first voltage. The second transimpedance amplifier converts the second light current from the second photodetector to a second voltage. The peak hold circuit holds a peak voltage of the second voltage as a first threshold voltage. The comparator compares the signal voltage with the first threshold voltage.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: December 19, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hideo Nishikawa, Yuichi Niimura, Takeshi Nakasuji
  • Patent number: 9846176
    Abstract: An acceleration sensor circuit 1 of the invention includes an acceleration sensor 11 having a first capacitor C1 whose capacitance changes according to a position of a first movable electrode and a second capacitor C2 whose capacitance changes as opposed to the first capacitor according to a position of a second movable electrode moved together with the first movable electrode, a first circuit 15A for generating a sinusoidal AC signal of a predetermined frequency, a second circuit 12 for generating a signal according to the positions of the movable electrodes, and an arithmetic circuit 14 for analyzing data in which a signal generated by the second circuit 12 is encoded and outputting data of acceleration.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 19, 2017
    Assignees: AKEBONO BRAKE INDUSTRY CO., LTD., Japan Oil, Gas and Metals National Corporation
    Inventors: Takashi Kunimi, Toru Sekine
  • Patent number: 9847763
    Abstract: A switched-capacitor circuit comprising a differential operational amplifier and a feedback circuit is described. In some embodiments, the feedback circuit may be configured to provide a reference voltage that is insensitive to temperature and/or process variations. In some embodiments, the feedback circuit may be configured to mitigate the time delay associated with one or more capacitors of the switched-capacitor circuit. The switched-capacitor circuit may be controlled by a pair of control signals. During a first phase, one or more capacitors may be charged, or discharged, through an input signal. During a second phase, the electric charge of the one or more capacitors may be retained.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: December 19, 2017
    Assignee: MediaTek Inc.
    Inventor: Wen-Hua Chang
  • Patent number: 9817428
    Abstract: In a current-mode bandgap reference integrated circuit: a bandgap voltage generator is configured to generate a bandgap voltage, a zero-temperature coefficient current generator configured to generate a zero-temperature coefficient current, and a proportional to absolute temperature current generator configured to generate a proportional to absolute temperature current. The integrated circuit includes a first pair of bipolar junction transistors (BJT) comprising a first BJT and a second BJT. The integrated circuit also includes a second pair of bipolar junction transistors, comprising a third BJT and a fourth BJT. The first pair of BJTs matches the second pair of BJTs.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: November 14, 2017
    Assignee: Synaptics Incorporated
    Inventors: Kevin Fronczak, Eric Bohannon
  • Patent number: 9804205
    Abstract: A method for sensing the current in a high-electron-mobility transistor (HEMT) that compensates for changes in a drain-to-source resistance of the HEMT. The method includes receiving a sense voltage representative of the current in the HEMT, receiving a compensation signal representative of a drain-to-source voltage of the HEMT, and outputting as a compensated sense voltage a linear combination of the sense voltage and the compensation signal.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: October 31, 2017
    Assignee: Power Integrations, Inc.
    Inventors: Rajko Duvjnak, William M. Polivka
  • Patent number: 9787265
    Abstract: An apparatus of correcting an offset for a differential amplifier which compensates a direct current (DC) offset voltage in a differential analog signal amplifier using a resistive feedback structure to minimize a deviation and a method thereof are provided. The apparatus includes a differential amplifier that is configured to amplify a common DC voltage input via a first resistor and a second resistor with a predetermined amplification factor to output the amplified voltage. A controller is configured to compare voltages output from both output terminals of the differential amplifier to determine whether to generate an offset. In addition, the offset is corrected using a switching unit coupled in parallel to an input terminal of the differential amplifier in response to detecting a generated offset. The controller is also configured to adjust an asymmetric property of the input terminal of the differential amplifier to correct the generated offset.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: October 10, 2017
    Assignee: Hyundai Motor Company
    Inventor: Sang-Hyeok Yang
  • Patent number: 9780763
    Abstract: A calibration circuit including mode, bias, calibration, offset, resistance and code modules. The mode module selects operation in a first or second mode. The bias module generates, for the preamplifier, a first and second bias currents respectively while in first and second modes. The calibration module, during calibration of first mode, connects inputs of preamplifier together to receive a predetermined voltage. The offset module determines an offset based on output voltages of preamplifier or output voltage of comparator and generates a control signal based on whether the offset is within a predetermined range. The resistance module, based on control signal and during calibration of first mode, adjusts a resistance of a resistor in a first resistance set of preamplifier for the first mode. The code module generates a calibration code based on the resistance. The resistance module calculates a second resistance set for second mode based on the calibration code.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: October 3, 2017
    Assignee: Marvell International Ltd.
    Inventors: Wei Lu, Xiangzhu Xu, Ke Xiao
  • Patent number: 9742397
    Abstract: An apparatus includes a first field effect transistor (FET) that has a body and is coupled in a circuit. The apparatus also includes a second FET that has a body and is coupled in the circuit. The circuit has an offset because of a mismatch. The apparatus further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 22, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Gang Yuan, Shouli Yan, Matthew Powell
  • Patent number: 9729109
    Abstract: Aspects of this disclosure relate to an amplifier with at least two chopper amplifier channels in parallel between a shared input and differential nodes. The amplifier can multiplex outputs of the chopper amplifier channels to provide the output of one or more chopper amplifier channels to the differential nodes at a time. In certain embodiments, this can mask dynamic settling errors.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: August 8, 2017
    Assignee: Analog Devices, Inc.
    Inventors: Marvin L. Shu, Arthur J. Kalb
  • Patent number: 9716470
    Abstract: Provided herein are apparatus and methods for compensating an operational amplifier (op-amp). In certain configurations, a compensation network is electrically connected between an output node of the op-amp and an input differential pair coupled source/emitter tail-current node. The compensation network can include a capacitor having a relatively low value of capacitance. In this manner, op-amp bandwidth is improved while power consumption is reduced to meet a “green” standard.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: July 25, 2017
    Assignee: Analog Devices, Inc.
    Inventor: Abhishek Bandyopadhyay
  • Patent number: 9712126
    Abstract: Automatically calibrating operational amplifier (op-amp) systems for mitigating effects of offset voltages are disclosed. In one aspect, an automatically calibrating op-amp system is provided that employs an analog calibration signal corresponding to a calibration mode to compensate an output voltage signal of an op-amp corresponding to an amplify mode. An automatic calibration circuit is included that employs a successive approximation register (SAR) controller configured to successively generate digital values based on the output voltage signal of the op-amp in response to a mode signal indicating the calibration mode. The automatic calibration circuit includes a digital-to-analog converter (DAC) configured to convert each successive digital value into the analog calibration signal in response to the mode signal indicating the calibration mode. The analog calibration signal is provided to an auxiliary differential input of the op-amp to compensate for the composite offset voltage in the amplify mode.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: July 18, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Burt Lee Price, Yeshwant Nagaraj Kolla, Dhaval Rajeshbhai Shah, Ajay Janardanan
  • Patent number: 9680430
    Abstract: A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: June 13, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Mohammad Hekmat, Amir Amirkhany
  • Patent number: 9674009
    Abstract: An on-chip AC coupled receiver with offset calibration. The receiver includes AC coupling circuitry to couple a differential input signal into a coupled differential signal having a first signal and a second signal. The receiver includes a first comparator to generate a first error signal indicative of whether a first reference signal is greater or smaller than a signal derived from the coupled differential signal. The receiver includes a second comparator to generate a second error signal indicative of whether a second reference signal is greater or smaller than the signal derived from the coupled differential signal. The receiver further includes feedback circuitry to adjust a voltage offset between the first signal and the second signal of the coupled differential signal based on the first error signal and the second error signal.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: June 6, 2017
    Assignee: Rambus Inc.
    Inventor: Yikui Jen Dong