Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.

Abstract: Optimizing data approximation analysis using low power circuitry including receiving a first set of data results and a second set of data results; charging a first capacitor on the circuit with a unit of charge for each of the first set of data results that indicates a positive data point; charging a second capacitor on the circuit with the unit of charge for each of the second set of data results that indicates a positive data point; applying a voltage from the first capacitor and a voltage from the second capacitor to a FET on the circuit, wherein a current flows through the FET toward an output of the circuit if the voltage on the first capacitor is greater than the voltage on the second capacitor and a difference in the voltage of the first capacitor and the second capacitor is greater than a threshold voltage of the FET.

Abstract: A phase shift detector comprises a comparator for detecting phase information of a signal and an offset calibration circuit. In order to prevent input offset voltage of the comparator from affecting phase detection accuracy, bulk voltage is inputted to the comparator from the offset calibration circuit to adjust threshold voltage of transistor in the comparator for compensating input offset voltage of the comparator and improving accuracy of the phase shift detector.

Abstract: An impact producing actuator can vary energy to be applied to a shape memory alloy, depending on, for example, an ambient temperature. The impact producing actuator has a drive signal generation unit that generates a drive signal based on a single pulse signal generated in response to an input operation and outputs the drive signal, a switching element whose switching operation is controlled by the drive signal, and a shape memory alloy through which electric current passes for a period of time during which the switching element is turned on or off. The impact producing actuator is configured such that the period of time during which the switching element is turned on or off varies depending on the ambient temperature.

Abstract: A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset.

Abstract: A method and an apparatus for DC-to-DC conversion are provided. The apparatus is a DC-to-DC converter including a first feedback current control circuit coupled to a first voltage output of the DC-to-DC converter. The first feedback current control circuit is configured to generate a first control current based on a voltage difference between a first reference voltage and the first voltage output of the DC-to-DC converter. The apparatus further includes a constant charge comparator coupled to the first feedback current control circuit and configured to compare an integrated error signal to a threshold to generate a comparison result, the integrated error signal comprising an integration of a first error signal over time, the first error signal based on the first control current.

Abstract: A subsea data communication interface unit for enabling data communication over a subsea data transmission line is disclosed. The subsea data communication interface unit includes at least an electrical interface for providing an electrical connection to the subsea data transmission line and a transmitter adapted to generate a data signal corresponding to the data to be transmitted. To obtain stable, robust and reliable communication, it is proposed that the subsea data communication interface unit includes a first voltage amplifier connected between the transmitter and the electrical interface. The first voltage amplifier is configured to convert the data signal generated by the transmitter from a lower voltage signal to a higher voltage signal.

Abstract: A control circuit for use with a four terminal sensor, such as a glucose sensor. The Glucose sensor is a volume product and typically its manufacture will want to make it as inexpensively as possible. This may give rise to variable impedances surrounding the active cell of the sensor. Typically the sensor has first and second drive terminals and first and second measurement terminals, so as to help overcome the impedance problem. The control circuit is arranged to drive at least one of the first and second drive terminals with an excitation signal, and control the excitation signal such that a voltage difference between the first and second measurement terminals is within a target range of voltages. To allow the control circuit to work with a variety of measurement cell types the control circuit further comprises voltage level shifters for adjusting a voltage at one or both of the drive terminals, or for adjusting a voltage received from one or both of the measurement terminals.

Abstract: A switched-capacitor circuit comprising a differential operational amplifier and a feedback circuit is described. In some embodiments, the feedback circuit may be configured to provide a reference voltage that is insensitive to temperature and/or process variations. In some embodiments, the feedback circuit may be configured to mitigate the time delay associated with one or more capacitors of the switched-capacitor circuit. The switched-capacitor circuit may be controlled by a pair of control signals. During a first phase, one or more capacitors may be charged, or discharged, through an input signal. During a second phase, the electric charge of the one or more capacitors may be retained.

Abstract: An optical reception circuit includes a first photodetector, a first transimpedance amplifier, a level shift circuit, a second photodetector, a second transimpedance amplifier, a peak hold circuit, and a comparator. The first transimpedance amplifier converts a first light current from the first photodetector to a first voltage. The level shift circuit generates a signal voltage from the first voltage. The second transimpedance amplifier converts the second light current from the second photodetector to a second voltage. The peak hold circuit holds a peak voltage of the second voltage as a first threshold voltage. The comparator compares the signal voltage with the first threshold voltage.

Abstract: An acceleration sensor circuit 1 of the invention includes an acceleration sensor 11 having a first capacitor C1 whose capacitance changes according to a position of a first movable electrode and a second capacitor C2 whose capacitance changes as opposed to the first capacitor according to a position of a second movable electrode moved together with the first movable electrode, a first circuit 15A for generating a sinusoidal AC signal of a predetermined frequency, a second circuit 12 for generating a signal according to the positions of the movable electrodes, and an arithmetic circuit 14 for analyzing data in which a signal generated by the second circuit 12 is encoded and outputting data of acceleration.

Abstract: In a current-mode bandgap reference integrated circuit: a bandgap voltage generator is configured to generate a bandgap voltage, a zero-temperature coefficient current generator configured to generate a zero-temperature coefficient current, and a proportional to absolute temperature current generator configured to generate a proportional to absolute temperature current. The integrated circuit includes a first pair of bipolar junction transistors (BJT) comprising a first BJT and a second BJT. The integrated circuit also includes a second pair of bipolar junction transistors, comprising a third BJT and a fourth BJT. The first pair of BJTs matches the second pair of BJTs.

Abstract: A method for sensing the current in a high-electron-mobility transistor (HEMT) that compensates for changes in a drain-to-source resistance of the HEMT. The method includes receiving a sense voltage representative of the current in the HEMT, receiving a compensation signal representative of a drain-to-source voltage of the HEMT, and outputting as a compensated sense voltage a linear combination of the sense voltage and the compensation signal.

Abstract: An apparatus of correcting an offset for a differential amplifier which compensates a direct current (DC) offset voltage in a differential analog signal amplifier using a resistive feedback structure to minimize a deviation and a method thereof are provided. The apparatus includes a differential amplifier that is configured to amplify a common DC voltage input via a first resistor and a second resistor with a predetermined amplification factor to output the amplified voltage. A controller is configured to compare voltages output from both output terminals of the differential amplifier to determine whether to generate an offset. In addition, the offset is corrected using a switching unit coupled in parallel to an input terminal of the differential amplifier in response to detecting a generated offset. The controller is also configured to adjust an asymmetric property of the input terminal of the differential amplifier to correct the generated offset.

Abstract: A calibration circuit including mode, bias, calibration, offset, resistance and code modules. The mode module selects operation in a first or second mode. The bias module generates, for the preamplifier, a first and second bias currents respectively while in first and second modes. The calibration module, during calibration of first mode, connects inputs of preamplifier together to receive a predetermined voltage. The offset module determines an offset based on output voltages of preamplifier or output voltage of comparator and generates a control signal based on whether the offset is within a predetermined range. The resistance module, based on control signal and during calibration of first mode, adjusts a resistance of a resistor in a first resistance set of preamplifier for the first mode. The code module generates a calibration code based on the resistance. The resistance module calculates a second resistance set for second mode based on the calibration code.

Abstract: An apparatus includes a first field effect transistor (FET) that has a body and is coupled in a circuit. The apparatus also includes a second FET that has a body and is coupled in the circuit. The circuit has an offset because of a mismatch. The apparatus further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.

Abstract: Aspects of this disclosure relate to an amplifier with at least two chopper amplifier channels in parallel between a shared input and differential nodes. The amplifier can multiplex outputs of the chopper amplifier channels to provide the output of one or more chopper amplifier channels to the differential nodes at a time. In certain embodiments, this can mask dynamic settling errors.

Abstract: Provided herein are apparatus and methods for compensating an operational amplifier (op-amp). In certain configurations, a compensation network is electrically connected between an output node of the op-amp and an input differential pair coupled source/emitter tail-current node. The compensation network can include a capacitor having a relatively low value of capacitance. In this manner, op-amp bandwidth is improved while power consumption is reduced to meet a “green” standard.

Abstract: Automatically calibrating operational amplifier (op-amp) systems for mitigating effects of offset voltages are disclosed. In one aspect, an automatically calibrating op-amp system is provided that employs an analog calibration signal corresponding to a calibration mode to compensate an output voltage signal of an op-amp corresponding to an amplify mode. An automatic calibration circuit is included that employs a successive approximation register (SAR) controller configured to successively generate digital values based on the output voltage signal of the op-amp in response to a mode signal indicating the calibration mode. The automatic calibration circuit includes a digital-to-analog converter (DAC) configured to convert each successive digital value into the analog calibration signal in response to the mode signal indicating the calibration mode. The analog calibration signal is provided to an auxiliary differential input of the op-amp to compensate for the composite offset voltage in the amplify mode.

Abstract: A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator.

Abstract: An on-chip AC coupled receiver with offset calibration. The receiver includes AC coupling circuitry to couple a differential input signal into a coupled differential signal having a first signal and a second signal. The receiver includes a first comparator to generate a first error signal indicative of whether a first reference signal is greater or smaller than a signal derived from the coupled differential signal. The receiver includes a second comparator to generate a second error signal indicative of whether a second reference signal is greater or smaller than the signal derived from the coupled differential signal. The receiver further includes feedback circuitry to adjust a voltage offset between the first signal and the second signal of the coupled differential signal based on the first error signal and the second error signal.

Abstract: An electric capacity measurement apparatus with temperature compensation and a temperature compensation method thereof are provided. The electric capacity measurement apparatus includes an electric capacity measurement circuit, a non-volatile memory, a temperature measurement circuit and a control circuit. The electric capacity measurement circuit is configured to obtain an input current signal and compensate the input current signal according to a present invalid current range or a present zero current offset to obtain an electric capacity signal. The non-volatile memory is configured to store a plurality of test parameters at different temperatures related to the electric capacity measurement circuit in a test stage. The temperature measurement circuit measures a present temperature value of the electric capacity measurement circuit in an operation stage.

Abstract: A burst-signal reception circuit that receives a differential signal of a burst signal input via a preamplifier. The burst-signal reception circuit includes a differential amplifier to which the differential signal is input via capacitors, an average detection circuit that detects an average of a differential input signal to the differential amplifier, and a differential-offset cancel circuit that operates to cancel a DC voltage level difference of the differential input signal on the basis of output signals of the average detection circuit. Average detection speed of the average detection circuit is configured to be switched according to presence or absence of burst signal reception. The average detection speed is switched to a high-speed side in a head portion of the burst signal and switched to a low-speed side in portions other than the head portion.

Abstract: An output buffer with an offset cancellation structure for an LCD source driver includes an operational amplifier, for driving an output signal of the output buffer according to a data signal from a data input terminal of the output buffer; a reference voltage generator, for generating a reference voltage and inputting the reference voltage to the operational amplifier; and a sampling capacitor, coupled between a second input terminal of the operational amplifier and the data input terminal of the output buffer in a first phase, and coupled between the second input terminal of the operational amplifier and an output terminal of the operational amplifier in a second phase, wherein the second input terminal of the operational amplifier is further coupled to the output terminal of the operational amplifier in the first phase. The output signal outputs the data signal where the offset voltage is cancelled in the second phase.

Abstract: A state wherein offset voltage is reduced can be maintained regardless of environmental fluctuation. A differential amplification unit has differential pair transistors, and amplifies a difference between input voltages. An offset voltage measurement unit samples offset voltage generated due to an imbalance in the current drive capacities of the differential pair transistors in a first mode, and determines the polarity of the sampled offset voltage in a second mode. A control unit switches the operating mode between the first mode and second mode, and outputs a control signal for correcting the offset voltage in accordance with the polarity determination result when in the second mode. An offset voltage correction unit corrects the offset voltage based on the control signal.

Abstract: An apparatus comprising a digital signal processor (DSP) unit configured to perform fiber dispersion pre-compensation on a digital signal sequence based on a dispersion value to produce a pre-compensated signal, wherein the dispersion value is associated with a remote optical receiver, a plurality of digital-to-analog converters (DACs) coupled to the DSP unit and configured to convert the pre-compensated signal into analog electrical signals, and a frontend coupled to the DACs and configured to convert the analog electrical signals into a first optical signal, adding a constant optical electric (E)-field to the first optical signal to produce a second optical signal, and transmit the second optical signal to the remote optical receiver.

Abstract: An A/D converter includes: an input buffer; N sub-A/D converters including N first sampling circuits that are connected to the input buffer, and that sample the output analog signal in respective sampling slots; a control circuit that executes calibration for the N first sampling circuits one by one; a reference A/D converter including a second sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and a third sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N?1) first sampling circuits out of the execution of the calibration.

Abstract: A control circuit for a switched-mode power supply having an input side (101) connectable to an electrical power source and an output side (102) connectable to a load.

Abstract: The present invention provides a boosting system, a diagnosing method and a diagnosing program, that may diagnose a boosting section while suppressing consumption of electric power and current, and without being carrying out by a CPU. Namely, during an initializing operation, difference between power supply voltage and own threshold voltage charges capacitor C1 of a comparison circuit, and a difference between voltage of a constant voltage and the own threshold voltage charges capacitor C2. In a comparing operation, a boosting section and the capacitor C1 are connected so that boosted voltage is inputted, and GND and the capacitor C2 are connected so that GND voltage is inputted. At this time, if output OUT is L level, it is diagnosed that there is no defect, whereas if the output OUT is H level, it is diagnosed that there is defect.

Abstract: A sigma delta receiver achieves increased stability and noise reduction. The sigma delta receiver includes a first integrator stage, an isolation stage, a second integrator stage, and a quantization stage. The first integrator stage receives an analog radio frequency (RF) signal from an antenna and generates an analog baseband signal based on the analog RF signal. The isolation stage is coupled to an output of the first integrator stage. The isolation stage receives the analog baseband signal from the first integrator stage and amplifies the analog baseband signal. The second integrator stage is coupled to an output of the isolation stage to receive the analog baseband signal. The second integrator stage further amplifies the analog baseband signal. The quantization stage converts the analog baseband signal to a digital signal, and outputs the digital signal.

Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

Abstract: An on-chip AC coupled receiver with baseline wander compensation. The receiver may be used for either single ended or differential signals. The receiver includes an input terminal to receive an input signal. AC coupling circuitry is between the input terminal and a node and couples the input signal into a coupled signal at the node. A control loop senses low frequency signal content at the node and uses a linear buffer in adjusting the coupled signal at the node based on the low frequency signal content. The operation of the control loop compensates for potential baseline wander in the coupled signal. An input stage to recovers data from the coupled signal at the node.

Abstract: A device and method for solving problems of the prior art in which channel information as well as a DC offset is removed when removing the DC offset using a feedback signal of a baseband amplifier is provided. The device includes a DC offset correcting unit for removing the DC offset using an HPF function and controlling a feedback path according to a control signal to stop the HPF function and a signal generator for generating the control signal for controlling the HPF function, wherein the control signal is a signal for controlling formation and cutting-off of the feedback path.

Abstract: Circuits and methods are provided for compensating an offset voltage measured between a first transistor and a second transistor of a sense amplifier circuit that is configured to sense a bit line signal during a sensing phase. The first transistor and the second transistor are cross-coupled. The first transistor is coupled to a first capacitor and the second transistor is coupled to a second capacitor. The first capacitor is further coupled to the second capacitor, and the first and second capacitors are coupled to a third transistor. The first capacitor applies a first bias voltage to the first transistor during a pre-sensing phase prior to the sensing phase, and the second capacitor applies a second bias voltage to the second transistor during the pre-sensing phase.

Abstract: An auto-zero circuit of an operational amplifier is disclosed, and the auto-zero circuit has: a micro-control unit and a digital potentiometer; the micro-control unit is used to obtain a voltage value of an offset voltage of the output end when there is no input in the operational amplifier, and generates a control signal which causes the voltage value of the offset voltage to be smaller than a first threshold value according to the voltage value of the offset voltage; the digital potentiometer is used to adjust a resistance thereof according to the control signal.

Abstract: A DC offset cancellation circuit is provided. A first DC current and a first sensing current are superposed with each other to generate a first superposed current. A second DC current and a second sensing current are superposed with each other to generate a second superposed current. The first superposed current is converted into a first voltage signal. The second superposed current is converted into a second voltage signal. After the first voltage signal and the second voltage signal are received by a differential amplifier, an output signal is generated. The output signal is processed into a DC value. The DC value is converted into a DC current signal. The superposing unit generates the first DC current and the second DC current according to the DC current signal, so that the first superposed current and the second superposed current have the same DC offset.

Abstract: An analog-to-digital converter (ADC) that comprises a first ADC stage and a second ADC stage. The first ADC stage comprises a successive approximation register (SAR). The first ADC is configured to convert an analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a digital output signal. The first ADC stage is also configured to generate a residual voltage corresponding to a difference between a voltage value of the analog input signal and the first digital signal. The second ADC stage comprises a plurality of time-to-digital converter (TDC) cells coupled in series. The second ADC is configured to convert the residual voltage into a plurality of second digital signals generated by the TDC cells. The second digital signals correspond to a least-significant-bits (LSB) portion of the digital output signal. The digital output signal is a digital representation of the analog input signal.

Abstract: A method for efficiently encoding and compressing ECG data optimized for use in an ambulatory electrocardiography monitor is provided. ECG data is first encoded and compressed in a lossy process and further encoded and compressed in a lossless process. A compression ratio significantly higher than other Holter-type monitors is achieved. Requirements for storage space and power cell consumption are reduced, contributing to the long-term availability of the monitor.

Abstract: A circuit that regulates electrical current flow through an integrated circuit involves a sequencing circuit connected to a clock signal generator, the sequencing circuit configured to, responsive to receiving a clock signal from the clock signal generator, generate a set of sequencing signals that includes a first switching signal, a second switching signal, and a disable signal. The circuit also involves a switching circuit connected to the sequencing circuit, the switching circuit configured to receive the first switching signal and the second switching signal and a current mirror connected to the switching circuit and the sequencing circuit, the current mirror configured to receive an activation signal from a current control logic circuit and to receive the disable signal.

Abstract: Aspects of this disclosure relate to compensating for a relatively large offset in a signal generated by a sensor, such as a pressure sensor and/or a resistive bridge based sensor. Such offset compensation can include applying an offset correction signal generated by a configurable voltage reference, such as a voltage mode digital-to-analog converter (DAC), to an input of an amplifier included in an instrumentation amplifier to compensate for the offset of the signal generated by the sensor.

Abstract: According to one embodiment, an AD conversion circuit of a pipeline type or successive-approximation type which compares an input voltage and a reference voltage to perform AD conversion is provided which comprises a reference voltage generating unit that generates the reference voltage. The reference voltage generating unit changes the reference voltage according to an analog-gain specifying value for setting a gain of an output value against the input voltage.

Abstract: A clock generator includes a diagnostic circuit that includes first and second muxes, first and second comparators, a logic gate, and a counter. The first mux receives first and second voltage signals and outputs a first intermediate signal based on a control signal. The second mux receives third and fourth voltage signals and outputs a second intermediate signal based on the control signal. The first and second comparators compare the intermediate signals with a first signal that is indicative of a DC value of the clock signal for generating first and second comparison signals. The logic gate receives the first and second intermediate signals and generates a control signal. The counter receives the clock signal and the control signal and generates a clock ready signal that is indicative of stability and quality of the clock signal.

Abstract: Provided is a photoelectric sensor that detects a workpiece by measuring light transmission time. A photoelectric sensor includes: a light emitting element which repeatedly generates detection light; a light receiving element which receives reflected light of the detection light; a binarization processing section which binarizes a light receiving signal; a waveform detection section which detects waveform data indicating a temporal change of the binarized light receiving signal; a waveform integration section which matches light emitting timing of the light receiving element to integrate two or more pieces of waveform data and generates integrated waveform data; and a workpiece discrimination section which discriminates presence or absence of a workpiece based on the integrated waveform data, whereby the reflected light is sampled at a high speed while a circuit scale is suppressed, to detect the workpiece.

Abstract: In one embodiment, ECG data collected during the long-term monitoring are compressed through a two-step compression algorithm executed by an electrocardiography monitor. Minimum amplitude signals may become indistinguishable from noise if overly inclusive encoding is employed in which voltage ranges are set too wide. The resulting ECG signal will appear “choppy” and uneven with an abrupt slope. The encoding used in the first stage of compression can be dynamically rescaled on-the-fly when the granularity of the encoding is too coarse. In a further embodiment, offloaded ECG signals are automatically gained as appropriate on a recording-by-recording basis to preserve the amplitude relationship between the signals. Raw decompressed ECG signals are filtered for noise content and any gaps in the signals are bridged. The signal is then gained based on a statistical evaluation of peak-to-peak voltage (or other indicator) to land as many ECG waveforms within a desired range of display.

Abstract: A circuit may include a photodiode configured to receive an optical signal and convert the optical signal to a current signal. The circuit may also include a transimpedance amplifier coupled to the photodiode and configured to convert the current signal to a voltage signal. The circuit may also include an equalizer coupled to the transimpedance amplifier and configured to equalize the voltage signal to at least partially compensate for a loss of a high frequency component of the optical signal. The equalizer and the transimpedance amplifier may be housed within a single integrated circuit.

Abstract: Techniques for determining the spectral content of a data bus are described herein. An example of a device in accordance with the present techniques includes a data bus comprising one or more signal lines, a first phasor generator, and a second phasor generator. The first phasor generator obtains a first data value based on the data to be transmitted over the data bus and generates a first phasor. The second phasor generator obtains a second data value based on the data to be transmitted over the data bus and generates a second phasor. The sum of the first phasor and the second phasor indicate, at least in part, the spectral content of the data to be transmitted over the data bus.

Abstract: A spectrum analyzer that provides from below 9 kHz to above 20 GHz operation range while remaining hand-held. The spectrum analyzer includes an integrated precision stand-alone step attenuator that does not rely on printed circuit board (PCB) mounted circuit elements within the signal path. Further, a PIN diplexing switch separates signals into different base-band and highband paths. The baseband path includes a pre-amplifier for low frequency signals, while the higher frequency bands may not necessarily include a pre-amplifier. The highband path incorporates multi-throw MMIC PIN diode switches to selectively filter different bands of input signals.

Abstract: A radar sensor for motor vehicles includes: a transmit and receive component, which includes a mixer for mixing a transmitted signal with a received signal; an evaluation circuit which is connected to an output of the mixer by a direct voltage coupling device; and a compensation device for compensating a DC offset in the output signal of the mixer, the compensation device being subdivided into a rough compensation device in the transmit and receive component, and a fine compensation device in the evaluation circuit.

Abstract: The fully integrated DC offset compensation servo feedback loop is an integrator that measures the output signal DC component, and then feeds back and subtracts the measured DC component from the input signal. A larger integrator time constant lowers the high pass corner frequency, which must be very small in order to minimize the loss of the low frequency component of the desired signals. The large time constant is achieved on an integrated circuit by the use of a class-AB fully differential opamp in conjunction with an R-2R ladder as a circuit element to accomplish an integrated large time constant integrator. The R-2R ladder is configured as a digitally programmable resistor.

Abstract: A digital-to-analog conversion system includes a digital-to-analog converter and an output stage for converting an output signal of the digital-to-analog converter into a voltage range. The output stage includes a first amplifier including a first input for receiving the output signal of the digital-to-analog converter, a first resistance element coupled between a second input and an output of the first amplifier, a second resistance element coupled between the second input of the first amplifier and a ground reference, and a third resistance element switchably coupled from the second input of the first amplifier to an offset voltage.