Distortion Compensation Patents (Class 327/317)
  • Patent number: 11031914
    Abstract: A diode linearizer according to the present invention has parallelly mounting linearizer core units on a RF signal path via capacitors between the RF signal path and a ground, thus does not need a switch using an FET, for example, at a time of selectively operating a plurality of linearizer core units. Moreover, the diode linearizer does not need a capacitor in series for blocking a direct current between RF signal input and output terminals. Thus, a range of a gain which can be compensated by the diode linearizer can be increased. Furthermore, an insertion loss of the RF signal path in a state where the diode linearizer is off can be reduced, and a range of a gain expansion in operation can be increased. The switch is not used, or the number of elements of the capacitors which are needed is small, thus a circuit size is also small.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: June 8, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ko Kanaya, Kazuya Yamamoto
  • Patent number: 10985965
    Abstract: A power amplifier system includes an input operable to receive an original value that reflects information to be communicated and an address data former operable to generate a digital lookup table key. The power amplifier system also includes a predistortion lookup table coupled to the address data former and a power amplifier having an output and coupled to the predistortion lookup table. The power amplifier system further includes a feedback loop providing a signal associated with the output of the power amplifier to the predistortion lookup table and a switch disposed in the feedback loop and operable to disconnect the predistortion lookup table from the output of the power amplifier.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 20, 2021
    Assignee: DALI WIRELESS, INC.
    Inventors: Dali Yang, Jia Yang
  • Patent number: 10943615
    Abstract: Methods and systems are disclosed for controlling fly-height of a read/write (RW) head. In an embodiment, a RW channel detects a servo gate signal and toggles a mode signal within a preamplifier from a RW data mode signal to a fly-height control (FHC) mode signal. In response to the FHC mode signal, the RW channel transmits FHC data over a differential interface to the preamplifier.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: March 9, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Takahiro Inoue, Shinichiro Kuno, Takao Sugawara
  • Patent number: 10825898
    Abstract: The semiconductor layout structure includes an active region surrounded by an isolation structure, at least one first gate structure disposed over the active region and the isolation structure, at least one second gate structure disposed over the active region and the isolation structure, and a plurality of source/drain regions disposed in the active region. The active region includes two first regions, a second region disposed between the two first regions, a third region disposed between one of the first region and the second region, and a fourth region disposed between the other first region and the second region.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 3, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Jhen-Yu Tsai, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10791015
    Abstract: A wireless communication apparatus includes amplifiers, peak component suppression units respectively corresponding to the amplifiers and configured to suppress, down to a first threshold, a peak level of a composite signal in which transmission signals to be transmitted to a plurality of terminals are superimposed, a detection unit configured to detect transmission power of the composite signal input to each of the peak component suppression units, and a control unit configured to perform at least one of control of the first threshold of each peak component suppression unit and a saturation point of an amplifier corresponding to each peak component suppression unit and control of the transmission power of the composite signal in accordance with the transmission power detected by the detection unit.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: September 29, 2020
    Assignee: NEC CORPORATION
    Inventor: Takuji Mochizuki
  • Patent number: 10277172
    Abstract: A system has a plurality of non-linear circuit stages and an intervening linear circuit stage. An input signal is provided to a first non-linear circuit stage, and from the first non-linear circuit stage, to the linear circuit stage. The first non-linear circuit stage applies a second-order distortion to the input signal and provides the resulting signal to the linear circuit stage. The resulting signal that is output from the linear circuit stage is inverted with respect to the input signal and suitably linearly processed (attenuated or amplified). This signal is then provided to a second non-linear circuit that applies a second-order distortion and outputs a signal that has an overall reduction in second-order distortion.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: April 30, 2019
    Assignee: Zinwave, LTD
    Inventors: John Prentice, Alessandro Bertoneri, Chris Potter
  • Patent number: 10234499
    Abstract: Techniques and test structures for determining reliability and performance characteristics of an integrated circuit (IC) device are disclosed. For example, an IC device includes multiple functional elements and multiple test elements. The test elements are electrically coupled in series between a first test port and a second test port. A method of testing the IC device includes applying an electrical stimulus between the first test port and the second test port, measuring a parametric value in response to the electrical stimulus, comparing the parametric value and a statistical value, and determining a pass or fail status of the IC device. The statistical value is representative of a predicted reliability of the IC device.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 19, 2019
    Assignee: Keysight Technologies, Inc.
    Inventors: Martin W. Dvorak, Ben Keppeler
  • Patent number: 9899978
    Abstract: This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (?) from the output signal and the input signal. In various embodiments the extent to which the error signal (?) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203).
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: February 20, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: John Paul Lesso, Toru Ido
  • Patent number: 9876471
    Abstract: Apparatus and methods for phase compensation in power amplifiers are disclosed herein. In certain implementations, a method of phase compensation in a power amplifier includes amplifying a radio frequency signal using a power amplifier that includes an input stage and an output stage, powering a bipolar transistor of the output stage using a power amplifier supply voltage, changing a voltage level of the power amplifier supply voltage, the bipolar transistor having an input reactance that changes in response to the change in the voltage level of the power amplifier supply voltage, and compensating for a variation in a phase delay of the power amplifier arising from the change in the input reactance of the bipolar transistor using a compensation circuit that is electrically connected to an output of the input stage.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: January 23, 2018
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hardik Bhupendra Modi, Sabah Khesbak, Guohao Zhang
  • Patent number: 9754202
    Abstract: A method, system and tag for low power radio frequency communication is described. In one embodiment, the RF tag comprises: an access point coupled to provide access to a network; an RF tag comprising an energy harvesting unit operable to convert incident RF energy to direct current (DC); a storage unit operable to store recovered DC power; a passive wakeup pattern detector operable to generate an interrupt in response to detecting a set of one or more subcarriers; one or more sensors for sensing; a communication mechanism; and a microcontroller coupled to the energy harvesting and storage units, the one or more sensors, and the backscatter communicator, the microcontroller operable to wake up from a sleep state in response to the interrupt and cause the communication mechanism to exchange data wirelessly with another while powered by energy previously harvested and stored by the energy harvesting and storage unit.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: September 5, 2017
    Assignees: RICOH CO., LTD., DUKE UNIVERSITY
    Inventors: Ken Gudan, Sergey Chemishkian, Jonathan J. Hull, Matthew S. Reynolds
  • Patent number: 9747538
    Abstract: A method, system and tag for low power radio frequency communication is described. In one embodiment, the RF tag comprises: an energy harvesting unit operable to convert incident RF energy to direct current (DC); a storage unit operable to store recovered DC power; a passive wakeup pattern detector operable to generate an interrupt in response to detecting a set of one or more subcarriers; one or more sensors for sensing; a communication mechanism; and a microcontroller coupled to the energy harvesting and storage units, the one or more sensors, and the backscatter communicator, the microcontroller operable to wake up from a sleep state in response to the interrupt and cause the communication mechanism to exchange data wirelessly with another while powered by energy previously harvested and stored by the energy harvesting and storage unit.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: August 29, 2017
    Assignees: RICOH CO., LTD., DUKE UNIVERSITY
    Inventors: Ken Gudan, Sergey Chemishkian, Jonathan J. Hull, Matthew S. Reynolds
  • Patent number: 9680422
    Abstract: Exemplary embodiments are related to power amplifier power level compensation in a pre-distortion system. A method may include applying digital pre-distortion (DPD) of a power amplifier at a frequency channel, a fixed input power value, and a fixed temperature. The method may also include determining an optimal input power value for the power amplifier in response to a change in at least one of frequency and temperature.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: June 13, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Qijia Liu, Jifeng Geng, Daniel Fred Filipovic, Li Gao
  • Patent number: 9654310
    Abstract: An analog delay cell is provided that includes a transconductance-capacitance stage and an inductive transimpedance amplifier stage that provides an all-pass transfer function. In another embodiment, an adaptive analog delay cell including a transconductance (gm) plus capacitance (C) stage and an inductive-capacitance transimpedance amplifier (TIA) stage with digitally programmable phase-shift is provided. The adaptive analog delay cell increases the phase-shift by incorporating an LC network in the feedback path of the transimpedance stage. The disclosed analog delay cells can be used to provide delays in a tapped delay line. Also, the disclosed analog delay cells may be used to perform the multiplier and summation functions of a tapped delay line in addition to providing the delays. In another embodiment, the transimpedance amplifier stage includes an inductive-capacitive transimpedance amplifier stage.
    Type: Grant
    Filed: November 19, 2016
    Date of Patent: May 16, 2017
    Assignee: NXP USA, INC.
    Inventor: Yi Cheng Chang
  • Patent number: 9270246
    Abstract: Embodiments provide a limiter circuit that includes a power splitter coupled with a plurality of antiparallel diode pairs. In some embodiments, the power splitter may be part of a first stage of the limiter circuit. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 23, 2016
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Joseph J. Bouchez, Tuong Nguyen
  • Patent number: 9111561
    Abstract: A disk drive dynamic wave shaper (DWS) write driver includes a write current generator that produces a baseline output current for the write current pulses and an overshoot current generator that produces an overshoot current with different values. The overshoot current is added to the baseline current, with the value of the overshoot current amplitude (OSA) being selected in response to the frequency of transitions in the write data signal. The write driver includes logic circuitry that detects the pattern of transitions. Transitions that are immediately followed by a transition will receive a larger-than-nominal OSA1, transitions that are not immediately followed by a transition and that are not preceded by a long sequence of non-transitions will receive a nominal OSA2, and transitions after longer sequences of non-transitions will receive a smaller-than-nominal OSA3.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: August 18, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: John Contreras, Samir Y. Garzon, Weldon Mark Hanson, Rehan Ahmed Zakai
  • Patent number: 9077300
    Abstract: The predistortion circuit with concave characteristic is developed from a novel functional model for class-AB solid-state bipolar amplifiers. The model, based on a Fourier sine-series is simple and can provide closed-form expressions for the intermodulation products resulting from exciting the power amplifier by a multi-sinusoidal signal. The special case of a two-tone equal-amplitude signal is considered in detail. The present model can be used to build a database for the intermodulation performance of the class-AB bipolar SSPAs excited by a multi-sinusoidal signal. Using this database, the diode-based predistortion circuit with concave characteristic for linearizing the class-AB solid-state power amplifier is designed.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: July 7, 2015
    Assignee: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS
    Inventors: Muhammad Taher Abuelma'atti, Abdullah M. T. Abuelma'atti
  • Patent number: 9013226
    Abstract: Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region are provided. In one embodiment, a circuit includes an averaging circuit configured to average signals at a drain and a source of a MOS transistor and provide the averaged signal to a gate of the MOS transistor, and one or more current sources coupled with the gate; the circuit is configured to vary voltage at the gate so as to vary a resistance of the MOS transistor. The averaging circuit comprises a first MOS circuit coupled between the drain and the gate, a first capacitor coupled in parallel to the first MOS circuit between the drain and the gate, a second MOS circuit coupled between the source and the gate, and a second capacitor coupled in parallel to the second MOS circuit between the source and the gate.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: April 21, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Shagun Dusad, Visvesvaraya Pentakota
  • Patent number: 8963608
    Abstract: The peak-to-average power ratio of an input signal can be reduced prior to amplification. This reduction in the peak-to-average power ratio can be accomplished without adding significant intermodulation distortion to the input signal. The resulting input signal can therefore have a peak-to-average power ratio that does not exceed the output backoff of the amplifier thereby preventing the amplifier from being operated in saturation and, as a result, minimizing the intermodulation distortion added by the amplifier. The peak-to-average power ratio of an input signal can be reduced using two stages of signal clipping. By employing two stages, the intermodulation distortion introduced to the input signal as it passes through the stages is minimized. Also, because this two-stage approach does not attempt to account for intermodulation distortion introduced by the downstream amplifier, it can be implemented without any prior knowledge of the amplifier's transfer function or any output monitoring scheme.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: February 24, 2015
    Assignee: L-3 Communications Corp.
    Inventors: June Y. Sun, William K. McIntire
  • Publication number: 20140368251
    Abstract: A distortion compensation device compensates a distortion component generated in a nonlinear circuit having a nonlinear input-output characteristic. The distortion compensation device includes a predistorter and an estimator. The predistorter converts an input signal into an inverse characteristic signal by using a compensation coefficient so that an estimation value of an inverse characteristic to the nonlinear input-output characteristic is given to the input signal. The estimator generates the compensation coefficient based on the input signal, the inverse characteristic signal and an output signal of the nonlinear circuit.
    Type: Application
    Filed: March 7, 2014
    Publication date: December 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto TANAHASHI, Yoshimasa EGASHIRA, Keiichi YAMAGUCHI
  • Publication number: 20140320191
    Abstract: The even order harmonic distortion in a differential circuit is reduced or eliminated by treating the amplitude and phase mismatch sources that cause the distortion as impedance mismatches, and utilizing switched resistor circuitry that adjusts the load resistance to reduce the effects of the amplitude mismatch sources, and switched capacitor circuitry that adds shunt capacitance to reduce the effects of the phase mismatch sources.
    Type: Application
    Filed: April 30, 2013
    Publication date: October 30, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Bumha Lee, Yongseon Koh
  • Publication number: 20140301742
    Abstract: A digital signal processing method has steps of pre-emphasizing a digital signal, and then processing the pre-emphasized digital signal through a non-linear device. In the pre-emphasizing step, an undershoot is applied to a first level of the digital signal at a positive signal transition or an overshoot is applied to the digital signal at a negative first signal transition.
    Type: Application
    Filed: April 3, 2014
    Publication date: October 9, 2014
    Applicant: TYCO ELECTRONICS SVENSKA HOLDINGS AB
    Inventors: Marek Grzegorz Chacinski, Nicolae Pantazi Chitica
  • Publication number: 20140152642
    Abstract: An error compensator and an organic light emitting display device using the same. The organic light emitting display device includes pixels each having a driving transistor and an organic light emitting diode; and a sensing unit extracting at least one of a first information including the threshold voltage of the driving transistor or a second information including the degradation of the organic light emitting diode from a pixel of the pixels. In the organic light emitting display device, the sensing unit includes an amplifier amplifying a voltage corresponding to the at least one of the first information or the second information; and an error compensator compensating for error components of elements included in the amplifier and the error compensator.
    Type: Application
    Filed: July 12, 2013
    Publication date: June 5, 2014
    Inventors: Bo-Yeon Kim, Oh-Jo Kwon, Hee-Sun Ahn
  • Patent number: 8677166
    Abstract: A semiconductor device includes a power gating unit, a combinational logic unit and a clamping unit. The power gating unit is turned on to output an internal signal at an output electrode based on an input signal or turned off according to operation modes. The combinational logic unit includes an input electrode directly connected to the output electrode of the power gating unit through a data line, and generates an output signal based on the internal signal received through the data line. The clamping unit is turned on to clamp the internal signal at a logic high level or at a logic low level or turned off according to the operation modes. The semiconductor device clamps the output electrode of the power gating unit without degrading an operation speed of the semiconductor device.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heon-Hee Lee, Hoi-Jin Lee
  • Patent number: 8593085
    Abstract: The present invention relates to an electrical device for charging accumulator means (5), said electrical device comprising: a motor (6) connected to an external mains (11); an inverter (2) connected to the phases of said motor (6); and switching means (4) integrated into the inverter (2), said switching means (4) being configured to permit said motor (6) to be supplied and to permit the accumulator means (5) to be charged by the inverter (2). According to the invention, said electrical device further includes, for each phase of said motor (6), an RLC low-pass filter (18) connected, on the one hand, to the mid-point (16) of the phase of said motor (6) and, on the other hand, to ground.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: November 26, 2013
    Assignee: Valeo Systemes de Controle Moteur
    Inventors: Boris Bouchez, Luis De Sousa
  • Patent number: 8536923
    Abstract: A system and method for reducing gain error and distortion in an operational amplifier due to errors in the second or integrator stage. A correction circuit may replicate an error current and insert the current into the signal stream to preempt the induction of an error at the amplifier's input. A capacitor may sample the error voltage at the input of the integrator stage of the amplifier and generate a replica of the error current in the integration capacitor to feed it into the input of the integrator stage. This eliminates any nonlinearity errors created by error currents in the compensation or integration capacitor at the second or integrator stage of the two-stage amplifier. Feeding the error current to the integrator stage may be facilitated with a unity gain buffer and a current mirror.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: September 17, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Moshe Gerstenhaber, Sandro Herrera, Chau Cuong Tran
  • Patent number: 8427221
    Abstract: The present invention includes a solution to the adherence to and improvement of the specifications regarding the conducted susceptibility of a microwave chain. It has an advantage of enabling significant attenuation of parasitic modulated signals carried in microwave chains of microwave devices such as those that are integrated into satellites by adding one or more 180° phase shifters between the units which do not exhibit a sufficient conducted susceptibility performance. The invention consequently makes it possible to do away with certain elements charged with the attenuation of the parasitic signals generally integrated into the power supplies and other DC/DC converters present in all contemporary microwave equipment.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: April 23, 2013
    Assignee: Thales
    Inventors: Christophe Ibert, Cecile Debarge
  • Patent number: 8253471
    Abstract: This document discusses, among other things, a system and method for offsetting reverse-bias leakage of a high impedance bias network. In an example, an apparatus includes an anti-parallel diode pair coupled between a signal node and a common-mode node. The anti-parallel diode pair can include a first diode and a second diode coupled to the first diode. A third diode can be coupled between a supply node and the signal node, and the third diode can be sized to compensate for a parasitic diode junction of the anti-parallel diode pair.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: August 28, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Christopher Bennett, Hrvoje Jasa
  • Publication number: 20120119810
    Abstract: A distortion model for a predistortion system uses tap output normalization to normalize the variance of data signals generated from different basis functions in a set of basis functions to a predetermined value. The distortion model is used by a distortion modeling circuit to calculate the weighting coefficients for a digital predistorter.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 17, 2012
    Inventor: Chunlong Bai
  • Publication number: 20120119811
    Abstract: Digital predistorter circuits with selectable basis function configurations are described. In some embodiments, an input scaling block is introduced prior to a basis function generator structure. The input scaling factor is based on the input signal's average power. In other embodiments, configurable connection coefficients are used to construct the orthogonal basis functions. Multiple sets of tap weights for the predistorter are maintained, each set corresponding to a given basis function configuration. In an example method for pre-distorting an input signal to compensate for distortion introduced by an electronic device, a statistic characterizing the input signal is calculated, and one of a pre-determined set of basis function configurations is selected, based on the statistic.
    Type: Application
    Filed: November 16, 2010
    Publication date: May 17, 2012
    Inventors: Chunlong Bai, Bradley John Morris, Brian Lehman
  • Publication number: 20120049923
    Abstract: An output circuit includes a first output transistor disposed between a higher-potential power supply terminal and an external output terminal, a current flowing from the source of the first output transistor to the drain thereof being controlled on the basis of an external input signal; a second output transistor disposed between a lower-potential power supply terminal and the external output terminal, a current flowing from the source of the second output transistor to the drain thereof being controlled on the basis of an external input signal; and a clamping transistor having a first terminal and a control terminal, the first terminal and the control terminal being coupled to the gate of the first output transistor, and a second terminal coupled to the drain of the first output transistor.
    Type: Application
    Filed: August 1, 2011
    Publication date: March 1, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kouichi NISHIMURA, Hiromichi OHTSUKA, Toshikazu MURATA
  • Patent number: 8068537
    Abstract: A communication circuit for providing a bi-directional data transmission over a signal line, thereby receiving a first digital data stream and transmitting a corresponding first signal into a near end of a signal line to a remote device, the remote device being connected to a far end of the signal line, receiving a second signal at the near end of the signal line from the remote device and deriving a second digital data stream therefrom, having a replica generator for providing, in response to the first digital data stream or a signal derived therefrom, a replica signal, and an extraction circuit for extracting the second digital data stream from the second signal in response to the replica signal and a comparator signal deduced from the near end of the signal line and an automatic test equipment having a plurality of communication circuits each providing a bi-directional data transmission.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: November 29, 2011
    Assignee: Verigy (Singapore) Pte. Ltd.
    Inventor: Bernhard Roth
  • Patent number: 8064777
    Abstract: A system includes a laser generator, and a signal distortion generator circuit inline with the laser generator modulation signal and configured to generate distortion vectors in any of four distortion vector quadrants.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: November 22, 2011
    Assignee: ARRIS Group, Inc.
    Inventors: Venkatesh Gururaj Mutalik, Marcel Franz Christian Schemmann, Long Zou
  • Patent number: 8044698
    Abstract: A liquid level detection apparatus includes a resistance plate which has a conducting pattern formed on a board, the conducting pattern including a first slide portion, a second slide portion, a plus electrode electrically connected to the first slide portion, and a minus electrode electrically connected to the second slide portion, a float which moves in accordance with a change of a liquid level, a float arm connected to the float, a sliding arm which slides over the resistance plate in accordance with a pivotal movement of the float arm, a plus connection terminal connected to the plus electrode, a minus connection terminal connected to the minus electrode, and a protective layer formed on the plus connection terminal so as to cover the plus connection terminal.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: October 25, 2011
    Assignee: Yazaki Corporation
    Inventors: Yasunori Kawaguchi, Kenichi Tanaka, Toshio Oike
  • Patent number: 7940106
    Abstract: An apparatus for generating a correction signal for linearizing an output signal of a non-linear element includes a correction signal generator. The correction signal generator is configured to generate a correction signal on the basis of a superposition of a digital reference signal and a superposed output signal. The superposed output signal is based on a superposition of the output signal and an analog reference signal.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: May 10, 2011
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Christopher Laske, Gerald Ulbricht
  • Patent number: 7925170
    Abstract: A predistortion circuit provides a predistorted input signal that compensates for distortion generated by a non-linear amplifier such as a laser device. The predistortion circuit may be used in an optical transmitter designed for broadband applications, such as a laser transmitter used for forward path CATV applications. The predistortion circuit may include a primary signal path and a secondary signal path that receive an input signal. A second order distortion generator on the secondary signal path generates predistortion of a magnitude corresponding to the magnitude of, but at an opposite phase to, the distortion generated by the non-linear amplifier. The second order distortion generator includes diodes with an adjustable diode bias to control phase, magnitude and/or magnitude/phase versus frequency of the predistortion.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: April 12, 2011
    Assignee: Applied Optoelectronics, Inc.
    Inventor: Brian Ishaug
  • Patent number: 7868682
    Abstract: According to an embodiment of the present invention, an insulating communication circuit includes a first insulating circuit 62#11 having first and second circuits, a second insulating circuit 62#12 having third and fourth circuits, and a communication interface that is connected to a first ground and transmits a signal to the first circuit based on a communication signal and a clock signal from an external control device.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: January 11, 2011
    Assignee: Keihin Corporation
    Inventors: Kouji Suzuki, Kenichi Takebayashi, Kazutaka Senoo
  • Patent number: 7785284
    Abstract: The joint (36) comprises a tubular body (37) having two connecting zones (38, 39) each connected by an end to a tubular element (40) of a fluid transport line, giving continuity to passage of fluid. The tubular body is made of a mixture of an electrically-conductive material such as PVC, with carbon black to give it electrical conductivity. The joint has an internal surface (41) which is destined to come into contact with the transported fluid, and an external surface which is destined to have a grounded galvanic contact. The joint is inserted in the discharge fluid drainage line of a dialyzer filter, in an apparatus for intensive treatment of acute renal insufficiency, for eliminating ECG artefacts due to functioning of peristaltic pumps in the apparatus.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: August 31, 2010
    Assignee: Gambro Lundia AB
    Inventors: Vincenzo Baraldi, Annalisa Delnevo, Gianfranco Marchesi, Andrea Ligabue, Massimo Zaccarelli
  • Patent number: 7724079
    Abstract: Techniques and circuitry are provided for programmatically controlling signal offsets in integrated circuitry. In one embodiment, a buffer circuit having an offset cancellation circuit receives a signal and transmits the signal to programmable logic circuit. The programmable logic uses programmable resources and/or one or more algorithms to measure integrated circuit operations and/or operational errors associated with the offset. The control signal is fed back to an input of the offset cancellation circuit. In one embodiment, the offset cancellation circuit adjusts the offset of the signal in response to the magnitude of the offset cancellation signal received until changes associated with the offset and/or the magnitude of the operational errors are no longer attributable to the offset.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: May 25, 2010
    Assignee: Altera Corporation
    Inventor: Sergey Yuryevich Shumarayev
  • Patent number: 7710185
    Abstract: A CMOS transconductor for cancelling third-order intermodulation is provided. The transconductor includes a transconductance circuit and a tuneable distortion circuit. The transconductance circuit takes an input voltage and generates an output current having a transconductance element and an IM3 element. The distortion circuit takes the same input voltage and generates a current having an IM3 element of equal amplitude and opposite phase to the IM3 element of the transconductance circuit. A controller circuit tunes the distortion circuit to adjust its IM3 element to substantially equal the amplitude of the IM3 of the transconductance circuit. The distortion and transconductance circuits are arranged to sum their output currents thereby effectively cancelling the IM3 elements, leaving the transconductance relatively unmodified.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: May 4, 2010
    Assignee: Icera Canada ULC
    Inventor: Tajinder Manku
  • Patent number: 7634198
    Abstract: A distortion circuit is provided for correcting the distortion from a nonlinear circuit element by generating a frequency dependent signal having a sign opposite to the distortion signal produced by the nonlinear circuit and substantially the same magnitude. The distortion circuit includes an input signal and a first nonlinear device coupled to the input signal for generating a first signal and where the first nonlinear device has a first bias level. Also included is a second nonlinear device different from same first nonlinear device and coupled to the first nonlinear device for modifying the first signal to produce an output second signal, the second nonlinear device having a second bias level. A bias control means is provided for adjusting the first and said second bias levels so that the magnitude, phase and frequency of the output second signal can be adjusted.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: December 15, 2009
    Assignee: Emcore Corporation
    Inventor: Eva Peral
  • Patent number: 7613538
    Abstract: A method of contact lithography includes predicting distortions likely to occur in transferring a pattern from a mold to a substrate during a contact lithography process; and modifying the mold to compensate for the distortions. A contact lithography system includes a design subsystem configured to generate data describing a lithography pattern; an analysis subsystem configured to identify one or more distortions likely to occur when using a mold created from the data; and a mold modification subsystem configured to modify the data to compensate for the one or more distortions identified by the analysis subsystem.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: November 3, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Wu, Duncan Stewart, Shih-Yuan Wang, R. Stanley Williams
  • Patent number: 7561809
    Abstract: An integrated laser device includes a pre-distortion circuit. The pre-distortion circuit receives an electrical modulation signal and generates a pre-distorted modulation signal. A laser is integral with the pre-distortion circuit. The laser includes an electrical modulation input that is connected to the output of the pre-distortion circuit. The laser modulates an optical signal with the pre-distorted modulation signal. The pre-distorted modulation signal causes at least some vector cancellation of distortion signals generated when the laser modulates the optical signal.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: July 14, 2009
    Assignee: Finisar Corporation
    Inventors: Thomas R. Frederiksen, Jr., Stephen B. Krasulick
  • Patent number: 7541857
    Abstract: An impedance compensation circuit for inputs of a programmable device includes programmable impedance circuits connected with input nodes. The programmable impedance circuits can be configured to apply a compensating voltages to input nodes to reduce or eliminate unwanted offset voltages. An impedance compensation circuit may include resistors in series or current sources in parallel. A set of bypass switches selectively apply each resistor or current source to an input node, thereby changing the offset voltage of the node and compensating for impedance mismatches. Control logic provides signals to control the bypass switches. The control logic may be implemented using programmable device resources, enabling the control logic to be updated and improved after the manufacturing of the device is complete. The control logic can automatically evaluate offset voltages at any time and change compensating impedances accordingly. This reduces manufacturing costs and takes into account temperature and aging effects.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: June 2, 2009
    Assignee: Altera Corporation
    Inventors: Wilson Wong, Tin H. Lai, Sergey Shumarayev, Rakesh H. Patel
  • Patent number: 7397295
    Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a video input signal having a voltage. The second circuit may have a finite input resistance configured to generate a current in response to presenting the voltage across the finite input resistance. The third circuit may be configured to cancel the current by (i) generating the current in response to presenting the voltage across a replica resistor having a resistance similar to the finite input resistance and (ii) passing the current away from the apparatus.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: July 8, 2008
    Assignee: LSI Corporation
    Inventor: Ara Bicakci
  • Patent number: 7376358
    Abstract: An optical spike is generated at an arbitrarily selected location within an arbitrary optical link. The optical spike is generated by deriving a spike signal having a plurality of components, and launching the spike signal into the a transmitter end of the optical link. An initial phase relationship between the components is selected such that the involved signal components will be phase aligned at the selected location. In order to achieve this operation, the initial phase relationship between the components may be selected to offset dispersion induced phase changes between the transmitter end of the link and the selected location. One or more optical spikes can be generated at respective arbitrarily selected locations within the link, and may be used for performance monitoring, system control, or other purposes.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: May 20, 2008
    Assignee: Nortel Networks Limited
    Inventors: Kim Roberts, Maurice O'Sullivan
  • Publication number: 20080031382
    Abstract: A limiter for minimizing an amount of phase change caused by input amplitude variation includes a variable gain amplifier configured to receive a signal having an amplitude component and a phase component and having a gain controlled by a compensation capacitance and a variable resistance, in which the compensation capacitance minimizes an effect of parasitic capacitance and the variable resistance adjusts a gain in the variable gain amplifier such that the amplitude component at an output of the variable gain amplifier remains substantially constant.
    Type: Application
    Filed: June 29, 2007
    Publication date: February 7, 2008
    Inventor: Ichiro Aoki
  • Patent number: 7248092
    Abstract: In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5?Vtn] when an excessive voltage of negative polarity is applied.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: July 24, 2007
    Assignee: DENSO CORPORATION
    Inventors: Katsutoyo Misawa, Yasuyuki Ishikawa, Akira Suzuki, Yoshinori Teshima, Hideaki Ishihara, Toshiharu Muramatsu
  • Patent number: 7218687
    Abstract: A receiver with baseline wander correction for correcting a received input signal. The receiver includes first and second biasing resistor networks configured to receive first and a second signal of the received input signal, and to produce a first correction signal and a second correction signal. A comparator is employed to compare the first and the second correction signals in order to produce a control signal. The receiver also has comparison logic and compensation control circuitry. The comparison logic generates a logic signal according to the first and the second correction signals. Finally, the compensation control circuitry produces a compensation signal and provides it to respective output terminals of the first and the second biasing resistor networks so as to correct respective DC values of the first and the second correction signals.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: May 15, 2007
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chin-Wen Huang, Chao-Cheng Lee
  • Patent number: 7208992
    Abstract: System and method for even order and odd order nonlinear distortion of a compensating signal that removes substantially all of the nonlinear distortion in one order or in two orders. Two or more diodes are arranged in at least one of an anti-series configuration and an anti-parallel configuration in which a circuit voltage is equal to a selected odd order and/or to a selected even order in current, plus higher order terms that are often negligible. The diodes may be replaced by other selected nonlinear devices.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: April 24, 2007
    Assignee: C-COR.net Corporation
    Inventors: Somnath Mukherjee, Yahsing Yuan, Mridul K. Pal
  • Patent number: 7113606
    Abstract: There is provided an adjustable harmonic distortion detector that includes a clock signal source, means for the detection of a first period of evaluation, and means for the detection of a second period of evaluation. The detector has the characteristic that a first block memorizes a number equal to the clock pulses present in the first period of evaluation, a multiplier block performs a multiplication between the number stored in the first block and a multiplicative factor during the second period of evaluation, and a second block memorizes the outcome. The second block is adapted to generate an output signal when the outcome in the second block is equal to zero.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: September 26, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Edoardo Botti, Mauro Cleris, Antonio Grosso