Abstract: A semiconductor device turns on and off a power switching device having a gate terminal and output terminals between which an output current is produced by a gate voltage applied to the gate terminal. The semiconductor device includes: an output current detector detecting a current value correlated with the output current; a voltage detector detecting a voltage across the output terminals of the power switching device; a clamp circuit clamping the gate voltage at a predetermined value; and a controller controlling the clamp circuit to adjust the gate voltage based on the voltage detected by the voltage detector. The controller controls the clamp circuit to set the gate voltage to be at a minimum voltage according to the detected voltage to cause the output current to be larger than a threshold current required for detecting the short circuit in the power switching device.

Abstract: In one implementation, a voltage converter includes a driver providing a gate drive for a power switch and a sense circuit coupled across the power switch. The gate drive provides power to the sense circuit, and the sense circuit provides a sense output to the driver corresponding to a current through the power switch. In one implementation, the sense circuit includes a high voltage (HV) sense transistor coupled between a first sense input and a sense output, a delay circuit configured to be coupled to the gate drive to provide power to the HV sense transistor when the gate drive is high, and a pull-down transistor configured to couple the sense output to a second sense input when the gate drive is low.

Abstract: A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state.

Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter.

Abstract: A digital input unit for an automation device includes at least one current drawing DC input channel for connecting a transducer operated at a nominal DC voltage, where the input channel is configured to set the current based on an input voltage (UEM) according to an input characteristic curve. Measures are proposed, as a result of which the digital input unit is suitable for connecting transducers of different supply voltages, where the digital input unit is operable with a reduced power loss.

Abstract: A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state.

Abstract: Conventional circuits often have undesirable characteristics to due “hot spots” or use a large amount of area. Here, however, a charging circuit is provides that uses an improved driver. Namely, an amplifier within a current sensor is used to control the rate that a switch can charge an external capacitor. This is accomplished through the adjustment of the gain of the amplifier during a charging mode.

Abstract: In various embodiments, applicants' teachings are related to an active guarding circuit and method for reducing parasitic impedance signal loading on a signal-transmission channel that is shunted by a parasitic impedance. The presence of an electrical signal on the signal-transmission channel causes a leakage current to flow through the parasitic impedance. In various embodiments, the circuit comprises an amplifier and an impedance, one terminal of the impedance is coupled to the signal-transmission channel. The input of the amplifier is coupled to the signal-transmission channel and the output is coupled to the other terminal of the impedance so as to cause a compensation current to flow through the impedance. The gain of the amplifier and the value of the impedance are selected so that the compensation current has a magnitude substantially equal to the leakage current magnitude.

Abstract: An in-rush or out-rush current limiting circuit employs a low number of components to effect in-rush current limiting and may be employed in dongles or on-chip (in the case of serving as an out-rush current limiting circuit). The in-rush current limiting circuit may be employed, for example, in USB dongles, Display Port (DP) dongles, or any other suitable connector as desired. Alternatively, the circuit may be integrated onto a circuit board or within an integrated circuit as desired. Among other advantages, a lower cost, low complexity solution may be provided. In addition, bulk capacitance can be increased such as by employing a trickle resistor or other suitable limiting structure.

Abstract: An in-rush or out-rush current limiting circuit employs a low number of components to effect in-rush current limiting and may be employed in dongles or on-chip (in the case of serving as an out-rush current limiting circuit). The in-rush current limiting circuit may be employed, for example, in USB dongles, Display Port (DP) dongles, or any other suitable connector as desired. Alternatively, the circuit may be integrated onto a circuit board or within an integrated circuit as desired. Among other advantages, a lower cost, low complexity solution may be provided. In addition, bulk capacitance can be increased such as by employing a trickle resistor or other suitable limiting structure.

Abstract: An embodiment of an input-buffer circuit may include an input stage with an inverter having an input operable to receive a signal to be translated. The input stage may include a limiting circuit coupled to the input stage for arresting quiescent current. Additional embodiments of an input-buffer circuit formed according to the subject matter disclosed herein may include feedback transistors suited to provide additional current to the input stage and a hysteresis circuit suited to provide hysteresis current to the input stage when an input signal has a high-frequency change rate.

Abstract: A voltage level clamping circuit which can be implemented in an integrated circuit (IC) and a high-speed comparator module, wherein the IC includes a parasitic diode coupled between a first voltage source and a second voltage source. The voltage level clamping circuit includes a switch module coupled between the first voltage source and the second voltage source and a comparator module having an output terminal coupled to the switch module, a first input terminal coupled to the first voltage source, and a second input terminal coupled to the second voltage source, for comparing a voltage level of the first voltage source with a voltage level of the second voltage source to generate an output signal, and transmitting the output signal to the switch module to control a conducting state of the switch module to selectively clamp the voltage level of the second voltage source.

Abstract: An electronic device under test (DUT) may be incorporated into a circuit having a voltage limiter connected in parallel with the DUT. The circuit includes a controlled current source having an output current connected in series with the DUT. The voltage limiter is characterized in that, when the output current is such that the voltage across the DUT (Vdut) would exceed a particular maximum voltage Vmax, without the voltage limiter in place, at least a portion of the output current flows through the voltage limiter, so as to limit Vdut to be less than or equal to Vmax. When the output current is such that Vdut would be less than or equal to Vmax, current does not flow through the voltage limiter. The circuit may include a plurality of DUTs, each DUT connected in series with the output current of a controlled current source, with a voltage limiter connected in parallel with each DUT.

Abstract: A level translator has an inverter comprising a first transistor having a first predetermined voltage threshold and a second transistor having a second predetermined voltage threshold. The two transistors have control gates being of complementary conductivity. A first capacitor is connected at one end to the gate of the first transistor and at a second end to an input signal. A second capacitor is connected at one end to the gate of the second transistor, the input signal being applied to a second end of the second capacitor. A comparator is used for detecting the relationship between the input signal and a reference voltage. A first current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the first transistor. A second current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the second transistor. A first clamp circuit is used for limiting a gate voltage of said first transistor.

Abstract: An integrated circuit radio transceiver and method therefor includes a linear regulator an output transistor for producing a current into an output node of the regulator wherein an amplification block is operable to produce a bias signal to a gate terminal of the output transistor to operably bias the output transistor to produce the current into the output node of the regulator. A current steering amplification block is operably disposed to steer current in/out of the gate of the output transistor (depending on device type) based upon the current being conducted through the output node of the regulator exceeding a specified threshold. The current steering amplification block further includes a current sinking element operably disposed to sink a specified amount of current to define the specified threshold.

Abstract: A low differential output voltage circuit having a voltage generator and a differential output unit is provided. The voltage generator includes a first PMOS transistor, a first amplifier circuit, a unit gain stage, a first NMOS transistor, a second NMOS transistor. The differential output unit includes a first controlled current source, a second controlled current source, a common voltage circuit, a first switch, a second switch, a third switch, and a fourth switch. Due to the voltage generator directly provides a common mode voltage to the differential output unit, and the first amplifier circuit and the unit gain stage could overcome a channel modulation effect of MOS transistors and enhance the driving ability of the common mode voltage respectively. Thus, a response time of the invention is decreased, and an output current of the differential output unit is in a proportion to the reference current received by the voltage generator.

Abstract: A level translator has an inverter comprising a first transistor having a first predetermined voltage threshold and a second transistor having a second predetermined voltage threshold. The two transistors have control gates being of complementary conductivity. A first capacitor is connected at one end to the gate of the first transistor and at a second end to an input signal. A second capacitor is connected at one end to the gate of the second transistor, the input signal being applied to a second end of the second capacitor. A comparator is used for detecting the relationship between the input signal and a reference voltage. A first current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the first transistor. A second current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the second transistor. A first clamp circuit is used for limiting a gate voltage of said first transistor.

Abstract: A method and a circuit for controlling at least one thyristor constitutive of a rectifying bridge with a filtered output, including closing the thyristor when the voltage thereacross becomes greater than zero, and making the gate current of the thyristor disappear when the current therein exceeds its latching current.

Abstract: An interconnect circuit for communicating data. The interconnect circuit including at least one driver to receive and transmit data. At least one termination device in communication with each driver. A first power supply having an output to supply power to the driver. A second power supply having an output to supply power to the termination device. A first decoupling capacitor in communication with the first power supply output and the second power supply output.

Abstract: A power switching device has a power switching transistor connected in series in a load circuit with an inductive load portion and a commutation circuit. The commutation circuit is connected in parallel with the gate-drain or base-collector path of the power transistor and has a first Zener diode, which determines the commutation clamping voltage for switching on the power switching transistor during commutation, and an oppositely biased normal diode that is connected in series with the first Zener diode. The commutation circuit further has control elements in order to reduce, during a short time, the commutation clamping voltage at the beginning of each commutation cycle or after an adjustable delay from the beginning of each commutation cycle.

Abstract: The invention concerns a semi-conductor device comprising on a substrate: a first dynamic threshold voltage MOS transistor (10), with a gate (116), and a channel (111) of a first conductivity type, and a current limiter means (20) connected between the gate and the channel of said first transistor. In accordance with the invention, this first transistor is fitted with a first doped zone (160) of the first conductivity type, connected to the channel, and the current limiter means comprises a second doped zone (124) of a second conductivity type, placed against the first doped zone and electrically connected to the first zone by an ohmic connection. Application to the manufacture of CMOS circuits.

Abstract: The present invention provides a Driver circuit having dynamically adjusting output current and limiting input current function. This present invention dynamically adjusts the output current provided by the driver unit to reduce this output current in real time. A protection circuit is also provided to limit the input current supplied to the driver unit. This present invention avoids overdriving the driver unit.

Abstract: In a current switching circuit, a complementary circuit switches, in response to an input signal, a pair of current mirror circuits between a first state, enabling the first of the current mirror circuits, through a first current mirror current and disabling the second of the current mirror circuits, and a second state, disabling the first of the current mirror circuits and enabling the second of the current mirror circuits, through a second current, mirror current such that at least one of the first and second current mirror currents flows through a level shift circuit as a level shift current.

Abstract: According to some embodiments, a device includes a phase generator to generate m control signals, each of the m control signals associated with a respective signal period, and at least m filters, each of the at least m filters comprising m-n taps, each of the m-n taps to receive one of the m control signals, to acquire a signal sample according to a signal period associated with the received control signal, and to modulate the signal sample according to a weighting coefficient associated with the tap. The device further includes m evaluation circuits, each evaluation circuit associated with a respective one of the at least m filters and to output a sum of signal samples modulated by the taps of the associated filter in response to one of the m control signals associated with a signal period other than the signal periods according to which the signal samples were acquired.

Abstract: A circuit configuration for driving a load is described. The circuit configuration has a first and a second connecting terminal for connecting the load, a first drive input for applying a first drive signal, and a first semiconductor switching element having a first load terminal connected to the first connecting terminal, a second load terminal connected to the second connecting terminal and a drive terminal coupled to the drive input. A voltage limiting circuit is provided and is connected between the first load terminal and the drive terminal of the first semiconductor switching element.

Abstract: In one embodiment of the invention, a clamping circuit clamps an input signal to reduce overshoot and ringback. A pulse generator generates a pulse signal having a pulse interval from the input signal and a delayed signal. The input signal transitions from a first level to a second level. The delayed signal is derived from the input signal. A controller generates a control signal responsive to the pulse signal. A switching circuit clamps one of the overshoot and the ringback of the input signal within the pulse interval upon receipt of the control signal.

Abstract: An output drive circuit of an output buffer circuit has a signal output line and first, second and third switching circuits connected to the signal output line at different locations thereof. Each of the first, second and third switching circuits includes one of first switching devices connected between a power source line and the signal output line, and one of second switching devices connected between the signal output line and a ground line. Each of the first, second and third switching circuits includes one of first control signal lines that turn on and off the first switching devices, respectively, and one of second control signal lines that turn on and off the second switching devices, respectively. Drivabilities of the first and/or the second switching devices in the switching circuits are set to gradually increase in a specified order.

Abstract: A current mode step attenuation control circuit with digital technology. The circuit includes several stages of serially connected current attenuation circuits, each having a digital control input port, common mode feedback signal input port and bias input port, which are connected to corresponding a digital control signal, a common mode feedback current and a bias voltage, respectively. An analog input signal inputted to the circuit is controlled by the digital control signal to implement step attenuation. By using the conducting resistance of a MOS transistor to form equivalent resistance or match of current source for attenuation, the circuit eliminates dependence on resistance match of conventional technology. Because step attenuation is directly controlled by a digital control signal, the transmission speed is fast, phase delay is small, control accuracy is high and the device is suitable for digital integrated circuit manufacturing technology.

Abstract: An output current limiter circuit is effectively insensitive to variations in temperature. A first arm of each of an NPN and a PNP network has a first auxiliary resistor, the current through which is proportional to temperature, and compensates for the negative temperature coefficient of the base-emitter voltage of that arm's (NPN or PNP) transistor, as well as tracks the positive temperature variation in the Vbe-bias control resistor in the other arm of the network. The other arm includes a second additional resistor, the voltage across which is established by a (fixed) bandgap voltage device, that uses a current from which the current through the first arm of the network is derived.

Abstract: This semiconductor integrated circuit is constituted by any one of a p-channel MOS transistor and an n-channel MOS transistor, and is connected between the control terminal and the common terminal so as to produce predetermined voltage. The comparing circuit is operated in response to a control voltage applied between the control terminal and the common terminal so as to compare the predetermined reference voltage with the current-detected voltage which is obtained from the current detecting circuit. The gate controlling MOS transistor controls a gate voltage of the power MOS transistor based upon the comparison output of the comparing circuit. Then, all of these structural members are formed on the same semiconductor substrate.

Abstract: A device for automatically varying resistance includes a comparator for comparing a control voltage to a reference voltage; a switch operatively coupled to the comparator; and a first resistor and second resistor operatively coupled in a series connection between a pull-up voltage and a signal line. The switch is operatively coupled in a parallel connection with the first resistor and, based on the comparison between the control voltage and the reference voltage, the switch selectively bypasses the first resistor. A method of automatically varying resistance includes comparing a control voltage and a reference voltage; pulling-up a signal line to a pull-up voltage through a first resistor and a second resistor operatively connected in series if the comparison has a first outcome; and pulling up the signal line to the pull-up voltage through only the second resistor if the comparison has a second outcome.

Abstract: A current clamp circuit which can easily restrict an output current externally in an output current amplifier circuit using a current buffer IC, is provided. The current clamp circuit 10 restricts the output current in the output current amplifier circuit 20 for amplifying the output current by using the operational amplifier 2 and the current buffer IC 1, wherein the resistor 4 is connected to the output terminal of the current buffer IC, and the output current restriction unit for restricting the output current is connected to the current buffer IC 1 and the resistor 4 in parallel.

Abstract: This semiconductor integrated circuit is constituted by any one of a p-channel MOS transistor and an n-channel MOS transistors and is connected between the control terminal and the common terminal so as to produce predetermined voltage. The comparing circuit is operated in response to a control voltage applied between the control terminal and the common terminal so as to compare the predetermined reference voltage with the current-detected voltage which is obtained from the current detecting circuit. The gate controlling MOS transistor controls a gate voltage of the power MOS transistor based upon the comparison output of the comparing circuit. Then, all of these structural members are formed on the same semiconductor substrate.

Abstract: A circuit for addressing leakage. The circuit may have a variable supply stage having an active load in parallel with a switch transistor where the active load and the switch transistor are coupled to a decoupling capacitor. The circuit may also have a leakage detect stage having a leak device coupled to a critical node. An embodiment of the circuit may have a supply node; an input node; an output node; a buffer stage where the buffer stage supply node is coupled to a variable supply stage output, the buffer stage input is coupled to the input node and the buffer stage output is coupled to the output node; a leakage detect stage where the leakage detect stage supply node is coupled to the supply node and the leakage detect stage input is coupled to the input node; and a variable supply stage where the variable supply stage supply node is coupled to the supply node and the variable supply stage input is coupled to the leakage detect stage output.

Abstract: A semiconductor device including a current source having a first node coupled to a terminal, and a second node for extracting a current in response to an electrostatic discharge (ESD) on the terminal. The semiconductor device further including a transistor having a control electrode, a first current electrode coupled to the terminal, and a second current electrode coupled to the second node of the current source, and including a resistive element coupled to a first voltage reference node and the second node of the current source. The transistor of the semiconductor device is biased by detecting a negative voltage event (such as an ESD) at a first current electrode of the transistor and biasing a second current electrode of the transistor in response to detecting the negative voltage event, wherein the biasing of the second current electrode is for preventing a forward biasing of an p-n junction associated with the transistor.

Abstract: In a method and an arrangement for adapting, from a DC point of view, the signal input of a first circuit, lying at a first DC voltage, to the signal output of at least one second circuit, lying at a second DC voltage, the signal input terminal is connected to the respective signal output terminal of the respective second circuit via a respective first resistance, whereby first DC currents will be allowed to flow through the respective first resistance. The signal input is adapted to be virtually short-circuited to a source for the first DC voltage, which is of a predetermined value, separate from zero. The first circuit is adapted to internally generate a DC cancellation current and bring it to flow in the signal input. The signal input is to be connected to ground via a selectable, second resistance, whereby a second DC current will flow through the second resistance.

Abstract: Leading-edge blanking circuits blank the leading edge of a current sense signal generated by sensing circuitry sensing the current through a switching field-effect transistor. A current sensor is employed to sense the magnitude of gate current being provided to the gate of the switching transistor by a driver circuit. A comparator indicates whether the sensed magnitude of the gate current exceeds a predetermined threshold current. A blanking circuit component, such as a transistor connected to ground, is also used. In one blanking circuit, the blanking component forces the current sense signal to zero when the comparator indicates that the gate current of the switching transistor exceeds the threshold current, and otherwise allows the value of the current sense signal to be determined by the current-sensing circuitry. In another blanking circuit, a latch is interposed between the comparator and the blanking component. The latch generates a blanking control signal to control the blanking component.

Abstract: A drive circuit for a field-effect-controlled semiconductor component reduces a charging current for driving the field-effect-controlled semiconductor component when a load current limiting responds. That prevents an increase in current consumption of the drive circuit while maintaining a short switching time.

Abstract: A soft clipper circuit in CMOS technology not only allows the knee to be programmed, but also the slope of the curve after the knee to be programmed. This is accomplished by putting a second transconductance in parallel with the first transconductance, and using a switching circuit to connect the output of the second transconductance to that of the first transconductance when the knee level is reached. This is determined by a comparator which has an input coupled to the second transconductance and controls a control node of the switching circuit.

Abstract: A signal conditioning module for sensing multiform field signals and for providing isolated digital signals appropriate for a processing system. The present invention allows sensing of field signals which are either AC or DC and which have magnitudes ranging from zero to greater than 240 volts in the preferred embodiment. A circuit according to the present invention includes a bidirectional maximum current limiter coupled to a bidirectional isolation current sensor. The current sensor preferably includes an opto-coupler. The current limiter preferably includes cross-coupled depletion mode devices and a current limit resistor. In this manner, current flowing through the resistor develops a voltage for turning off one depletion mode device or the other depending upon the polarity of the current, so that the input current is limited to a predetermined maximum level for a wide voltage range of input signals and regardless of voltage polarity.

Abstract: A circuit for limiting the current flow in a "pluggable" circuit during start-up or circuit fault conditions employs a MOSFET in conjunction with a feedback system, wherein a source terminal of the MOSFET is connected to a power supply bus and a drain terminal of the MOSFET is connected to the circuit to be current limited, respectively. A gate terminal of the MOSFET is controlled by a pair of op amps, wherein the first op amp amplifies the voltage across a current sensing resistor between the MOSFET and the circuit and outputs this pre-amplified voltage into the second op amp, and the second op amp amplifies the difference between this pre-amplified voltage and a first reference voltage. The output of the second op amp is connected to the gate terminal of the MOSFET, thereby varying the voltage at the gate terminal, as the output of the second op amp varies.

Abstract: The present invention is aimed at providing a method and a circuit for protecting the output stage of a power actuator against voltage transients of the surge type. In particular, it provides protection against voltage surge transients of the kind described by International Standard IEC 801-5, for a power transistor contained in the output stage of the actuator.The method of this invention provides for:the utilization of the power transistor (PW) intrinsic diode (DP) for dumping the transient energy to one of the supply generator terminals during a positive transient; andthe utilization of the power transistor (PW) restoration feature to the on state for dumping the energy thereinto during a negative transient, while simultaneously inhibiting the current limiting function.

Abstract: A signal generator and method that is tolerable to supply voltage fluctuations and differentials. A current switch is driven that is independent of the supply voltage. By clamping the slewing voltage at the gate of a transistor driver, the difference between the clamped gate voltage and the threshold turn on voltage of the driver will be constant with respect to the supply voltage. This will cause the transition edges of the driver's output voltage to be constant with respect to the supply voltage. This technique minimizes variations in the output signal edge transitions as the supply voltage varies over various tolerance ranges. Because this technique increases the control of the transition edges in the output signal, it is possible to generate much slower edges and still maintain a consistent transition voltage shape with variations in the supply voltage and the symbol width.

Abstract: An IGBT driving circuit includes an IGBT connected in series with a primary winding of an ignition coil and a current detecting resistor. A transistor is connected to the gate of the IGBT to apply a gate voltage in response to an ignition signal. A comparator compares a voltage produced across the current detecting resistor with a comparison voltage. An NPN transistor connected to the gate of the IGBT turns on and off in response to the comparison result of the comparator to adjust the gate voltage. The gate voltage is fed back to the detection terminal side of the comparator for oscillation suppression through an oscillation suppressing resistor. A charge/discharge control resistor is connected between the gate of the IGBT and the oscillation suppressing resistor and a diode is connected in parallel with the charge/discharge control resistor, so that the electric current flowing to the IGBT is maintained constant.

Abstract: A clamping circuit for clamping a circuit node during an initial circuit powerup interval includes a switching circuit and a switching control circuit. The switching circuit is an N-MOSFET with its drain and source terminals connected to circuit ground and the subject node sought to be clamped, respectively, and its gate terminal connected to the switching control circuit. The switching control circuit includes a number of N-MOSFETs which are interconnected in such a manner as to receive the power supply voltage and generate a switching signal which turns the switching circuit N-MOSFET on during an initial circuit powerup interval to clamp the subject node and then off after the power supply has reached a preselected minimum value. Upon initial circuit powerup, the switching control circuit self-triggers itself to turn the switching circuit on and clamp the subject node at ground potential.

Abstract: A current clamping circuit is provided which clamps a current signal to a predetermined reference current level. An input current signal and a reference current signal are supplied to the clamping circuit. The clamping circuit includes a current differencing device which determines the difference between the input current signal and the reference current signal. This current difference is summed with the original input current signal or a mirror thereof at a summing node to produce an output signal which is clamped at the predetermined reference current level.

Abstract: A non-linear transmission line terminator (10) is provided in which voltages appearing on a transmission line are sensed. If the voltage level sensed is equal to a predetermined voltage, the non-linear transmission line terminator (10) couples a reference voltage to the transmission line. If the sensed voltage is less than the predetermined voltage, the non-linear transmission line terminator (10) delivers current to the transmission line having a magnitude related non-linearly to the sensed voltage.

Abstract: An interface circuit for linking microprocessors, intended to limit the current (Iout) in the link (L1-L2) by inserting in the link the emitter-collector path of a first transistor (T.sub.1) which is in the saturated state during operation. This circuit includes a second transistor (T.sub.2) which has a geometry k times smaller than that of the first transistor (T.sub.1) and which is coupled to the first transistor (T.sub.1) so as to produce a copy (Iy) of the link current (Iout), and a base current generator (10) which produces an output current (Iz) which feeds the bases of the first and the second transistor (T.sub.1, T.sub.2), and which is a regressive function of the copy current (Iy), on the basis of a fixed reference current (I.sub.0). A pair of transistors (T.sub.3, T.sub.4), similar to the first and the second transistor (T.sub.1, T.sub.2) but connected to the link (L1-L2) in an inverted manner, provides protection for bidirectional operation.

Abstract: A current rise in fall time limited voltage follow is shown having a voltage driver providing a voltage signal into a current driver. The output of the current driver is a load varying in resistance, for example, as the number or combination of devices connected to the load vary. The maximum current into the load and the maximum rise time of the current into the load is limited at the output of the current driver to a maximum by the input impedance of the current driver. The rise time and the current into the load may increase until the resistance of the load is substantially that of the current driver input resistance reduced by a factor of N. The factor N is the maximum current capability of the output of the current driver related to the current driver input current generated by the voltage signal from the voltage driver.

Abstract: A semiconductor device with an excess current prevention circuit includes a bootstrap circuit, a first NMOS transistor, a second NMOS transistor and a constant voltage element. The first NMOS transistor has a drain electrode to receive a power supply potential, a gate electrode to receive an output of the bootstrap circuit, and a source electrode connected to an output terminal to which an output load is connected. The second NMOS transistor has a gate electrode whose potential is held at the power supply potential and a source electrode connected to-the output terminal. The constant-voltage element such as a diode or a Zener diode is connected between the gate electrode of the first NMOS transistor and the drain electrode of the second NMOS transistor.