Abstract: A comparator circuit includes an input stage with a set of differential current paths and a pair of differential input transistors connected to a pair of input terminals. An output stage includes an output current path between a first and a second supply terminal, an output transistor connected in the output current path and having a control terminal coupled to the set of differential current paths, and a comparator output connected to the output current path. An auxiliary stage includes an auxiliary current path between the supply terminals, an auxiliary current source, a first auxiliary transistor connected in the auxiliary current path and having a control terminal connected to the control terminal of the output transistor, and a voltage follower with a second auxiliary transistor and a third auxiliary transistor.

Abstract: A comparator includes a first-stage op amp circuit, a second-stage op amp circuit, a bias circuit and a clamping circuit. The first-stage op amp circuit includes two voltage input terminals and a voltage output terminal; the second-stage op amp circuit is connected with the bias circuit and the voltage output terminal of the first-stage op amp circuit; and the clamping circuit is connected with the voltage output terminal of the first-stage op amp circuit. By adding a clamping circuit in the comparator, the highest voltage at the voltage output terminal of the first-stage op amp circuit can be clamped to a preset voltage. During the operation of the comparator, the voltage change range of the voltage output terminal of the first-stage op amp circuit is smaller, which reduces the discharge delay of the voltage output terminal of the first-stage op amp circuit, thereby increasing the flip speed of the comparator.

Abstract: An electronic chip includes a chip core including an input terminal, an output terminal, an external pad, and an input-output circuit coupled to the chip core and the external pad. The input-output circuit includes an enable terminal coupled to the chip core, a connection terminal coupled to the external pad, a switchable diode device coupled between a supply voltage and a reference voltage, and a levelling circuit. The switchable diode device is coupled to the connection terminal and the enable terminal and is configured to operate as a diode in response to a control signal in a first state applied to the enable terminal and to operate as an open circuit in response to the control signal in a second state applied to the enable terminal. The levelling circuit is coupled to the connection terminal, the input terminal of the chip core, and the output terminal of the chip core.

Abstract: A neuromorphic weight cell (NWC) including a resistor ladder including a plurality of resistors connected in series, and a plurality of shunting nonvolatile memory (NVM) elements, each of the shunting NVM elements being coupled in parallel to a corresponding one of the resistors.

Abstract: Nonlinear bandwidth compression circuitry is provided. In examples discussed herein, nonlinear bandwidth compression circuitry can be configured to modify predefined amplitude(s) of a predefined voltage waveform to generate modified amplitude(s) of a modified voltage waveform that is never less than the predefined amplitude(s) of the predefined voltage waveform. Thus, by providing the nonlinear bandwidth compression circuitry in an envelope tracking (ET) system to perform bandwidth compression, signal distortion(s) resulted from the bandwidth compression can be corrected (e.g., via digital pre-distortion). As such, the ET system can amplify a radio frequency (RF) signal having a signal modulation bandwidth exceeding a voltage modulation bandwidth limitation of the ET system, without degrading spectral performance of the RF signal.

Abstract: Transistor devices are provided. A transistor device includes a unipolar transistor coupled between a first terminal and a second terminal; and a bipolar transistor coupled in parallel to the unipolar transistor between the first terminal and the second terminal. The bipolar transistor is configured to carry a majority of a current flowing through the transistor device when at least one of the current or a control voltage controlling the unipolar transistor and the bipolar transistor exceeds a predetermined threshold. The bipolar transistor is further configured to have a threshold voltage higher than a threshold voltage of the unipolar transistor, and a difference between the threshold voltage of the bipolar transistor and the threshold voltage of the unipolar transistor is at least 1 V.

Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage.

Abstract: A method and an apparatus for measuring a bioimpedance are disclosed. The apparatus includes a first electrical signal generator configured to generate a first electrical signal to measure a bioimpedance of an object. The apparatus also includes a compensation signal generator configured to generate a compensation signal to compensate a biosignal measured based on the first electrical signal, and an amplifier configured to amplify the compensated biosignal.

Abstract: A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal.

Abstract: Memory access circuitry controls access to multiple memory units with two access units. Arbitration circuitry forwards memory access requests for one memory unit to a first access unit, for a further memory unit to a second access unit, and for yet further memory unit to one of the first or second access units. The access units store requests in a queue prior to transmitting them to the respective memory unit. Tracking circuitry tracks requests and determines when to transmit subsequent requests from the queue. Control circuitry sets a state of each access unit to one of active, prepare and dormant, switches states of the two access units periodically, and does not set more than one access unit to the active state at the same time.

Abstract: An electronic apparatus includes a communication unit that performs wireless communication, a load unit, a power receiving unit that wirelessly receives power from a power supply apparatus, and a control unit that controls to limit a supply of power to the load unit if the communication unit transmits data to the power supply apparatus.

Abstract: To provide a switch circuit in which ON/OFF control can be realized even in a state where high voltage is not applied, and high voltage can be completely lowered to the ground. Provided is a switch circuit that includes plural MOS switches connected in series in such a manner that the source of one element is connected to the drain of another between high voltage and a system ground and that switches a connection state between the high voltage and the system ground, the switch circuit including: a MOS switch 101 the source of which is connected to the system ground among the plural MOS switches; a MOS switch 102 the source of which is connected to the drain of the MOS switch 101 in a shared manner and the drain of which is connected to the high voltage side among the plural MOS switches; a MOS switch 103 the drain of which is connected to the gate of the MOS switch 102 in a shared manner; and a resistor 104 that is connected in parallel between the gate and the source of the MOS switch 102.

Abstract: Exemplary embodiments or implementations are disclosed of methods, apparatus, and systems for a volume limiter circuit. A rectifier sub-circuit is configured to rectify at least a portion of an audio signal received from an audio source. A junction field effect transistor (JFET) has a channel connected in series between the audio source and a speaker. A feedback sub-circuit is configured to provide a gate signal at a gate of the JFET and to modulate a control signal in accordance with the audio signal crossing the JFET channel. The feedback sub-circuit is connected with the rectifier sub-circuit so as to extend a range of variable resistance of the JFET channel. The limiter circuit provides functionality that changes in response to varying audio voltages.

Abstract: A system and method for limiting in-rush current from a power source to a load includes sensing that a load has been electrically connected to receive electrical power from the power source. A current limiter circuit is configured to at least inhibit electrical current flow from the power source to the load for a predetermined time period. After the predetermined time period, the current limiter circuit is configured to no longer at least inhibit the electrical current flow from the power source to the load. Upon sensing that the load has been electrically disconnected from the power source, the current limiter circuit is reconfigured to at least inhibit electrical current flow from the power source to a load that may be subsequently connected to receive electrical power from the power source.

Abstract: A circuit having an active mode and a sleep mode includes a power transistor, an amplifier, and a protection circuit. The power transistor has a first current electrode coupled to a first power supply terminal, a second current electrode as an output of the circuit for coupling to a load, and a control electrode, wherein the power transistor is characterized by having a threshold voltage and a leakage current, wherein the leakage current occurs between the control electrode and the first current electrode during the sleep mode. The amplifier has an output coupled to the control electrode of the power transistor that provides an active output during the active mode. The protection circuit detects the leakage current and prevents the leakage current from developing a voltage on the control electrode of the power transistor that exceeds the threshold voltage of the power transistor.

Abstract: A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal.

Abstract: In a method for generating a pulse sequence for operating a magnetic resonance (MR) system for acquiring data from an examination subject having an interfering object in the patient's body, the bandwidths of at least two of the RF (radio-frequency) pulses in the pulse sequence are matched such that the matched RF pulses respectively excite a congruent slice when they are radiated into an examination subject under the effect of a slice selection gradient of identical amplitude. The matching of the RF pulses in the manner ensures so that the respective slices excited by the at least two RF pulses are subject to the same nonlinearities and inhomogeneities, and therefore the same spatial distortions, and so that signal losses due to inconsistent excitations of the two pulses are avoided. The image data that can be acquired with the pulse sequence are therefore optimized.

Abstract: The invention relates to an electronic device comprising an RF-LDMOS transistor (1) and a protection circuit (2) for the RF-LDMOS transistor. The protection circuit (2) comprises: i) an input terminal (Ni) coupled to a drain terminal (Drn) of the RF-LDMOS transistor (1); ii) a clipping node (Nc); iii) a clipping circuit (3) coupled to the clipping node (Nc) for substantially keeping the voltage on the clipping node (Nc) below a predefined reference voltage, wherein the predefined reference voltage is designed to be larger than the operation voltage on the drain terminal (Drn) and lower than a trigger voltage of a parasitic bipolar transistor (100) that is inherently present in the RF-LDMOS transistor; iv) a capacitance (Ct) coupled between the clipping node (Nc) and a further reference voltage terminal (Gnd), and v) a rectifying element (D1, D2) connected with its anode terminal to the input terminal (Ni) and with its cathode terminal to the clipping node (Nc).

Abstract: A circuit includes a first input transistor and a first voltage divider coupled to a source of the first input transistor and a second input transistor and a second voltage divider coupled to a source of the second input transistor. A first set of series connected transistors include a first transistor with a gate coupled to the first input transistor source and a second transistor with a gate coupled to a tap of the first voltage divider. A second set of series connected transistors include a third transistor with a gate coupled to the second input transistor source and a fourth transistor with a gate coupled to a tap of the second voltage divider. An output is coupled to the sources of the first and second input transistors. The first and second sets are coupled to one of the first input transistor drain or second input transistor drain.

Abstract: A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state.

Abstract: Various implementations include circuits, devices and/or methods that provide open loop current limiting power amplifiers and the like. In some implementations, an open loop current clamp includes a trim module to provide a control value and a limiting source having respective input and output terminals. The input terminal is coupled to the trim module to receive the control value. The output terminal coupled to a control terminal of the first transistor to provide a limiting electrical level produced in response to the control value by the limiting source. The limiting electrical level substantially setting a first mode of operation for the first transistor such that the current draw of the first transistor is substantially determined by the first mode of operation and the limiting electrical level such that a voltage at an output terminal of the first transistor exerts reduced influence on the current draw.

Abstract: A fast response time, self-activating, adjustable threshold limiter including a limiting element LE, a first coupling element CE1 electrically connected from a signal node of LE to a control input of LE, and a second coupling element CE2 electrically connected from the control input of LE to a nominal node of LE. An initial bias (control) voltage is also supplied to the control input of LE to dynamically control the limiting threshold for the limiter.

Abstract: A clamping circuit includes a clamping element with a control terminal and a load path that is coupled between a first circuit node and a second circuit node. A control circuit is coupled between the first circuit node and the second circuit node and is also coupled to the control terminal of the clamping element. The control circuit includes at least one snap-back unit with two load terminals and is only coupled between the first circuit node and the control terminal of the clamping element. The snap-back unit has an electrical resistance between the two load terminals and is configured to reduce the electrical resistance when a voltage between the two load terminals reaches a given threshold value.

Abstract: A system that drives multiple MOSFETs in parallel for direct current and alternating current solid state power controller applications may include networks connected to the gates of the MOSFETs to protect the MOSFETs from being damaged during high current interruption. For direct current applications, the system may include a switching protection and damping network and a gate drive balancing network. For alternating current applications, the system may include two switching protection and damping networks and a gate drive balancing network.

Abstract: In one embodiment, a circuit includes a resistance including first and second terminals. The first terminal of the resistance is coupled to ground. The circuit also includes a first switching element including first, second, and third terminals. The first terminal of the first switching element is coupled to an output of an integrated circuit and the second terminal of the first switching element is coupled to a voltage supply of the integrated circuit. Additionally, the circuit includes a second switching element including first, second, and third terminals. The first terminal of the second switching element is coupled to an enable input of the integrated circuit. Furthermore, the second terminal of the second switching element is coupled to the third terminal of the first switching element and to the second terminal of the resistance. Moreover, the third terminal of the second switching element is coupled to the ground.

Abstract: A method and system are disclosed for calibrating a mid-voltage node in an integrated circuit including an input-output circuit having charge-recycling stacked voltage domains including at least first and second voltage domains. In one embodiment, the method comprises transmitting data through the input-output circuit, including transmitting a first portion of the data across the first voltage domain, and transmitting a second portion of the data across the second voltage domain. The method further comprises measuring a specified characteristic of the data transmitted through the input-output circuit; and based on the measured specified characteristic, adjusting a voltage of said mid-voltage node to a defined value. The voltage of the mid-voltage node may be adjusted to accomplish a number of objectives, for example, to achieve a desired trade-off between power and performance, or so that the two voltage domains have the same performance.

Abstract: A digital circuit which can operate normally regardless of binary potentials of an input signal is provided. A semiconductor device comprising a correcting unit and one or a plurality of circuit elements, the correcting unit including a first capacitor, a second capacitor, a first switch, and a second switch, wherein the first electrode of the first capacitor is connected to an input terminal, the supply of a first potential to the second electrode of the first capacitor is controlled by the first switch, the supply of a second potential to the second electrode of the second capacitor is controlled by the second switch, and a potential of the second electrode of the first capacitor or a potential of the second electrode of the second capacitor is supplied to the one or the plurality of circuit elements.

Abstract: The present invention provides a power circuit, including a current-limiting chip, a current-limiting value setting circuit, and a baseband chip. A current setting port of the current-limiting chip is connected to a general-purpose input/output port of the baseband chip through the current-limiting value setting circuit. The general-purpose input/output port is configured to generate a first signal in a first time sequence period of timeslot transmitting of the baseband chip so that the current-limiting value setting circuit sets a current-limiting value of the current-limiting chip as a first current-limiting value. In the other time sequence periods of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a second signal so that the current-limiting value setting circuit sets the current-limiting value of the current-limiting chip as a second current-limiting value. The first current-limiting value is greater than the second current-limiting value.

Abstract: A semiconductor integrated circuit has an output terminal connected to an external load, an internal signal line by which the output terminal is connected to an internal node, and a voltage generator that outputs a voltage to the internal node, for output through the internal signal line and the output terminal to the external load. A voltage attenuating element is connected to the internal signal line to attenuate voltage swings on the internal signal line. A limiting circuit is connected to the internal node to limit the voltage at the internal node to a predetermined range. Moderate voltage swings caused by external electromagnetic interference are kept within the predetermined range by the voltage attenuating element, so that the limiting circuit does not operate and the average output voltage is not changed.

Abstract: A receiving circuit for a core circuit is provided and includes a first receiving-path unit. The first receiving-path unit is capable of receiving an input signal and outputting an output signal to the core circuit according to the input signal. The first receiving-path unit includes an input buffer which is capable of operating in a core power domain of the core circuit and receiving a first clamped signal. When a level of the input signal is substantially equal to or lower than a first predetermined voltage level, the input signal is passed to the input buffer to serve as the first clamped signal, and the input buffer is capable of outputting the output signal in the core power domain according to the first clamped signal. When the level of the input signal is higher than the first predetermined voltage level, the input signal is not passed to the input buffer.

Abstract: The present invention provides a power circuit, including a current-limiting chip, a current-limiting value setting circuit, and a baseband chip. A current setting port of the current-limiting chip is connected to a general-purpose input/output port of the baseband chip through the current-limiting value setting circuit. The general-purpose input/output port is configured to generate a first signal in a first time sequence period of timeslot transmitting of the baseband chip so that the current-limiting value setting circuit sets a current-limiting value of the current-limiting chip as a first current-limiting value. In the other time sequence periods of timeslot transmitting of the baseband chip, the general-purpose input/output port generates a second signal so that the current-limiting value setting circuit sets the current-limiting value of the current-limiting chip as a second current-limiting value. The first current-limiting value is greater than the second current-limiting value.

Abstract: A system adjusts a voltage swing of an output driver based on a supply voltage. A supply voltage monitor generates a digital code indicating the difference between the supply voltage and nominal voltage representing a preferred level for the supply voltage. An impedance controller sets the voltage swing for the output driver based on the digital code, thereby keeping the voltage swing of the output driver output signal within specified limits while maintaining an impedance match with a load coupled to the output driver.

Abstract: A P-channel MOS transistor MP1 is provided between an input voltage Vin and the low-voltage circuit. The cathode of a first zener diode Z1 is connected to a node between the input voltage Vin and the source of the P-channel MOS transistor MP1. The anode of the first zener diode Z1 is branched into two lines at a branch node N1, and one of the two lines is connected to a ground through a resistor R1. The other of the two lines is connected to the gate of the P-channel MOS transistor MP1. The cathode of a second zener diode Z2 is connected to a node between the low-voltage circuit and the drain of the P-channel MOS transistor MP1. The anode of the second zener diode Z2 is connected to a ground.

Abstract: Methods and apparatuses for programming a parameter value in an IC (e.g., any power electronic device, such as a controller of a power converter) are disclosed. The parameter can be selected/programmed by selecting a clamp using an external optional (selectively inserted) diode coupled to a multi-function programming terminal. In particular, a controller IC for a power converter can be externally programmed via one or more multiple function terminals during startup of the converter to select between two or more options using the external programming terminal(s). Once programming is complete, internal programming circuitry may be decoupled from the programming terminal and during normal operation the programming terminal may then be used for another function, such as a bypass (BP) terminal to provide a supply voltage to the IC or other required functionalities.

Abstract: There is disclosed a method of controlling an input to an envelope modulated power supply of an envelope tracking amplification stage, comprising: generating an envelope signal representing the envelope of a signal to be amplified; applying a shaping function to the envelope signal to generate a shaped envelope signal, including: clipping the shaped envelope signal at high input envelope values; and providing the shaped envelope signal as an input signal to the envelope modulated power supply.

Abstract: A circuit can compensate for intra pair skew or mode conversion in a channel by applying a second or corrective mode conversion effect that counters the channel's mode conversion. The circuit can process the common mode signal with a frequency dependent filter prior to injection back into the differential mode. The circuit can implement the reverse mode conversion with passive circuits using integrated resistors and metal oxide semiconductor (MOS) switches. In certain embodiments, such actions can proceed effectively without necessarily consuming active power.

Abstract: A load driver includes a switching element connected to a load, a constant current generator that generates a constant current, and a driver circuit that turns on the switching element for an on-period, which depends on a value of the constant current and is shortened with an increase in the value of the constant current. The constant current generator supplies a first constant current having a first current value to the driver circuit during the on-period, and supplies a second constant current having a second current value smaller than the first current value after the on-period has elapsed and the switching element reaches an on state.

Abstract: An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.

Abstract: Apparatus and methods for an integrated circuit, high-impedance network are provided. In an example, the network can include an anti-parallel diode pair coupled between first and second nodes. The anti-parallel diode pair can include a first diode including a P+/NWELL junction and a second diode including N+/PWELL junction. In an example, the first diode and the second diode can include a common substrate.

Abstract: A switch device comprised of a wide band gap semiconductor is provided. The switch device comprises a drain, a source, a gate and a gate voltage clamp circuit, which is connected between a signal terminal, to which a signal for driving the gate is input, and the gate through a series circuit of a capacitor and a resistance, and which comprises a diode and a voltage limiter circuit provided between the drain and the gate.

Abstract: A voltage clamping circuit for protecting an input/output (I/O) terminal of an integrated circuit from over shoot and under shoot voltages includes transistors connected to form a current conducting path. A voltage at the I/O pin is detected using a voltage detection circuit. The current conducting path is switched on when the voltage at the I/O pin exceeds a predetermined value.

Abstract: Conventional circuits often have undesirable characteristics to due “hot spots” or use a large amount of area. Here, however, a charging circuit is provides that uses an improved driver. Namely, an amplifier within a current sensor is used to control the rate that a switch can charge an external capacitor. This is accomplished through the adjustment of the gain of the amplifier during a charging mode.

Abstract: In various embodiments, applicants' teachings are related to an active guarding circuit and method for reducing parasitic impedance signal loading on a signal-transmission channel that is shunted by a parasitic impedance. The presence of an electrical signal on the signal-transmission channel causes a leakage current to flow through the parasitic impedance. In various embodiments, the circuit comprises an amplifier and an impedance, one terminal of the impedance is coupled to the signal-transmission channel. The input of the amplifier is coupled to the signal-transmission channel and the output is coupled to the other terminal of the impedance so as to cause a compensation current to flow through the impedance. The gain of the amplifier and the value of the impedance are selected so that the compensation current has a magnitude substantially equal to the leakage current magnitude.

Abstract: A low side clamp circuit has a control portion, a sense portion, and a clamp portion. When the sense portion detects that the input voltage of an output stage of a buffer has gone below a threshold voltage, it triggers the control portion to quickly turn on a clamp transistor (in the clamp portion) to clamp the output voltage to the clamp voltage. The control portion and sense portion have cross-coupled transistors that create increased speed and a sharp response with little or no voltage offset with a wide range of load currents. A clamp current source draws current through a resistor coupled in series between the base of the output transistor in the control portion and the collector of the output transistor in the sense portion. The clamp current is set to ClLo/R, where ClLo is the clamp voltage. A high side clamp is also described.

Abstract: Methods, devices and circuits are provided for protection from backdrive current. One such device is subject to back voltage from an output node of the device and includes circuitry that is configured to compare the supply voltage node and the output node. In response to the comparison, the circuitry generates an output signal. Level shifted versions of the output signal are used to provide an output voltage corresponding to the higher of a supply voltage node and an output node. Switches are used to place the device in different modes in response to the output signal.

Abstract: The present invention provides a voltage clamping circuit which is operated in a stable manner with the simple constitution and a switching power source device which enables a high-speed operation. In a switching power source device, one of source/drain routes is connected to an input terminal to which an input voltage is supplied, a predetermined voltage to be restricted is supplied to a gate, and using a MOSFET which provides a current source between another source/drain route and a ground potential of the circuit, a clamp output voltage which corresponds to the input voltage is obtained from another source/drain route. The switching power source device further includes a first switching element which controls a current which is made to flow in an inductor such that the output voltage assumes a predetermined voltage and a second switching element which clamps an reverse electromotive voltage generated in the inductor when the first switching element is turned off to a predetermined potential.

Abstract: The limiter circuit of this invention is a limiter circuit which, by switching action of a pair of transistors, allows passage of only signal voltage components of an input signal voltage included in ranges of an upper limit signal voltage and a lower limit signal voltage. With this construction, the pair of transistors carry out comparisons between the input signal voltage and threshold signal voltages and line switching at the same time. Therefore, there is no influence of propagation delay speed, and no switching noise occurs at times of line switching. Since diodes are not used, a high-speed limiter circuit can be manufactured.

Abstract: A system for processing an input signal, the system including: (a) a hardware memory module configured to store a lookup table; and (b) a signal processing module, configured to clip the input signal to provide a second signal that does not exceed a magnitude threshold, wherein the signal processing module is configured to clip the input signal by processing the input signal using at least one filtering parameter that is retrieved from the lookup table using at least one lookup table index which is selected in response to the input signal.

Abstract: An in-rush or out-rush current limiting circuit employs a low number of components to effect in-rush current limiting and may be employed in dongles or on-chip (in the case of serving as an out-rush current limiting circuit). The in-rush current limiting circuit may be employed, for example, in USB dongles, Display Port (DP) dongles, or any other suitable connector as desired. Alternatively, the circuit may be integrated onto a circuit board or within an integrated circuit as desired. Among other advantages, a lower cost, low complexity solution may be provided. In addition, bulk capacitance can be increased such as by employing a trickle resistor or other suitable limiting structure.

Abstract: A P-channel MOS transistor MP1 is provided between an input voltage Vin and the low-voltage circuit. The cathode of a first zener diode Z1 is connected to a node between the input voltage Vin and the source of the P-channel MOS transistor MP1. The anode of the first zener diode Z1 is branched into two lines at a branch node N1, and one of the two lines is connected to a ground through a resistor R1. The other of the two lines is connected to the gate of the P-channel MOS transistor MP1. The cathode of a second zener diode Z2 is connected to a node between the low-voltage circuit and the drain of the P-channel MOS transistor MP1. The anode of the second zener diode Z2 is connected to a ground.