Abstract: A conversion circuit includes a voltage supply circuit, a storage circuit, and a gate terminal. The storage circuit includes a first terminal and a source terminal. The voltage supply circuit is configured to provide a bias voltage according to a power supply voltage. The first terminal is configured to receive a low voltage. The source terminal is configured to output a source voltage according to a storage voltage and the low voltage, wherein the storage circuit is configured to storage the storage voltage according to the bias voltage and the low voltage. The gate terminal is configured to output a gate voltage, wherein during a first period, the gate terminal is coupled to the first terminal, and the gate-source voltage can form a negative voltage.

Abstract: An integrated photodetecting optoelectronic semiconductor component for detecting light bursts in a light signal received by the component includes a silicon photomultiplier for: measuring the intensity of the light signal received by the component, and outputting a measurement signal that is indicative of the light intensity of the received light signal. The component is characterised by a comparator circuit: having a first input section, a second input section and an output section, and operatively connected to the silicon photomultiplier via its first input section.

Abstract: Surge protection circuitry includes a pair of series connected diodes sharing a first common terminal that is directly electrically connected to only one of a pair of transmission lines, a pair of series connected Zener diodes, in parallel with the series connected diodes, sharing a second common terminal that is directly electrically connected to only the other of the transmission lines, and a pair of series connected power supplies each configured to reverse bias one of the series connected diodes such that the diodes prevent electrical coupling of the Zener diodes to the transmission lines responsive to a voltage of the signal source being less than a threshold value, and the diodes permit electrical coupling of at least one of the Zener diodes to the transmission lines responsive to the voltage being greater than the threshold value.

Abstract: A avalanche diode arrangement comprises an avalanche diode (11) that is coupled to a first voltage terminal (14) and to a first node (15), a latch comparator (12) with a first input (16) coupled to the first node (15), a second input (17) for receiving a reference voltage (VREF) and an enable input (21) for receiving a comparator enable signal (CLK), and a quenching circuit (13) coupled to the first node (15).

Abstract: Embodiments of a solid state photomultiplier are provided herein. In some embodiments, a solid state photomultiplier may include an epitaxial layer, a high voltage region formed in the epitaxial layer, a low voltage region formed in the epitaxial layer, and an intermediate region disposed between the high voltage region and low voltage region, wherein the high voltage region is electrically coupled to the low voltage region via the intermediate region, and wherein at least a portion of the epitaxial layer is disposed between the high voltage region and intermediate region and between the low voltage region and the intermediate region.

Abstract: According to an embodiment, a photodetector includes a plurality of photoelectric transducers, a plurality of resistors, and a plurality of resetting sections. Each of the photoelectric transducers is configured to output a detection signal resulting from conversion of received light into an electric charge. Each of the resistors is connected in series with an output end of a corresponding photoelectric transducer at one end of the resistor. Each of the resetting sections is connected in parallel with a corresponding resistor and configured to bring the output end of the corresponding photoelectric transducer to a reset level in response to the detection signal.

Abstract: An analog silicon photomultiplier system includes at least one analog pixel comprising a plurality of analog photodiodes (APDs), and a capacitor, a signal generator, a phase detector, and a compensation network. The signal generator is configured to generate and propagate a sinusoidal signal concurrently along first and second transmission lines. A capacitor is loaded on the first transmission line when an APD corresponding to the capacitor detects a photon. The phase detector is coupled with the first and second transmission lines, determines a phase difference between the first transmission line and the second transmission line and calculates a number of APDs that have fired from the phase difference. The compensation network is coupled with the second transmission line and the phase detector, and comprises a plurality of compensation capacitors, wherein the compensation capacitors are loaded on the second transmission line in proportion to the number of APDs that have fired.

Abstract: The present invention relates to a circuit arrangement having the following features: a load transistor having a control connection and a first and second load connection; a drive connection coupled to the control connection of the load transistor and serving for the application of a drive signal; a voltage limiting circuit connected between one of the load connections and the drive connection of the transistor; and a deactivation circuit connected to the voltage limiting circuit and serving for the deactivation of the voltage limiting circuit in a manner dependent on a deactivation signal, which is dependent on a load current through the load transistor and/or on a drive voltage of the load transistor.

Abstract: A P-channel MOS transistor MP1 is provided between an input voltage Vin and the low-voltage circuit. The cathode of a first zener diode Z1 is connected to a node between the input voltage Vin and the source of the P-channel MOS transistor MP1. The anode of the first zener diode Z1 is branched into two lines at a branch node N1, and one of the two lines is connected to a ground through a resistor R1. The other of the two lines is connected to the gate of the P-channel MOS transistor MP1. The cathode of a second zener diode Z2 is connected to a node between the low-voltage circuit and the drain of the P-channel MOS transistor MP1. The anode of the second zener diode Z2 is connected to a ground.

Abstract: Disclosed are a system, a method and an apparatus of reduction of delay between subsequent capture operations of a light-detection device. In one embodiment, a light-detection circuit includes an avalanche photodiode implemented in a deep submicron CMOS technology. In addition, the light-detection circuit includes a passive quench control circuit to create an avalanche current that generates a high voltage at an output of a second inverter gate of the circuit. The light-detection circuit further includes an active quench control circuit to reduce a dead time of the circuit. The light-detection circuit also includes a reset circuit to create a low voltage at an output of the second inverter gate and to create an active reset through a PMOS transistor of the light-detection circuit.

Abstract: A power unit (e.g., inverter module) includes a housing and a switch attached to the housing. The switch may be configured to be electrically coupled to a remotely-mounted drive circuit through two or more wire leads. The power unit also includes a clamping circuit electrically coupled to terminals of the switch and in parallel with the switch. The clamping circuit may be disposed inside the housing or on an outer surface of the housing, and is configured to limit a voltage across the switch.

Abstract: Disclosed are a system, a method and an apparatus of reduction of delay between subsequent capture operations of a light-detection device. In one embodiment, a light-detection circuit includes an avalanche photodiode implemented in a deep submicron CMOS technology. In addition, the light-detection circuit includes a passive quench control circuit to create an avalanche current that generates a high voltage at an output of a second inverter gate of the circuit. The light-detection circuit further includes an active quench control circuit to reduce a dead time of the circuit. The light-detection circuit also includes a reset circuit to create a low voltage at an output of the second inverter gate and to create an active reset through a PMOS transistor of the light-detection circuit.

Abstract: A driver circuit includes an output transistor circuit that includes a first transistor of a first conductivity type and a second transistor of a second conductivity type disposed between a supply voltage source and a reference voltage source, and that outputs an output signal from a connection node between the first transistor and the second transistor, a first pre-buffer circuit that drives a gate of the first transistor in response to an input signal, and a second pre-buffer circuit that drives a gate of the second transistor in response to the input signal.

Abstract: A drive circuit includes a transformer T1 having a primary winding N1 to which a drive signal P1 is applied and a first secondary winding N2, a first switching element Q1, a first capacitor C3 connected between a first end of the first secondary winding of the transformer and a control terminal of the first switching element, and a first series circuit including a first zener diode ZN1 and a second zener diode ZN2, a cathode of the first zener diode being connected to a connection point of the first capacitor and first switching element, a cathode of the second zener diode being connected to a second end of the first secondary winding.

Abstract: The present invention is a high voltage semiconductor switch that is formed from a chain of series coupled cascode circuits. In one embodiment, the switch may be a single-throw configuration coupled between an output and a direct current (DC) reference. In an alternate embodiment, the switch may be a double-throw configuration such that the output is switched between either a first DC reference or a second DC reference, such as ground. Each cascode circuit may have clamp circuits to prevent over voltage during switching transitions. The series coupled cascode circuits may be formed using discrete components or on a silicon-on-insulator (SOI) wafer, which may have a Silicon Dioxide insulator layer or a Sapphire insulator layer.

Abstract: A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a condition state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.

Abstract: In order to transfer data at high speed over a long distance, a current mode logic output circuit (CML) having a large number of taps, high accuracy, and a wide switchable range of the amount of pre-emphasis is needed. However, when the amount of emphasis is set by adding unit source-coupled pair circuits, a problem will arise that the output capacitance of the current mode logic output circuit would increase, thus hampering high-speed transmission. An output circuit of the invention is constructed from unit source-coupled pair circuits 501, which are obtained by dividing a current mode logic output circuit (CML) into m groups, terminal resistors 502, and a data selector 504. The amount of emphasis of each tap is determined by the ratio of the number of unit source-coupled pair circuits, which have been obtained by dividing the CML into m groups, allocated to each tap. Thus, the amount of emphasis can be set to be any arbitrary amount without a change in the output amplitude of 1.

Abstract: A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a condition state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.

Abstract: A pass transistor signal level translator between a first voltage level and a higher second voltage level having a bias circuit for the pass transistor including a first switching circuit coupled to the first voltage level for providing a bias voltage that is less than the first voltage level. A second switching circuit is coupled to the second voltage level for providing a pulse at substantially the second voltage to the bias voltage. A voltage clamping circuit is coupled between the bias voltage and a reference voltage.

Abstract: A method and apparatus for providing non-linear, passive quenching of avalanche currents in Geiger-mode avalanche photodiodes (APDs) is provided. A non-linear, passive, current-limiting device is connected in series with the APD and a bias source. The non-linear, passive, current-limiting device rapidly quenches avalanche currents generated by the APD in response to an input photon and resets the APD for detecting additional photons, using a minimal number of components. The non-linear, passive, current-limiting device could comprise a field-effect transistor (FET), as well as a junction FET (JFET) a metal-oxide semiconductor FET (MOSFET), or a current-limiting diode (CLD) connected in series with the APD and the bias source.

Abstract: A high voltage gate driver circuit according to an embodiment of the present invention controls an operational range of an output signal of a level shifter to be appropriate for an operational range of a reshaper through a VIV converter. Even though the voltage range of the signal which is input from the high voltage gate driver circuit to the level shifter is different from the operational range of the reshaper, the input signal can always be recognized exactly regardless of the VTH voltage of the reshaper by controlling the operational range of the signal through the VIV converter. In addition, incorrect operation of the circuit can be prevented by erasing a common mode noise which is input with the input signal.

Abstract: A double quench circuit for an avalanche current device is provided in which the circuit includes an avalanche current device having a first terminal responsive to a bias voltage to reverse bias the avalanche current device above its avalanche breakdown voltage. A first quench circuit is responsive to the bias voltage and coupled to the first terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device. A second quench circuit is coupled to a second terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device.

Abstract: A method and apparatus for providing non-linear, passive quenching of avalanche currents in Geiger-mode avalanche photodiodes (APDs) is provided. A non-linear, passive, current-limiting device is connected in series with the APD and a bias source. The non-linear, passive, current-limiting device rapidly quenches avalanche currents generated by the APD in response to an input photon and resets the APD for detecting additional photons, using a minimal number of components. The non-linear, passive, current-limiting device could comprise a field-effect transistor (FET), as well as a junction FET (JFET) a metal-oxide semiconductor FET (MOSFET), or a current-limiting diode (CLD) connected in series with the APD and the bias source.

Abstract: The present invention provides a system for producing high voltage, low power driver circuitry (300) that addresses a number of disparate design requirements. The present invention provides circuitry comprising a voltage supply (308) and an output node (302). A transistor (304) is provided. A first resistive element (312) is coupled to the voltage supply, while a second resistive element (314)—having a resistance value equal to that of the first resistive element—is coupled between a second terminal of the transistor and the output node. A first diode (310) is coupled to the first resistive element and to a first terminal of the transistor. A clamping system (316) is coupled to the transistor, and a current limiting system (318) is coupled to the clamping system.

Abstract: A cable detection apparatus is disclosed having a filter, the filter transmitting components of a signal detected substantially at certain harmonics of a first frequency. The filter may also attenuate the signal at certain even harmonics thereof. A method of detecting and/or locating cables in the same manner is also disclosed.

Abstract: An integrated circuit having a voltage generator supplying a determined voltage, a voltage-limiting circuit arranged at the output of the voltage generator, the voltage-limiting circuit having at least one PN junction formed by a diode-arranged MOS transistor, the PN junction having a breakdown voltage defining a threshold for triggering the voltage-limiting circuit as from which the PN junction is on by avalanche effect, at least one load in series with the PN junction for limiting an avalanche current passing through the PN junction when the PN junction is on, and at least one switch in parallel with the PN junction and the load, the switch arranged in the open state when the PN junction is off and to be in the closed state when the PN junction is on.

Abstract: A protection circuit 10 has a diode 31 being connected in parallel to an inductive load 11 and having a forward direction set reverse to the conduction direction of a power supply current and a Zener diode 33 being placed between one terminal of the diode 31 and one terminal of the load 11 corresponding to the terminal of the diode and having a forward direction matched with the conduction direction of the power supply current.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: A protection circuit 10 has a diode 31 being connected in parallel to an inductive load 11 and having a forward direction set reverse to the conduction direction of a power supply current and a Zener diode 33 being placed between one terminal of the diode 31 and one terminal of the load 11 corresponding to the terminal of the diode and having a forward direction matched with the conduction direction of the power supply current.

Abstract: Voltage level translators are presented, inter alia, for operating an operational amplifier integrated circuit designed for operation with a single ended power supply, to operate with a split level power supply having a center tapped ground. A first polarity power supply terminal of a operational amplifier integrated circuit is coupled to a first polarity of the of the split level power supply, and a second polarity power supply terminal of the operational amplifier integrated circuit is coupled to a second polarity of the power supply, with a positive signal input terminal of the operational amplifier being coupled to a center tapped ground of the split level power supply.

Abstract: An integrated circuit is disclosed in which a steering diode is coupled between an input bond pad and a ground bond pad. The steering diode is reverse biased when a voltage applied to the input bond pad exceeds the voltage at the ground bond pad. A circuit coupled between the input bond pad and the ground bond pad includes a transistor having a first electrode coupled the input bond pad and a second electrode coupled to the ground bond pad. There may be other circuit elements between the emitter and the ground bond pad. At least two series coupled diodes are coupled between the input bond pad and the ground bond pad. The at least two series coupled diodes provide ESD protection to the transistor and circuit coupled between the input bond pad and the ground bond pad.

Abstract: A regenerative tie-high, tie-low cell (circuit) that provides unconditionally stable logic (1 and 0) output states used to tie off logic inputs. The circuit of this invention eliminates any current flow through p-channel/n-channel transistor pairs found in many conventional circuits and adds a regenerative transistor 42 to assure rapid response in achieving the proper logic output states. In one preferred embodiment, the circuit consists of only three CMOS transistors 40-42 that reduce the silicon area required, lowers the cost, and improves the overall reliability.

Abstract: A structure for protection against electrostatic surges having two input terminals and two output terminals. The output terminals of the structure are connected to the inputs of a circuit to be protected. A first input terminal is connected to a first output terminal via an impedance. The second input terminal is connected to the second output terminal. The input terminals are interconnected by a first avalanche diode. The output terminals are interconnected by a second avalanche diode having the same biasing as the first avalanche diode.

Abstract: A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply.

Abstract: A variable transconductance current mirror circuit includes a first field effect transistor having a gate, a source, and a drain, and a second field effect transistor having a gate, a source, and a drain. The gate of the second transistor is coupled to the gate of the first transistor, and a current source is coupled to the gates of the first and second transistors. The circuit also includes a voltage supply coupled to the sources of the first and second transistors. The circuit further includes a first diode having an anode and a cathode. The anode of the first diode is coupled to the gates of the first and second transistors, and the cathode of the first diode is coupled to the source of the first and second transistors. The first diode comprises a zener diode having a reverse breakdown voltage operable to prevent gate oxide breakdown of the first and second transistors.

Abstract: In combination with a transistor designed to drive an inductive load, there is included a network connected between the output electrode (e.g., drain) and the control electrode (e.g., gate) of the transistor for limiting the overshoot and controlling the waveshape of the signal produced at the output electrode of the transistor, when the transistor is being turned-off. The network includes a series string of zener diodes with one or more by-pass capacitors connected across the zener diodes closest to the control electrode of the transistor for shaping the output signal produced at the output electrode of the transistor and for reducing electromagnetic radiation. The network also includes unidirectional conducting elements for discharging each bypass capacitor each time the transistor is turned-on. The zener diodes and the "discharging" unidirectional conducting elements of the network may be formed as integral parts of the same integrated circuit (IC).

Abstract: A circuit configuration for protecting a MOSFET against overvoltages, includes at least one diode connected in the blocking direction between a drain terminal and a gate terminal of the MOSFET to be protected. A series connection of a load path of a further MOSFET and a further Zener diode connected in the blocking direction, is connected between the at least one Zener diode and the gate terminal of the MOSFET to be protected. A cathode of the further Zener diode is connected to a gate terminal of the further MOSFET.

Abstract: An active quench circuit for an avalanche current device applies a bias voltage to reverse bias an avalanche current device above its avalanche breakdown voltage; a current amplifier circuit having a turn-off speed slower than the avalanche speed of the avalanche device and responsive to the avalanche current of the avalanche device generates an overshoot current continuing after the end of the avalanche current; and a feedback circuit responsive to the overshoot current generates a quenching voltage for reducing the bias voltage below the avalanche breakdown voltage to quench the avalanche current of the avalanche device.

Abstract: A network is connected between the drain and gate of a transistor for limiting the overshoot and controlling the waveshape of the signal produced at the drain of the transistor, when the transistor is being turned-off. The network includes a series string of zener diodes with one or more by-pass capacitors connected across one or more zener diodes for shaping the output signal produced at the drain of the transistor and for reducing electromagnetic radiation. The network also includes unidirectional conducting elements for discharging each bypass capacitor each time the transistor is turned-on. The zener diodes and the "discharging" unidirectional conducting elements of the network may be formed as integral parts of the same integrated circuit (IC). For best results, the bypass capacitors are connected across the zener diodes closest to the gate of the transistor.

Abstract: An injector control circuit for a motor vehicle electronic injection system utilizing current recirculation to control an injector actuation winding provided with a circuit configuration containing a constant current generator operable to eliminate the problems of instability and sensitivity to supply line interruptions to which prior art control circuits are subject.

Abstract: A dV/dt clamp circuit is connected to a base of a phototransistor for triggering a control electrode of a thyristor, thereby making an attempt to prevent an operation error. A control electrode voltage of the thyristor is applied to the gate of the MOSFET via a high breakdown voltage capacitor. The gate electrode voltage of the MOSFET can be continuously held at a threshold value or more by adjusting a zener voltage of a zener diode and a resistance value of a resistor. Since with a high dV/dt the MOSFET can be operated at a high speed to allow conduction between the drain and source of the MOSFET, the phototransistor does not trigger the thyristor, thereby preventing an operation error.

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: A clamp circuit (50) for protecting a MOSFET (52) from destructive voltages includes a clamping element (56), a Zener diode (64), two current mirrors (66 and 62), a current switch (58), a reference current source (68), and a voltage detector (72). When a drain voltage of the MOSFET (52) rises above a clamping voltage of the clamp circuit (50), a clamping current exceeding a current in the current switch (58) flows through the clamping element (56) and activates the MOSFET (52). During the activation, the two current mirrors (66 and 62) generate an output current exceeding a reference current in the reference current source (68) and raise a voltage at an input terminal of the voltage detector (72). The voltage detector (72) generates a signal indicating the activation of the clamp circuit (50), thereby indicating that the clamp circuit (50) and its inductive load (74) are intact.

Abstract: A snubbing clamp network (14) is disclosed which comprises a gate voltage clamp (16) having an input and an output, the output connected to a first node, a gate-source voltage clamp (18) having an input connected to the first node and an output connected to the second node, and voltage reference (20) having an output connected to the input of the gate voltage clamp (16).

Abstract: An A/D circuit to convert an analog signal to a digital signal. The circuit includes a low noise analog-to-digital conversion chip and a precision voltage reference source. The voltage reference source includes a diode with two terminals and a passive attenuation circuit. The attenuation circuit and the diode are coupled in parallel between the two terminals to provide a voltage reference signal for use by the analog to digital conversion chip. The analog to digital chip uses the voltage reference signal to set the full scale input range for the signal conversion, and the voltage reference signal is attenuated to correspond to the full scale range of the analog signal. The A/D converter circuit has a passive temperature compensation feature to substantially eliminate or reduce the effects of thermal drift and of operating at different temperatures.