Abstract: A power supply control device that includes a controller configured to switch on and off a first semiconductor switch and a plurality of second semiconductor switches whose current input terminals are connected to a current output terminal of the first semiconductor switch, the controller being configured to control supply of power via the plurality of second semiconductor switches by switching; a first parasitic diode connected between a current input terminal and the current output terminal of the first semiconductor switch; and a plurality of second parasitic diodes that are respectively connected between the current input terminals and current output terminals of the plurality of second semiconductor switches.

Abstract: Overcurrent circuits are disclosed for preventing overcurrent in shielded coaxial communication cables. A shield breaking element of an overcurrent circuit is adaptable to be coupled in series with a shield conductor of a shielded coaxial cable, and is also configured to open upon conducting a first electrical current that exceeds an overcurrent threshold, thereby preventing the first electrical current from flowing through the shield conductor of a shielded coaxial cable. A signal breaking element of the overcurrent circuit is adaptable to be coupled in series with a signal conductor of the shielded coaxial cable, and is configured to open when the shield breaking element opens thereby preventing a second electrical current from flowing through the signal conductor. Systems and devices that use the overcurrent circuits, for example, to provide alerts and status, are also disclosed.

Abstract: A non-magnetic material frequency selective limiter circuit has first and second resonators and a non-linear coupling component. The first resonator oscillates at a fundamental frequency. The second resonator oscillates at one half of the fundamental frequency. The non-linear coupling component non-linearly and parametrically couples the first resonator and the second resonator. The first resonator, second resonator and the non-linear coupling component are arranged so as to reduce the amplitude of an output signal for an input signal of frequency ? when an input signal amplitude is above a voltage threshold value, by converting part of the input signal to a signal at the frequency ?/2. The first resonator, second resonator and the non-linear coupling component are formed of non-magnetic materials.

Abstract: Disclosed is an apparatus for protecting an analog input module from overvoltage, the apparatus including an analog input module and a stabilization unit. The analog input module converts one of a plurality of positive/negative analog signals inputted from the outside thereof into a digital signal and insulates the converted digital signal. The stabilization unit supplies voltages of the positive/negative analog signals to the analog input module when the voltage levels of the plurality of positive/negative analog signals are higher than the levels of positive/negative operating voltages in the analog input module.

Abstract: According to one embodiment, a semiconductor device has a transistor comprising a source electrode, a drain electrode, and a gate electrode, a diode and a switch element connected in series between the gate and source electrodes of the transistor, and a control circuit configured to supply a control signal for switching the switch element. The control circuit has a predetermined time constant and is configured to supply the control signal to the switch element if a pulse signal having a voltage that is equal to or higher than a predetermined voltage is supplied to the gate electrode of the transistor.

Abstract: Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode.

Abstract: The present invention relates to a circuit arrangement having the following features: a load transistor having a control connection and a first and second load connection; a drive connection coupled to the control connection of the load transistor and serving for the application of a drive signal; a voltage limiting circuit connected between one of the load connections and the drive connection of the transistor; and a deactivation circuit connected to the voltage limiting circuit and serving for the deactivation of the voltage limiting circuit in a manner dependent on a deactivation signal, which is dependent on a load current through the load transistor and/or on a drive voltage of the load transistor.

Abstract: A device for use with an RF generating source, a first electrode, a second electrode and an element. The RF generating source is operable to provide an RF signal to the first electrode and thereby create a potential between the first electrode and the second electrode. The device comprises a connecting portion and a current sink. The connecting portion is operable to electrically connect to one of the first electrode, the second electrode and an element. The current sink is in electrical connection with the connection portion and a path to ground. The current sink comprises a voltage threshold. The current sink is operable to conduct current from the connecting portion to ground when a voltage on the electrically connected one of the first electrode, the second electrode and the element is greater than the voltage threshold.

Abstract: This document discusses, among other things, a system and method for offsetting reverse-bias leakage of a high impedance bias network. In an example, an apparatus includes an anti-parallel diode pair coupled between a signal node and a common-mode node. The anti-parallel diode pair can include a first diode and a second diode coupled to the first diode. A third diode can be coupled between a supply node and the signal node, and the third diode can be sized to compensate for a parasitic diode junction of the anti-parallel diode pair.

Abstract: Disclosed is an apparatus for protecting an analog input module from overvoltage, the apparatus including an analog input module and a stabilization unit. The analog input module converts one of a plurality of positive/negative analog signals inputted from the outside thereof into a digital signal and insulates the converted digital signal. The stabilization unit supplies voltages of the positive/negative analog signals to the analog input module when the voltage levels of the plurality of positive/negative analog signals are higher than the levels of positive/negative operating voltages in the analog input module.

Abstract: A signal level crossing detector circuit includes a DC isolator and a detector circuit. The DC isolator has at least a first input, which is operable to receive a high voltage AC signal, and at least a first capacitor, a first plate of the first capacitor being electrically connected to the first input. The detector circuit is operable at a low voltage and has at least a first detector input, the first detector input being electrically connected to a second plate of the first capacitor, the low voltage detector circuit being operable to provide a change in output signal in dependence on a high voltage AC signal on the first input crossing a predetermined signal level. The signal level crossing detector may be single ended or differential.

Abstract: An ECU serving as a transmission side and an ECU serving as a reception side are coupled to each other through communication lines and junction connectors. A diode in which a direction directed from a negative-side output terminal of the ECU serving as the transmission side to a positive-side output terminal thereof becomes a forward direction is provided between the positive-side output terminal and the negative-side output terminal.

Abstract: A load drive circuit which can operate at high speed with low consumption current while performing the gate-to-source over voltage protection for its load driving field-effect transistor. A Zener function device is connected between the gate and the source of the load driving field-effect transistor, and an on/off-switch circuit to supply either on-potential or off-potential to the gate of the field effect transistor is provided. The current flowing through the Zener function device when the load driving field-effect transistor is conductive is limited by the on/off-switch circuit.

Abstract: A semiconductor power device includes a circuit to provide a gate signal wherein the gate signal has a negative temperature coefficient of gate driving voltage for decreasing a gate driving voltage with an increase temperature whereby the semiconductor power device has a net Ids temperature coefficient that is less than or equal to zero. In an exemplary embodiment, the gate voltage driver includes a diode that has a negative forward voltage temperature coefficient connected between a gate and a source of the semiconductor power device. In another embodiment, the gate voltage is integrated with the semiconductor power device manufactured as part of an integrated circuit with the semiconductor power device.

Abstract: A voltage converter includes a first N-channel MOSFET transistor, an inverter, a plurality of serially-connected diodes and a second N-channel MOSFET transistor. The inverter is coupled to the gate of the first N-channel MOSFET transistor to turn on/off the voltage converter. The anode of the diodes is coupled to the source of the first N-channel MOSFET transistor and the cathode of the diodes are coupled to the drain of the second N-channel MOSFET transistor. Since the source of the second N-channel MOSFET transistor is ground, the voltage clamped at the source of the first N-channel MOSFET transistor is not higher than 3.4V when a high voltage applied to the gate of the second N-channel MOSFET transistor turns it on.

Abstract: An active diode including a NMOS transistor having a source terminal, a drain terminal, a gate terminal and a back gate terminal, where the source terminal is connected to the back gate terminal and forms the anode terminal of the active diode, and the drain terminal forms the cathode terminal of the active diode. The active diode further includes an offset bias voltage source having a first terminal and a second terminal; and an amplifier having a non-inverting input terminal and an inverting input terminal, and an output terminal, where the inverting input terminal is connected to the drain terminal of the transistor, the non-inverting input terminal is connected to the first terminal of the offset bias source, the output terminal is connected to the gate terminal of the transistor, and the second terminal of the offset bias source is connected to the source terminal of the transistor.

Abstract: Diode network configurations are disclosed in which cathode bias voltage is held substantially constant to provide an attenuator circuit in which return loss is optimized throughout a broad dynamic attenuation range. Preferred embodiments include PIN diodes arranged in a ? network having two attenuation control signals provided thereto. Alternative embodiments include PIN diodes arranged in a T network having two attenuation control signals provided thereto.

Abstract: Power supply voltages are selectively modulated to correspond with degraded input voltages to a logic device. Modulated power supply voltages are provided to transistors within the logic device, so that the degraded input voltages supplied to the transistors are sufficient to turn the transistors substantially on or off. Leakage currents are prevented thereby from flowing across the transistors.

Abstract: A clamping circuit (10) including an input/output node (12), adapted to be coupled to the protected circuit or component; a first diode (D1) having an anode connected to the input/output node (12); a second diode (D2) having a cathode connected to the input/output node (12); a third diode (D3) connected between the cathode of the first diode (D1) at a first node (14) and the anode of the second diode (D2) at a second node (16); a first arrangement for supplying a first potential at the cathode of the first diode at first node (14); a second arrangement for supplying a second potential at the anode of the second diode at second node (16); a first capacitor (C1) connected between the cathode of the first diode at first node (14) and ground; and a second capacitor connected between the anode of the second diode at second node (16) and ground.

Abstract: A two terminal semiconductor circuit that can be used to replace the semiconductor diodes used as rectifiers in conventional DC power supply circuits. Three semiconductor circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. All three circuits have a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode.

Abstract: A protection circuit 10 has a diode 31 being connected in parallel to an inductive load 11 and having a forward direction set reverse to the conduction direction of a power supply current and a Zener diode 33 being placed between one terminal of the diode 31 and one terminal of the load 11 corresponding to the terminal of the diode and having a forward direction matched with the conduction direction of the power supply current.

Abstract: In a high frequency power amplifier module of a multi-stage structure in which a plurality of heterojunction bipolar transistors (npn-type HBTs) are cascade-connected, a protection circuit in which a plurality of pn junction diodes are connected in series is connected between the collector and emitter of each HBT. The p-side is connected to the collector side, and the n-side is connected to the emitter side. A protection circuit in which pn junction diodes of the number equal to or smaller than that of the pn junction diodes are connected in series is connected between the base and the emitter. The p-side is connected to the base side, and the n-side is connected to the emitter side. With the configuration, in the case where an overvoltage is applied across the collector and emitter due to a fluctuation in load on the antenna side, the collector terminal is clamped by an ON-state voltage of the protection circuits, so that the HBT can be prevented from being destroyed.

Abstract: In a half-wave or multi-path RF diode-rectifier circuit having at least one rectifier diode and at least one output-side charging capacitor, the output is loaded with a non-linear load resistance having approximately the same relative temperature coefficient as the video resistance at zero bias of the rectifier diode and being non-linear, so that linearization of the relationship between output voltage and the square of input voltage is carried out beyond the square-law range.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: A two terminal semiconductor circuit that can be used to replace the semiconductor diodes used as rectifiers in conventional DC power supply circuits. Three semiconductor circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. All three circuits have a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode. In a first configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is utilized as a two terminal device by connecting together the gate and source leads. The terminal voltage in the conducting state is considerably smaller than conventional semiconductor diodes. In a second configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is connected with a transformer such that the source and the drain serve as the two leads of a two terminal circuit.

Abstract: An I/O ESD protection circuit is provided utilizing a driver circuit, an ESD protection circuit, a Vcc/Vss protection circuit, and a clamping circuit. The driver circuit and the ESD protection circuit each comprise a NMOS cascode circuit. NMOS transistors and biasing resistive means comprise the Vcc/Vss protection circuit. The clamping circuit is a diode coupled between the I/O pad of the protection circuit and the gate of that NMOS transistor. In an ESD event the diode turns on the NMOS transistor of the Vcc/Vss protection circuit , thus clamping off the first transistor of both NMOS cascode circuits. The clamping inhibits the gate of those first two transistors to be coupled up by an ESD voltage and creates a parasitic bipolar transistor in each cascode circuit. The parasitic bipolar transistors provide a uniform current flow in the buried area of the P-well of both NMOS cascode circuits.

Abstract: A semiconductor device that operates at high speed using a low voltage power source, in which the output of each gate in the standby state is stable, and which has a delay time that is not affected by the frequency of the input signal. TrQ1 to TrQ8, which form multiple stages of the inverters are designed to have a low threshold voltage in order to accomplish low voltage operation. When input node A is at “L” in the standby state, TrQ2, Q3, Q6, and Q8 which cut-off are connected to high threshold voltage TrQn1 and Qp1. In the standby state, power cutting TrQn1 and Qp1 cut off in accordance with chip selecting signals CS, /CS, thereby blocking the flow of sub-threshold current to TrQ1˜Q8. Since TrQ1, Q4, Q5 and Q8 are not cut off at this time, the output potential of each inverter is stable.

Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.

Abstract: Accuracy of correction of offset drift with temperature and noise are corrected in a high voltage, high current amplifier is improved by thermal isolation and/or temperature regulation of another amplifier having greater gain and connected to a different power supply in a closed loop feedback servo system. A clamping network connected to the higher gain amplifier to avoid hard saturation due to transient feedback signals from a reactive load, especially an inductive load, also prevents hard saturation of the high voltage, high current amplifier. An adjustable feedback circuit connected to the higher gain amplifier allows adjustment to obtain critical damping of a second order system and faster response to achieve proportionality of output current to input voltage with an accuracy of very few parts per million error and with minimum settling time.

Abstract: A protection circuit for a load dump condition employs a voltage division circuit to reduce the voltage applied to the system under test so that the peak applied voltage is reduced to permit the use of a lower voltage rating for power MOSFETs in the system under test. The voltage division circuit employs a resistor and switch in which the switch is closed at voltages higher than a given value at the terminals of the system under test; and is opened when the applied voltage reduces below the given value.

Abstract: A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages. The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock. Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages. Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge. The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal. Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode. In a method of use, a first stepped voltage is developed on a first capacitor and selectively coupled to a second capacitor to develop a second stepped voltage of greater absolute value.

Abstract: The present invention relates to a circuit for controlling waveform distortion resulting from nonlinearity of the impedance of a control terminal (gate or base) capacitance of a transistor, which can be employed in circuits showing a nonlinearity performance of high frequency amplifier or oscillator. According to the circuit of the invention, the waveform distortion can be properly controlled to improve the efficiency of power conversion in a high frequency circuit employing FET, regardless of the frequency band, while assuring a favorable matching of input for the circuit. Also, it can provide the reliability of an integrated circuit by employing outside voltage control circuit. Moreover, it can be fabricated on a wafer substrate of FET circuit with an inexpensive cost, which affords unrestricted designing of the circuit.

Abstract: A diode circuit of the present invention comprise an input/output terminal connected to the transmission line, a power supply terminal connected to the power supply, a plurality of diodes connected in series between the input/output terminal and the power supply terminal and a capacitive element having one end connected to a connected point of the plurality of diodes and the other end connected to the ground. In the input/output terminal, an applied signal from the transmission line exceeds the predetermined potential, it is clamped to the predetermined potential by the plurality of diodes connected in series. At the connecting points among a plurality of diodes and the input/output terminal, vibration of potential is reduced by the capacitance element.

Abstract: A high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called “dual-gate” or “thick-oxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.

Abstract: A back bias voltage level detector is capable of accurately detecting a back bias voltage level by constantly maintaining a voltage inputted into a comparator using a clamp circuit or a current mirror circuit. The back bias voltage level detector includes voltage control circuitry for accurately detecting the back bias voltage and maintaining a constant input voltage to the comparator, and first and second resistors coupled in series between an electric voltage and a back bias voltage for distributing voltage inputted thereto. A comparator compares the distributed and inputted voltage with a reference voltage. A back bias voltage detector is provided for outputting a detection signal by determining that a predetermined back bias voltage is detected when the input voltage and the reference voltage are identical as a result of the comparison.

Abstract: Provided is a protection circuit for high speed signal communication via a two-wire connection between the two output terminals of a PECL driver and the two input terminals of a PECL receiver. The PECL driver and receiver are supplied with power from individual power supplies. The protection circuit includes two diodes connected in series with a respective wire with their cathodes electrically coupled to the respective output terminal of the PECL driver and their anodes electrically coupled to the respective input terminal of the PECL receiver, and two resistors connected between the PECL receiver power supply and the anodes of the respective diode. The resistance of the resistors ensures forward biasing of the diodes when the receiver power supply is supplying power. A capacitor may be connected in parallel with the respective diodes.

Abstract: The present invention relates to a variable power-attenuation circuit whose attenuation is controlled electronically by a control voltage (Vc). This circuit includes resistive elements (R20, R21, D20, D21) of which at least two resistive elements are diodes (D20, D21), and a biasing device intended to set the direct current passing through the diodes. This circuit is characterized in that the biasing device includes means for independently setting the characteristic impedance of the circuit, the size of the dynamic range of the control voltage (Vc) and the position of the said dynamic range.Application to the production of transmission devices for directional radio.

Abstract: A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages. The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock. Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages. Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge. The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal. Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode. In a method of use, a first stepped voltage is developed on a first capacitor and selectively coupled to a second capacitor to develop a second stepped voltage of greater absolute value.

Abstract: A circuit and apparatus for generating a light pulse from an inexpensive light-emitting diode (LED) for an accurate distance measurement and ranging instrument comprises an LED and a firing circuit. An optional pre-biasing circuit provides a reverse-bias signal to the LED to ensure the LED does not begin to emit light before a firing circuit can provide a sufficiently high current pulse of short duration as a forward current through the LED. The LED is driven by the firing circuit with a pulse of high peak power and short duration. The resulting light pulse from the LED can be inexpensively used to derive distance and ranging information for use in a distance measurement and ranging device.

Abstract: Electro-static-discharge (ESD) protection circuits are supplied for inhibiting the destruction of buffers, drivers, logic and memory cells in Metal-Oxide-Semiconductor (MOS) devices such as a CMOS device including Static-Random-Access-Memory (SRAM). This is accomplished by tiering diodes adjacent the input of the chip and in certain specific areas internally of the chip (e.g. power supplies etc.) providing bidirectional diode protection from over-voltage.

Abstract: Electro-static-discharge (ESD) protection circuits are supplied for inhibiting the destruction of buffers, drivers, logic and memory cells in Metal-Oxide-Semiconductor (MOS) devices such as a CMOS device including Static-Random-Access-Memory (SRAM). This is accomplished by tiering diodes adjacent the input of the chip and in certain specific areas internally of the chip (e.g. power supplies etc.) providing bidirectional diode protection from over-voltage.

Abstract: A semiconductor amplifier circuit receiving a high frequency signal and amplifying and outputting the signal includes a transistor for receiving the high frequency signal; and a waveform control connected to an input terminal of the transistor and controlling a negative value of the high frequency signal to be less than the gate breakdown voltage of the transistor and not below a negative threshold voltage. Therefore, a low distortion characteristic is available even when a transistor with a large magnitude of the gate breakdown voltage is manufactured. As a result, accuracy in controlling the value of the gate breakdown voltage during manufacturing is not required to be as high as in conventional manufacturing, resulting in a lower processing cost as well as improved yield.

Abstract: In order to provide a differential ECL wherein the malfunction resulting from the constant current source being cut off from the power supply is prevented and wherein the output logic is determined on one side even when input terminals thereof are left open, a differential ECL of the invention comprises means for clamping a potential difference that is smaller than a predetermined value between the collector and the emitter of one of the differential transistors and enabling a current to flow through the constant current source.

Abstract: A voltage clamping circuit for a semiconductor memory device which is capable of rapidly coping with the demand of the user. The voltage clamping circuit includes PMOS transistors connected in series between an external supply voltage terminal and a node on an output line of a DC voltage generator, a control PMOS transistor having a channel connected at both ends thereof respectively to the node on the output line and a node between the second and third ones of the series-connected PMOS transistors, and a pad connected to a control electrode of the control PMOS transistor. The pad is selectively connected to a supply voltage in a first state and to a ground voltage in a second state, thereby controlling a clamping interval of the clamping means to be variable. The first state is a state requiring a longer clamping interval than that of the second state.

Abstract: The present invention relates to a static and monolithic current limiter and circuit-breaker component including, between two terminals, a one-way conduction current limiter, a sensor of the voltage between the terminals, and a mechanism for inhibiting the conduction of the current limiter when the voltage sensed exceeds a given threshold.

Abstract: An automatic gain control circuit in the feedback path for a laser wavelength control circuit is described herein. This gain control circuit automatically adjusts the amplification of the analog signals output from a photodetector array, where the array detects a fringe pattern created by a laser beam. Another feature of the preferred embodiment feedback circuit is the automatic setting of a DC offset voltage that compensates for errors in the feedback path and enables an accurate determination of a dark level signal in the fringe pattern signal. This dark level signal provides a reference for measuring the magnitude of the fringe pattern signal. Varying photodetector outputs may now be more accurately measured. The preferred embodiment feedback circuit also employs a very fast amplifier anti-saturation circuit using LED's connected in a clamp circuit.

Abstract: A level shift circuit includes a plurality of diodes connected in tandem in a forward direction, a normally-ON transistor connected between a high-potential power line and a node of a highest potential side among the plurality of diodes connected in tandem, and a first pull-down circuit connected between a node of a lowest potential side among the plurality of diodes connected in tandem and a low-potential power line. The level shift circuit further includes a second pull-down circuit connected between a node among the plurality of diodes and the low-potential power line. An input voltage is applied to a control electrode of the normally-ON transistor, and an output voltage is taken from the node of the lowest potential side among the plurality of diodes. By the constitution, the magnitude of a level shift can remain constant relative to a wide range of input voltages. Eventually, a linear input/output characteristic can be obtained.

Abstract: An inputted signal applied to an input terminal of a detecting circuit is rectified in a positive amplitude range thereof by a rectifier block and stored in a capacitor. In a negative amplitude range, the electric energy stored in the capacitor is discharged through a load block. The rectifier block and the load block have equal impedances, and hence a time constant when the capacitor is charged is equal to a time constant when the capacitor is discharged. A DC signal outputted from an output terminal of the detecting circuit has a level which is the same as the average power level of the inputted signal. The detecting circuit is capable of outputting a DC signal which is accurately representative of the power level of the inputted signal.

Abstract: A pre-biasing technique for a transistor-based avalanche circuit which improves the initial rate of rise in the current applied through a laser diode or other light emitting device in a laser based distance measurement and ranging instrument and, therefore, the sharpness of the leading edge of the laser pulse produced. Since the timing of the flight time of a laser pulse to a target and back to the ranging instrument is determined with reference to the leading edge of the emitted laser pulse, the inherent precision obtainable is enhanced by the production of a sharper leading edge pulse. Through the use of the pre-biasing technique disclosed, the very rapid rise time pulse which may be achieved also allows for the substitution of a much cheaper light emitting diode in lieu of a conventional laser diode in an alternative implementation of a light pulsed-based distance measuring and ranging instrument.

Abstract: A pulse-shaping circuit comprises a current limiter, which is connected in parallel with a voltage divider, for limiting a source voltage and enabling first and second voltage signals divided by the voltage divider to be constantly maintained, and an output voltage limiter which is provided to prevent a collector voltage of an output switching transistor from being increased to more than 0.1 V, so that an output pulse signal from an output terminal thereof may be lowered nearly to about 0.1 V when a low input pulse signal is applied to an input terminal thereof.