Abstract: A shunt and shunt control circuit are connected to the wires of an on-chip terminated I/O bus. Each instance monitors the wire that it is connected to. If the wire has been pulled low by any device on the bus, the circuit does nothing. If, however, the wire was not pulled low, then current is shunted from the termination voltage supply to ground. The turn on and turn off rates for this shunt are matched to the ramps of current through the termination impedance of the bus. This makes the variability in current drawn from the termination voltage supply less data dependent.

Abstract: Between a positive power supply 18 and a negative power supply 19, a p-channel transistor 11 and an n-channel transistor 14 are connected in series while a p-channel transistor 12 and an n-channel transistor 15 are also connected in series. An inverted input signal *Sig1 is input to the respective gates of the transistors 11 and 14, while an input signal Sigl is input to the respective gates of the transistors 12 and 15. As a result, of a pair of the transistors connected in series, namely either the transistors 11 and 14 or the transistors 12 and 15, when one transistor turns ON, the other transistor turns OFF. Thus, generation of through currents is prevented.

Abstract: The common mode component in the difference signal on the bus terminals (2, 4) of a CAN bus is counteracted by four transistors (M1-M4) connected between the supply terminals (28, 32) and a center tap (16) of a voltage divider (6A, 6B, 8, 10, 12A, 12B) between the bus terminals (2, 4). As a result of this, the voltage on the center tap (16) varies to a substantially smaller extent or not at all. Thus, it is possible to use a simpler differential amplifier (20) having a smaller common mode swing at the inputs (22, 24). Moreover, the attenuation factor selected for the voltage divider can be smaller, as a result of which a higher difference voltage is available for the differential amplifier (20).

Abstract: A pulse signal output circuit charges and discharges a capacitor in response to a clock signal and outputs a pulse signal having a pulse width determined by a time for charging and discharging the capacitor. A control signal generation circuit outputs a control signal in response to the pulse signal, where the control signal has a first voltage level determined by the pulse width. An output circuit has a first output transistor and a first regulating transistor connected in series between the first power supply node and the output terminal. The first output transistor is operated in response to a signal transferred from inside or outside a semiconductor device, and the first regulating transistor is operated in response to the control signal.

Abstract: When signal transmission is performed between two semiconductor integrated circuit devices in synchronization with a clock signal using a small signal amplitude relative to an operating voltage of the two semiconductor integrated circuit devices, a received signal is held in the receiving semiconductor integrated circuit device in synchronization with the clock signal while the small signal amplitude of the held signal is kept substantially without change. The received signal having the small signal amplitude is amplified along a signal transmission path including a combined logic circuit to a subsequent latch circuit of the receiving semiconductor integrated circuit device.

Abstract: A method of stabilizing the working point of a predistorter diode of a predistorter for an optical modulator as protection from temperature fluctuations, whereby the predistorter diode is supplied with a temperature-dependent voltage in order to adjust the working point, is characterized by the fact that a reference diode is thermally coupled with the predistorter diode so that the reference diode is supplied with a constant current, whereby it is not supplied with a signal distorted by the predistorter, and the predistorter diode is supplied with a voltage which is proportional to the reference diode. One advantage of the invention is that it is possible to achieve good temperature stability in an easy manner.

Abstract: A buffer/driver system that operates on an input signal to provide an output signal with a sufficient capability at an output terminal to drive a particular interface is disclosed. The input signal is operated on to produce the output signal that has wider voltage swing than the input signal. Therefore, the devices in a circuit that is producing the input signal can operate with low voltages, while the output signal can drive other systems with sufficient voltage levels.

Abstract: An apparatus stabilizes the level of an output signal (b) of an output control unit (1) according to a control signal (c). When a power source is turned on or when burst signal transmission starts, an input signal (a) to the output control unit (1) rises. While the input signal (a) is rising, a switching circuit (6) selects initial value data (e) held in an initial value data holding circuit (8), so that a smoothing unit (4) may generate the control signal (c) from the initial value data (e). When a variation in difference data obtained from a moving average of the difference between level data (h) detected by a level detecting unit (3) and reference value data (g) held in a reference value data holding circuit (9) decreases below a predetermined value, the switching circuit (6) provides the difference data as average value data (f) to the smoothing unit (4) so that the smoothing unit (4) may generate the control signal (c) from the average value data (f).

Abstract: An efficient charge pump circuit. Increased efficiency compared to previous pump circuits is achieved through use of a novel charge transfer switch and associated clocking scheme which reduces the supply current required to operate the charge pump. Instead of repeatedly charging and discharging a stray capacitance of each pump stage capacitor, some of the charge stored in the stray capacitor on the clock driver side is transferred to the next pump stage. This serves to pre-charge the stray capacitor of the next stage, reducing the supply current required to operate the charge pump. The apparatus and method described can also be used to reduce the power consumed by a system or circuit which has internal signals or nodes which are in opposite phase to each other. This is accomplished by reducing the power used to charge and discharge a stray capacitance associated with the signals or nodes.

Abstract: An anti-fuse programming circuit comprising an operation switching part for precharging the anti-fuse programming circuit with a half voltage to operate it, an anti-fuse connected to the operation switching part, the anti-fuse being subjected to a dielectric breakdown when it is supplied with an overcurrent, a sense signal input part for inputting a sense signal to verify a programmed state of the anti-fuse, a breakdown voltage supply part for supplying a source voltage for the dielectric breakdown of the anti-fuse, an output part for outputting a signal indicative of the programmed state of the anti-fuse in response to the sense signal inputted by the sense signal input part, a feedback part for feeding back the output signal from the output part strongly at low power and high speed, a current blocking part for blocking a current path from the breakdown voltage supply part to the anti-fuse in response to a control signal from the feedback part, a reverse current prevention part for blocking the flow of curre

Abstract: When signal transmission is performed between two semiconductor integrated circuit devices in synchronization with a clock signal using a small signal amplitude relative to an operating voltage of the two semiconductor integrated circuit devices, a received signal is held in the receiving semiconductor integrated circuit device in synchronization with the clock signal while the small signal amplitude of the held signal is kept substantially without change. The received signal having the small signal amplitude is amplified along a signal transmission path including a combined logic circuit to a subsequent latch circuit of the receiving semiconductor integrated circuit device.

Abstract: A system and method for providing a high speed differential receiver circuit is disclosed. The system comprises a source device. A receiver is coupled to the source device. The receiver receives first and second differential signals at a first input and a second input and provides first and second output signals at a first output and a second output. The system also comprises a first plurality of load devices coupled to the first output. The first plurality of load devices control a first voltage swing at the first output. The system also comprises a second plurality of load devices coupled to the second output. The second plurality of load devices control a second voltage swing at the second output.

Abstract: An integrated circuit, configured for connection to an SCSI bus includes a strobe assertion edge triggered glitch filter. Input data latches are controlled by the strobe assertion edge gated with a strobe enable signal and the inverted and delayed Q output of a flip-flop. Once a valid strobe assertion edge is detected, it is used latch data bus signals into the data latches. Following a defined delay period through a delay stage, the data latch strobe is masked from any further transition until the strobe enable signal is again affirmatively asserted by an SR latch. The masking period is defined upon receipt of a valid strobe assertion edge and maintained for a first period by the combination of the SR latch, a flip-flop and a delay stage. The latch strobe mask is maintained for a second period by a strobe masking extension circuit made up of series-connected flip-flops.

Abstract: A small amplitude signal output circuit comprises an output section for receiving a logic signal to output a small amplitude signal, a level sense circuit for sensing the rise or fall of an output voltage at an output terminal, and a level control circuit for responding to the output of the level sense circuit to suppress the rise or fall of the output voltage. The output circuit suppresses voltage variations caused by variations in fabrication process of transistors, ambient temperature and source voltage noise.

Abstract: A differential output circuit has first and second output lines and an output impedance connected between the first and second lines. The output impedance includes an active device (e.g., a field effect transistor) having a control input for receiving a control signal value for controlling the impedance value of the active device. A bias circuit is responsive to a reference impedance element for generating the control signal value for controlling the impedance value of the active device. An output driver stage is connected to the first and second output lines for supplying first and second differential driven output signals to the first and second output lines, respectively. An integrated circuit can include a number of differential output circuits and a common bias circuit responsive to a single reference impedance element for generating the control signal value for controlling the impedance value of each active device.

Abstract: A buffer circuit including current sources and switches to connect and disconnect current sources to an output node. The switches are controlled by voltage detectors for comparing an input signal with a reference level. When the reference level is a predetermined value, the amplitude of an output signal swings up to V.sub.CC and swings down to V.sub.EE.

Abstract: A milled tooth shaped rotary cone drill bit for drilling oil wells and the like manufactured using a powder metallurgy process in which an alloy powder is pressure molded into the desired bit shape, sintered, and precision machined.

Abstract: A current limiting circuit used with voltage regulators or other similar circuits is disclosed. The current limiting circuit uses two transistors, configured as a differential pair, combined with a fixed current source to limit the current available to a pass transistor of the voltage regulator.

Abstract: A series drive circuit for driving a plurality of serially-connected electronic elements, such as electrochromic elements. The series drive circuit maintains a accurately controlled voltage across each of the electronic elements, while reducing power consumption and current consumption. A constant voltage is applied to the serially-connected electronic elements that is the sum of the required voltage for each of the electronic elements. In order to prevent excess voltage across any of the elements, shunts are connected in parallel with each of the elements. In order to reduce excess voltage across any of the elements, the voltage across each of the elements is monitored and used to control the shunts to maintain a accurately controlled voltage across each of the serially-connected electronic elements.

Abstract: Modification of process control signals so as to enable electrostatographic reproduction apparatus, including a dielectric support member transported about a path into operative association with electrographic process elements to form an information reproduction on a receiver member and a process controller for receiving and sending appropriate timing control signals in an expected value range for controlling the electrographic process, to operate over an alternate process range. For the desired signal modification, an input signal in a particular value range is received. A predetermined gain is applied to the received signal, and thereafter a predetermined offset is applied to the signal as modified by the gain application. The signal derived by gain application and offset is then emitted at an alternate value range to effect process control.

Abstract: A semiconductor sensor device using a semiconductor material for the sensor and having a circuit configuration in which the operational amplifier of the final amplification stage forms an inverting amplifier circuit, and a pull-up resistance is connected to the output terminal of the operational amplifier, includes a saturation circuit for saturating the output voltage of the operational amplifier when the voltage of the inverting input terminal of the operational amplifier of the final amplification stage drops below a voltage value .alpha. at which the output voltage from the output terminal is saturated.

Abstract: A method for providing a regulated core voltage to a processor within a computer system is disclosed. In accordance with a method and system of the present invention, a power supply is provided for a processor that includes multiple core transistors and multiple I/O transistors. An input voltage is supplied to a first power input of the processor for powering the I/O transistors within the processor. This input voltage is also supplied to a second power input of the processor for powering the core transistors within the processor via a voltage regulator and a resistor, with the voltage regulator and the resistor connected in parallel, such that the voltage drop across said voltage regulator can be reduced.

Abstract: An attenuator circuit having three cascaded attenuator stages which become active, one at a time, as an input signal strength increases. In the highest gain state, the three attenuator stages are active. As the input signal increases, the attenuator stages become inactive sequentially starting with the last stage.

Abstract: The present invention includes a variable gain amplifier to output two differential signals which are level shifted and compared through two comparators to drive a charge pump which produces either a discharge current or a charge current to provide feedback control to the variable gain amplifier.

Abstract: A level shifting circuit includes first and second load, gain and reference transistors. The first and second load transistors each have a source-drain path arranged between Vdd and Vss power supply voltages, and a gate coupled to the Vss power supply voltage. The first and second gain transistors each have a source-drain path arranged between the respective source-drain paths of the first and second load transistors and the Vss power supply voltage, and gates serving as respective differential input nodes. The first and second reference transistors each have a source-drain path arranged between the Vdd and Vss power supply voltages, and a gate coupled to respective first and second nodes serving as respective differential output nodes, the first node connecting the source-drain path of the first load transistor with the source-drain path of the first gain transistor, and the second node connecting the source-drain path of the second load transistor with the source-drain path of the second gain transistor.

Abstract: A level shift circuit shifting logic levels of an SCFL circuit to logic levels of a DCFL circuit, including an SCFL circuit having complementary outputs; two source follower circuits with their inputs respectively connected to the complementary outputs of the SCFL circuit; a high/low detecting circuit detecting "high" or "low" signals which have DCFL levels from the two source follower circuits and outputting signals having logic levels according to the detection results; and DCFL circuits with inputs connected to outputs of the high/low detecting circuit. Therefore, it is possible to obtain a level shift circuit operating with a wider voltage range and in a wider temperature range than the prior art circuit.

Abstract: The system and method of enhancing the yield of flash memory circuit is disclosed. The method comprises performing a diagonal erase of a select group of memory cells on a wafer during sort. If the memory cells do not erase in a satisfactory manner, the control voltage applied to the memory cell is adjusted based on the memory cell's erase time. The circuitry for providing the adjustment voltage includes trimming circuitry for an incrementally increasing the applicable control of voltage.

Abstract: A driver circuit that is powered by a power supply voltage has an output terminal, and includes a pull-up transistor for pulling the output terminal up toward the power supply voltage. A voltage divider that is connected across the power supply voltage has a tap connected in circuit to an input of the pull-up transistor and includes variable resistance elements whose resistance varies together with a threshold voltage of the pull-up transistor for limiting a voltage at the output terminal to within a predetermined range that is lower than the power supply voltage.

Abstract: A microwave monolithic integrated circuit (MMIC) RF-generated bias circuit and method includes an input for receiving an RF signal. A rectifier coupled to the input and to electrical ground produces a rectified RF signal in response. A voltage divider coupled to the rectifier and to the electrical ground receives the rectified RF signal and produces a DC voltage therefrom. An output is coupled to the voltage divider for applying the DC voltage to a MMIC field effect transistor (FET) for biasing. No separate bias battery is required, and efficiency is optimized because the generated bias voltage increases to the point where the amplifier voltage begins to decrease, which in turn reduces the generated bias voltage. The derived bias voltage may be used to control other circuits (e.g., other amplifiers, oscillators, mixers, etc.) which require detection of RF presence.

Abstract: A supply voltage detect circuit is described which generates a control signal indicating the status of VCC to be at 5.0 or 3.3 volts. This control signal is used to generate analog reference signals used by A/D and/or D/A circuitry in an audio processing integrated circuit and by other circuitry to control clock frequencies or current drive.

Abstract: A data transmitter circuit includes a pseudoternary conversion circuit for converting a binary logic signal to a differential pseudoternary signal having symmetric rise and fall characteristics. The output of the pseudoternary conversion circuit is filtered and passed to an electrically conductive medium via an isolation transformer. The conversion circuit includes a symmetric arrangement of toggle circuits which respond to transitions in respective complementary binary signals constituting a differential binary input signal. Voltage dividers are connected to the output terminals of the toggle circuits for providing three levels of output voltages in response to the logical states of the toggle circuits.

Abstract: A circuit for converting a system supply voltage having one of two levels to a voltage for use by an integrated analog circuit connected to the system upon power-up. The circuit uses a diode-connected transistor to generate a reference voltage necessary for a regulator to regulate the supply voltage when the supply voltage is first powered up. The regulated supply voltage is doubled to a voltage level sufficient to activate the integrated analog circuit's bandgap voltage. The activated bandgap voltage is thus switched on to supply a more precise reference voltage to the regulator so that the diode-connected transistor may be de-activated to conserve power. The circuit also provides a bypass path for connecting the supply voltage directly to the integrated analog circuit when the supply voltage is the same level as the necessary voltage for the integrated analog circuit.

Abstract: An automatic gain and level control method and circuit. In general, the inventive method includes the steps of detecting the DC level of a signal and providing a first signal in response thereto and detecting the AC amplitude or gain of the signal and providing a second signal in response thereto. A DC level error signal is generated in response to the first signal. An AC amplitude error signal is generated in response to the second signal. The DC level of the signal is corrected in response to the DC level error signal. The AC amplitude of the signal is corrected in response to the AC amplitude error signal.

Abstract: An MOS reference voltage generating circuit is provided which has a simplified circuit that eliminates the need for a feedback circuit and a large compensating capacitor, and reduces the current consumption of the device. This is achieved by utilizing a new circuit configuration which is simplified. The simplifier reference potential generating circuit comprises a first PMOS transistor having its gate and its drain connected in common to a first node and its source connected to Vcc, a second PMOS transistor having its gate and its drain connected in common to a second node and its source connected to Vcc, a resistor connected between the first node and the second node, and a first current source connected between the first node and ground. A third PMOS transistor is connected at its gate to the second node and at its source connected to Vcc, so that a current mirror is constituted of the second and third transistors.

Abstract: In a reference voltage generating circuit having an improved temperature compensation function, a PMOS transistor forming a constant voltage circuit has the same characteristics as a PMOS transistor forming a negative feedback circuit. As an ambient temperature changes, gate-source voltage and drain current characteristics of each transistor are shifted, but temperature compensation is achieved by appropriately setting a drain current of each transistor. Transistors for the temperature compensation can be formed in the same manufacturing steps, so that temperature compensating effect can be obtained without an additional manufacturing step.

Abstract: A circuit pulls up an integrated circuit input capable of receiving a low voltage, receiving a high voltage, or floating. The circuit includes a first MOS transistor connected between the input and the high voltage; a serial connection between the high and low voltages of a second, third, and fourth MOS transistor; a connection between the gates of the first and second transistors and the junction of the third and fourth transistors; and a connection between the input and the gates of the third and fourth transistors.

Abstract: A sound gain control device for automatically controlling a gain by which an output signal from a sound CODEC is multiplied is provided. Sound signals from a sound input device are processed by a non-linear conversion circuit so that the sound signals with small amplitudes are enlarged by extending the amplitudes and the time axis thereof, thereby to average the incidence probabilities of amplitudes. Then, a proper amplitude for a gain control is calculated based on the averaged signals by an amplitude calculating circuit, and a gain corresponding to the calculated amplitude is determined by a gain determining circuit and sent as a amplitude coefficient to a multiplier to which the sound signals from the sound input device are input through a sound CODEC.

Abstract: Improved automatic gain control for an amplifier is obtained by controlling the size of a null zone in a drive signal for the amplifier. The size of the null zone is controlled by estimating strength of an interference signal, and dynamically varying the size of the null zone based on the estimated strength of the interference signal. As a result, the amplifier rarely saturates, regardless of signal strength. The invention is useful to reduce the harmful effects of jamming or interference.