Abstract: A system, method and machine-readable instructions for monitoring a power electronics device. The system involves a semiconductor device, at least one sensor and a processor. The processor is configured to monitor a junction temperature of the semiconductor device by determining from the at least one sensor an on-state resistance of the semiconductor device and calculating the junction temperature of the semiconductor device according to a relationship between the on-state resistance of the semiconductor device and the junction temperature of the semiconductor device. The processor may apply an ageing coefficient to the on-state resistance.

Abstract: According to an embodiment, a signal processor includes an integrator, a differentiator, a zero cross detector, a pile-up detector, an event interval detector, a counter, and a creator. The integrator is configured to calculate charge of current from a photoelectric converter for an incident radiation. The differentiator is configured to calculate a differential value of the current. The zero cross detector is configured to detect a zero cross of the differential value. The pile-up detector is configured to detect pile-up of the current based on the zero cross. The event interval detector is configured to detect, based on the zero cross and pile-up, an event interval of the radiation entering. The counter is configured to count, based on the charge and pile-up, the respective numbers of events according to the charge and the event interval. The creator is configured to create histograms for the numbers of events.

Abstract: Embodiments of the present invention may include an apparatus and method to reduce an output swing in each stage of a multi-stage loop filter while also maintaining a desired signal transfer function for each respective stage. A given stage of the loop filter may include an integrator, a feedback path, a first cancellation path, and a second cancellation path. The first cancellation path may be coupled to the output of the integrator. The second cancellation path may be coupled to a feedback path provided about the input and output of the integrator. A first cancellation signal may be injected into the first cancellation path to reduce the output swing of the integrator. A second cancellation signal may be injected into the second cancellation path to minimize a change in the integrator's signal transfer function caused by the first cancellation signal.

Abstract: A biquad wideband signal processing circuit can operate over bandwidths of 50 MHz to 20 GHz or more. The biquad circuit employs a configuration of integrators (transconductors), buffers, and scalable summers that can be implemented using deep sub-micron CMOS technology. Combining this scaling with high gain/high bandwidth enables implementation of feedback and programmability for broadband analog signal processing. A biquad circuit implementing a number of parallel integrator lines having adjustable gain provides greater accuracy, stability, and bandwidth, and allows for control of process variations and temperature variation in real-time.

Abstract: Systems and methods for preventing saturation of analog integrator outputs are provided. Applications of the systems and methods in hybrid analog-digital integrators are also provided. Exemplary systems include two switches, one operational amplifier, one capacitor C, four gain blocks, three comparators, one XOR gate, one OR gate, one T flip-flop, and one digital counter.

Abstract: An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output. The apparatus also comprises a controllable current source coupled to the first input of the comparator and configured for supplying or drawing current. The apparatus also comprises a digital logic circuit that is configured for controlling an amount of current supplied or drawn by the controllable current source. The apparatus is configured for measuring a charge associated with an external source that is coupled to the first input of the comparator.

Abstract: A system includes a sinc filter module and a cyclic integrator module. The sinc filter module (i) determines a direct current (DC) voltage component of an error between a measured output voltage of a switched-mode power supply and a reference voltage and (ii) determines a signal with ripple by subtracting the determined DC voltage component from the error. The cyclic integrator module (i) applies a learning gain to a difference between the determined signal with ripple and a predicted ripple, (ii) performs integration of each of N segments of the gain-applied difference, and (iii) generates the predicted ripple by reconstructing the N integrated segments, wherein N is an integer greater than one.

Abstract: A mixed signal correlator utilizes coherent detection within a capacitance measurement application. In some applications, the mixed signal correlator is used to measure capacitance of a touch screen display. An external capacitor whose capacitance is measured is kept small for improved sensitivity and can be used for a variety of applications having varied integration periods for measurement. The external capacitor is kept small and can be used for varied applications by adjusting the output voltage within a range that is less than the supply voltage, and maintaining a count of the adjustments to later reconstruct an actual output voltage for the integration period. An output is a weighted sum of an analog integrator output and a digital counter output.

Abstract: The present application describes an apparatus and method for improving the performance of ?? modulators functioning as ADCs. In one embodiment, the ?? modulator comprises a plurality of quantizers operating in a round-robin fashion, rather than the single quantizer of the prior art. The use of multiple quantizers allows the ?? modulator to appear to be functioning at a significantly higher rate than a single quantizer allows. In another embodiment, a second-order ?? modulator contains a plurality of control loops, rather than the single control loop of the prior art. The use of multiple control loops allows the ?? modulator to have multiple points of maximum signal-to-noise ratio rather than a single such point as in prior art ?? modulators.

Abstract: A biquad wideband signal processing circuit can operate over bandwidths of 50 MHz to 20 GHz or more. The biquad circuit employs a configuration of integrators (transconductors), buffers, and scalable summers that can be implemented using deep sub-micron CMOS technology. Combining this scaling with high gain/high bandwidth enables implementation of feedback and programmability for broadband analog signal processing. A biquad circuit implementing a number of parallel integrator lines having adjustable gain provides greater accuracy, stability, and bandwidth, and allows for control of process variations and temperature variation in real-time.

Abstract: Low noise bandgap voltage references using a cascaded sum of bipolar transistor cross coupled loops. These loops are designed to provide the total PTAT voltage necessary for one and two bandgap voltage references. The PTAT voltage noise is the square root of the sum of the squares of the noise voltage of each transistor in the loops. The total noise of the reference can be much lower than approaches using two or 4 bipolar devices to get a PTAT voltage and then gaining this PTAT voltage to the required total PTAT voltage. The cross coupled loops also reject noise in the current that bias them. Alternate embodiments are disclosed.

Abstract: A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.

Abstract: Broadband analog radio-frequency devices can be used to create building blocks for scalable analog signal processors that operate over bandwidths of 50 MHz to 20 GHz or more. Example devices include integrators (transconductors), digitally controlled attenuators, buffers, and scalable summers implemented using deep sub-micron CMOS technology. Because the devices are implemented in CMOS, the ratio of trace/component size to signal wavelength is about the same as that of low-frequency devices implemented in printed circuit boards. Combining this scaling with high gain/high bandwidth enables implementation of feedback and programmability for broadband analog signal processing.

Abstract: A circuit may include a source of electrical energy and a plurality of current loads. Each load may be of a different amount. For each current load, a resistance may be in series between the source and the current load. The resistance may be weighted inversely proportional to the amount of the current load with respect to the other resistances. For each resistance, an integrator may generate an integrated output representative of an integration of the current traveling through the resistance. A summer may generate a summed output which is representative of the sum of each of the integrated outputs, weighted inversely proportional to the resistance that is associated with the integrated output.

Abstract: A multi-stage sigma-delta modulator including bit truncation between stages. The bit truncation reduces the number of bits that must be processed in subsequent stages and thus allows for faster response times. In some embodiments, the gain of a feedback loop is selected to compensate for the bit truncation such that the sigma-delta modulator operates in a stable state.

Abstract: A signal preprocessing device is disclosed, which is integrated into a structure-borne sound sensor or into an acceleration sensor for sensing structure-borne sound, or which is connected at the input end to at least one sensor of this type and is connected at the output end to at least one signal channel that is connected to at least one central electronic control unit, and wherein the signal preprocessing device has at least one filter module having at least two bandpass filters. A method for preprocessing structure-borne sound sensor signals is also disclosed, in which a filtering operation is carried out in which at least two frequency bands, which are at least to a certain extent part of the structure-borne sound spectrum, are transmitted. Use of the above device in electronic motor vehicle security systems, in particular safety systems, in particular in vehicle occupant protection systems and/or passenger protection systems is also disclosed.

Abstract: Reduction in power consumption of a counter circuit for continuous operation is demanded. Therefore, provided is a counter circuit including: a first counter of m bits for counting and storing a value of a predetermined bit width according to an input clock; a clock transmission control circuit for controlling whether to transmit the input clock based on a value output according to a counting result of the first counter; and a second counter of n bits for counting and storing another value of the predetermined bit width according to the input clock transmitted from the clock transmission control circuit.

Abstract: According to at least one embodiment of the invention, an apparatus may include first, second and third circuits. The first circuit receives input data and provides a plurality of first signals asserted based on the input data. The second circuit receives the plurality of first signals and provides a plurality of second signals used to select a plurality of circuit elements. The third circuit generates a control for the second circuit using a fractional data weight of the input data, the second circuit mapping the plurality of first signals to the plurality of second signals based on the control from the third circuit.

Abstract: Correction of scintillation event data from a nuclear medicine imaging system for effects of pulse pile-up is carried out by separating event data packets into total energy and individual detector energy data packets, executing pile-up correction algorithms on each of the separated packets simultaneously using a pipeline processing architecture, and reassembling the corrected data packets into corrected scintillation event data packets. Pulse tail correction information for each individual detector is stored in a storage medium for a present event and immediately preceding event for which correction information exists, which allows individual detector correction information to be retrieved by using a look-up procedure, thereby enabling correction to be performed within a single processor cycle.

Abstract: Methods and apparatus are disclosed for calibrating summing amplifiers based on current integration. For example, apparatus for calibrating output voltage levels of a current-integrating summing amplifier includes the following components. A duplicate integrator circuit is provided, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier. A comparing circuit, coupled to the duplicate integrator circuit, is provided for comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level.

Abstract: A perfect integrator emulator includes a first multiplier multiplying an input with a first constant, KNEW, and generating a scaled input, a summer summing the scaled input with a previously generated scaled output and generating an accumulated output, a delay adding a predetermined amount of delay to the accumulated output and generating a delayed output, a second multiplier multiplying the delayed output with a second constant, KOLD, and generating the scaled output. The constants KNEW and KOLD are chosen such that the accumulated output emulates a perfect integrator's relative weighting, and saturation protection is guaranteed.

Abstract: A ramp generator for use in a video mixing system to produce various transition effects between edited video frames. The ramp generator produces a ramp signal R according to the equation R=Ah+Bv+C. The ramp signal R corresponds to a video frame comprised of v video lines (where v is an integer from 0 to m), each video line having h pixels (where h is an integer from 0 to n), and where A, B, and C are coefficients. Multiple ramp signals can be combined to a ‘solid’ signal. Solid signals can be used to generate masks or wipe patterns. Each ramp be edge modulated before combining into a solid signal. A solid signal can also be solid modulated.

Abstract: An apparatus for turning power to a device on and off is disclosed. The apparatus comprises a first signal input, a second signal input, a first charge output electrically connected with the first signal input, a transistor electrically connected with the second signal input, and a second charge output electrically connected with the transistor. The first charge output, when the first signal input and second signal input are powered on, electrically ramps up a first portion of the device. This ramp up of the first portion draws from current available to ramp up a second portion of the device. The second charge output is, thus, provided. The second charge output, when the first signal input and second signal input are powered on, electrically charges the transistor and the transistor electrically ramps up the second portion of the device concurrently with the ramp up of the first portion.

Abstract: The present invention discloses a fully integrated precision HDA shock sense circuit with high-order filters implemented in integrated circuit technology. Filters are integrated with an improved on-chip bias generator so that they can provide stable, trimmable and/or programmable frequency responses with a minimum number of external capacitors. The invention provides dual full-wave rectifiers for X-axis and Y-axis shock sensing so that more accurate and reliable shock detection can be achieved. Input signals from X-axis and Y-axis shock sensors are converted to current and provided to the dual full-wave rectifiers. The currents thus full-wave rectified are summed and lowpass filtered to generate an output signal, which is then fed to a comparator to produce a shock detection logic signal.

Abstract: A degenerated differential pair waveform builder has a single ramp generator control circuit and a plurality of differential pairs. A trigger input is generated and input to the ramp generator control circuit. The ramp generator control circuit then generates a differential signal which is output to each of the differential pairs through a positive edge signal node and a negative edge signal node. Each differential pair then generates an output in response to the differential signal output from the ramp generator control circuit. The outputs from the differential pairs are combined in a summing circuit which outputs a composite waveform. Each differential pair has an associated ramp time which is dependent upon the value of the resistance in its emitter circuit. The ramp time of each differential pair directly affects the slope of its resulting output waveform.

Abstract: A switched current differentiator includes first and second interconnected current memory cells, An input current is applied to terminal (1) and is fed on line (2) to the current memory cells, A first output current is derived from the first current memory cell via a transistor and a second output current is derived from the second current memory cell via another transistor. The second output current is inverted (A1) and summed with the first output current. The summed current is inverted (A2) and fed to an output via a switch on odd phases of a clock signal and is fed directly to the output via a further switch (S4) on even phases of a clock signal. A damped differentiator may be formed using a feeback loop. In a fully differential version of the differentiator the inverters may be constructed by the correct interconnection of the differential signals, i.e. by crossing over connections.

Abstract: A method and apparatus for integrating a plurality of analog input signals. A first integrator(725) having a first pole frequency integrates a first of the input signals and a second integrator(730) having a second pole frequency different than the first pole frequency integrates a second of the input signals. A summer(735) is connected to the first and second integrators to then sum the integrated first and second signals and provide a composite integrated signal prior to transmitting a communications signal.

Abstract: An apparatus for generating a sensing signal from a generally periodic multi-phase AC signal is set forth. The apparatus utilizes a plurality of integrator circuits, a single integrator circuit being respectively associated with each phase of the AC signal. The integrator circuits each generate an integrated signal from the respective phase of the AC signal by integrating the respective phase during a time period between sloping transitions of the respective phase. A reset circuit is respectively associated with each integrator circuit for resetting each integrator circuit at the sloping transitions of the respective phase. The integrated outputs are summed by a summing circuit to form the sensing signal.

Abstract: A DMA control system continuously grants permission to access the I/O device and memory to continue data transfer in a cycle steal mode when there is a continuous stream of DMA requests from a number of I/O devices by producing a logical sum of the DMA requests.

Abstract: An automatic gain and level control output circuit. The inventive circuit (10) includes a first component (12) for multiplying an input signal by a first reference signal to provide a gain adjusted signal. The input signal is level shifted by a second reference signal by a second component (16) to provide a level adjusted signal. The gain and level adjusted signals are compared to third and fourth reference signals by third and fourth components (26 and 28), respectively. The outputs of the third and fourth components (26 and 28) are combined to provide a first signal. Either the output of the third component (26) or the fourth component (28) is selected to provide a second signal having a first or a second level respectively. The first signal is integrated to provide the first reference signal and the fourth signal is integrated to provide the second reference signal.

Abstract: An estimating circuit for application in estimating or deriving the value V.sub.rms.sup.2 or V.sub.peak.sup.2, of a line voltage V.sub.AC provides fast response time and a substantially ripple free value for these signals by the utilization of a controlled harmonic oscillator whose output precisely tracks the input voltage waveform. Two out of phase (by .pi./2) sine wave signals are derived from the input sine wave and these two out of phase signals are squared and summed to derive or estimate the desired square of the sine waveform signal at a fast response time while substantially excluding ripple of the estimated out of phase sine waves. An estimating circuit, described herein, comprises two integrator circuits series connected into a substantially closed loop. The output of the second integrator circuit is fed back to the input of the first integrator circuit. The output of each individual integrator circuit is a voltage sine wave separated in phase from the output of the other integrator by .pi.

Abstract: The circuit is adapted for integration of pulse signals of the shape U(t)=U.sub.0 exp(-t/.tau.), wherein the time constant .tau. can be determined in advance by a calibration measurement, in particular signals from a scintillation detector. The purpose is to treat pile-up phenomena, without measuring the integration time, wherein the measured integral is corrupted because the time distance between two pulses becomes smaller than the integration time for the first pulse. The circuit comprises an integrator (4, 5, 6, R, C) for the pulse signal and a summator (3, R.sub.1 -R.sub.3) for forming a weighted sum of the pulse signal (on 1, 2) and the integrated signal (from 4, 5), the weight of the pulse signal and the weight of the integrated signal having such a relation to each other that the result signal (on 8) is proportional to the sum of the time integral of the pulse signal and .tau. times the pulse signal.