Abstract: A voltage-mode transmitter includes a serializer, a pre-driver circuit, a driver circuit, and a resistor calibration circuit. The serializer converts a data into a serial data. The pre-driver circuit drives the serial data. The driver circuit includes a slice, a replica slice, a reference voltage generation circuit, a first operational amplifier, and a second operational amplifier. The reference voltage generation circuit is coupled between a first system voltage and a second system voltage and includes a resistor. The resistor calibration circuit is configured to use a first current source and a reference resistor to generate a reference voltage, the first current source being a current source having been calibrated by a bandgap reference (BGR) circuit; to generate a target voltage by causing a current of a second current source to flow through the resistor; and to adjust the resistor according to the reference voltage and the target voltage.

Abstract: Combinatorial logic circuits with feedback, which include at least two combinatorial logic elements, are disclosed. At least one of the combinatorial logic elements receives an external input (i.e., from outside the circuit), at least one of the combinatorial logic elements receives an input that is feedback of the circuit output, and at least one of the combinatorial logic elements receives an input that is neither an external input nor an output of the circuit but rather is from another of the combinatorial logic elements and thus only “implicit” to the circuit. No staticizers are needed; the logic circuits effectively create implicit equations to perform functions that were previously thought to require sequential logic. The combinatorial logic circuits result in a stable output (in some instances after a brief period of time) due to the implicit equations, rather than achieving stability from an explicit expression of some input to the circuit.

Abstract: The present disclosure relates generally to digital microphone and other sensor assemblies including a transducer and a delta-sigma analog-to-digital converter (ADC) with digital-to-analog converter (DAC) element mismatch shaping and more particularly to sensor assemblies and electrical circuits therefor including a dynamic element matching (DELM) entity configured to select DAC elements based on data weighted averaging (DWA) and a randomized non-negative shift.

Abstract: An integrated circuit with self-reference impedance includes an input/output pin provided for connection to an external impedance, a local impedance, a reference power circuit, a switching circuit, and a control circuit. The switching circuit is configured to conduct a connection between the input/output pin and the reference power circuit in a first state and to conduct a connection between the local impedance and the reference power circuit in a second state. The control circuit is configured to detect whether the external impedance is connected to the input/output pin or not and to generate a detection signal. The control circuit controls the switching circuit into the first state or the second state according to the detection signal. In the first state, the reference power circuit generates a reference signal according to the external impedance. In the second state, the reference power circuit generates the reference signal according to the local impedance.

Abstract: A semiconductor circuit and semiconductor device for determining status of a fuse element are provided. The semiconductor circuit includes a configurable reference resistor unit with a first terminal receiving a first power signal and a second terminal electrically coupled to the fuse element. The semiconductor circuit also includes a latch circuit for reading a first status signal of a first node between the configurable reference resistor unit and the fuse element. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to be provided to the gate of the first transistor.

Abstract: A test probe contactor includes an angled depressible probe configuration that causes the tips of the compressible probes to “swipe” the contact pads/solder balls of an IC device under test as the contacts are made. The angulation of the depressible probes permit penetration through foreign material layers on the pad/ball surfaces with less contact force. The contactor includes an upper block and a main block for housing the plurality of probes. The main block and the upper block include corresponding pluralities of slanted probe cavities. The upper bore axis of one or more of the upper probe cavities is laterally shifted relative to the main bore axis of a corresponding probe cavity of the main block, resulting in a lateral offset between the upper bore axis and the main bore axis.

Abstract: Device for improving an optical detecting smoke apparatus and implementing thereof. Apparatus and methods for detecting the presence of smoke in a small, long-lasting smoke detector are disclosed. Specifically, the present disclosure shows how to build one or more optimized blocking members in a smoke detector to augment signal to noise ratio. This is performed while keeping the reflections from the housing structure to a very low value while satisfying all the other peripheral needs of fast response to smoke and preventing ambient light. This allows very small measurements of light scattering of the smoke particles to be reliable in a device resistant to the negative effects of dust. In particular, geometrical optical elements, e.g., cap and optical defection elements, are disclosed.

Abstract: A resistance trimming circuit has a resolution of N=X+Y bits. Included is a first circuit with M resistors, where M=2X?1, with each of the M resistors having a resistance of R*(2Y)*i, i being an index having a value ranging from 1 to 2X?1. M switches are associated with the M resistors. Each of the M resistors is coupled between a first node and its one of the M switches, and each of the M switches couples its one of the M resistors to a second node. Included is a second circuit with P resistors, where P=2Y?1, with each of the P resistors having a resistance of R*i. P switches are associated with the P resistors. Each of the P resistors is coupled between the second node and its one of the P switches, and each of the P switches selectively couples its one of the P resistors to a third node.

Abstract: Disclosed is a test and measurement probe including a signal channel having an input series resistor with a series parasitic capacitance. The probe also includes an amplifier coupled to the signal channel. The amplifier includes a shunt parasitic capacitance. A variable shunt resistor is coupled to the signal channel and a ground. The variable shunt resistor can be set to match a resistance capacitance (RC) value associated with the series parasitic capacitance and the shunt. The probe can also include a variable series resistor coupled to the amplifier. The variable series resistor can be set to adjust for attenuation variation associated with the variable shunt resistor. Other embodiments may be described and/or claimed herein.

Abstract: A device includes a receiver and a decoder. The receiver is configured to receive bitstream parameters corresponding to at least an encoded mid signal. The decoder is configured to generate a synthesized mid signal based on the bitstream parameters. The decoder is also configured to generate one or more upmix parameters. An upmix parameter of the one or more upmix parameters having a first value or a second value based on determining whether the bitstream parameters correspond to an encoded side signal. The first value is based on a received downmix parameter. The second value is based at least in part on a default parameter value. The decoder is further configured to generate an output signal based on the synthesized mid signal and the one or more upmix parameters.

Abstract: A switch circuit includes: a switching device control circuit receiving a first voltage and a second voltage, a first Type-I switching device coupled to the switching device control circuit and a first control voltage, a first Type-II switch element coupled to the switch control circuit and the first Type-I switch element, and a second Type-II switch element coupled to the first Type-I switch element and the first Type-II switch element. When the second voltage is higher than the first voltage, the switch control circuit turns on the first Type-II switch element in order to turn off the second Type-II switch element; and when the second voltage is higher than the first voltage, the first Type-I switch element is off.

Abstract: A semiconductor device includes: a virtual power line extended in a first direction; an n-well extended in the first direction, wherein the virtual power line and the n-well are disposed in a row; a first power gate switch cell disposed in the n-well; a second power gate switch cell disposed in the n-well, wherein the first and second power gate switch cells are first type cells; and a third power gate switch cell disposed in the n-well between the first and second power gate switch cells, wherein the third power gate switch cell is a second type cell different from the first type cells.

Abstract: A capacitor having a capacitance settable by biasing, including: a series association of a plurality of first capacitive elements between two first terminals defining the capacitor electrodes; and two second terminals of application of bias voltages respectively connected, via resistive elements, to the opposite electrodes of each of the first capacitive elements.

Abstract: The present invention achieves a proper balance among multiple constituent bias resistors of a variable-capacitance circuit by using different resistance values for resistors located at specific positions and the other resistors, thereby reducing a response time while sufficiently blocking an alternating-current component. This variable-capacitance circuit is a variable-capacitance circuit for which variable-capacitance components (C1-C4), the capacitances of which change in accordance with a control voltage, are connected in series between terminals to which an alternating-current signal is applied, and multiple bias application paths for applying a bias voltage to each of the variable-capacitance components via resistance components (R1-R5) are formed, wherein, among resistance components (R1-R5), resistance components (R1, R5) connected to the terminals, to which the alternating current is applied, have different resistance values from the resistance values of the other resistance components (R2-R4).

Abstract: A variable capacitance device includes a ferroelectric capacitor, a control terminal, a ground terminal, and a capacitor. The ferroelectric capacitor includes a ferroelectric film and capacitor electrodes sandwiching the ferroelectric film, and its capacitance value is changed according to a control voltage value applied between the capacitor electrodes. The control terminal is connected to a first end of the ferroelectric capacitor. The ground terminal is connected to a second end of the ferroelectric capacitor. The capacitor is connected between the control terminal and the ground terminal, and has a capacitance larger than that of the ferroelectric capacitor.

Abstract: A deposit detection device for an exhaust pump is provided, which can be easily put into operation without the burdens of, for example, installing equipment for flowing a gas, or adding or changing operation modes in apparatuses.

Abstract: In a semiconductor chip for an electronic device, a programmable trim code is independent from a default trim code. An output trim code is produced by selecting either the default trim code or the programmable trim code. The default trim code for a plurality of the semiconductor chips is set by forming metal interconnects according to a first metal layout in a metal interconnect layer during fabrication of at least one of the semiconductor chips. The default trim code is reset by forming the metal interconnects according to a second metal layout in the metal interconnect layer during fabrication of subsequent semiconductor chips.

Abstract: Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.

Abstract: Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

Abstract: A transmission device that establishes efficient match with an impedance mismatch section of a differential transmission system. The transmission device includes: a differential driver; a differential receiver; a differential line that connects between the differential driver and the differential receiver, the differential line including in-phase signal wiring and inverted-phase signal wiring; a delay increasing structure interposed in the differential line at an upstream of the impedance mismatch section; and a delay increasing structure interposed at a downstream of the impedance mismatch section. The delay increasing structure is interposed only in one of the in-phase signal wiring and the inverted-phase signal wiring, and the delay increasing structure is interposed only in another of the in-phase signal wiring and the inverted-phase signal wiring.

Abstract: The present document relates to amplifiers, notably multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. An amplifier comprising an output stage for providing an output current at an output voltage, in dependence of an input voltage at a stage input node of the output stage, is described. The output stage comprises a first input transistor; wherein a gate of the first input transistor is coupled to the stage input node of the output stage. Furthermore, the output stage comprises a first diode transistor; wherein the first diode transistor is arranged in series with the input transistor. In addition, the output stage comprises a pass device configured to provide the output current at the output voltage; wherein the first diode transistor and the pass device form a current mirror.

Abstract: An interpolation circuit includes: a plurality of holding circuits configured to each hold a corresponding input data input chronologically; and a generating circuit configured to generate interpolation data by giving weights, based on an interpolation code, to input data that are chronologically adjacent to each other and are held by the plurality of holding circuits and combining the weighted data together.

Abstract: In an embodiment, the present invention includes a latch circuit having a first input to receive a data signal and a second input to receive a clock signal. This latch circuit may have a first pair of transistors including a first transistor gated by the data signal and a second transistor gated by an inverted data signal and a second pair of transistors including third and fourth transistors gated by the clock signal. The first transistor may be coupled to the third transistor at a first inter-latch node and the second transistor coupled to the fourth transistor at a second inter-latch node. A reset circuit may be coupled to the latch circuit to maintain the first and second inter-latch nodes at a predetermined voltage level when the clock signal is inactive.

Abstract: A communication system according to one aspect of the present invention, comprises one or more integrated circuits. The one or more integrated circuits comprise at least one of a local integrated circuit and a remote integrated circuit. At least one sending application hardware module located on the local integrated circuit has a sending logic that controls the sending of messages from the sending application hardware module. At least one receiving application hardware module is located on at least one of the local integrated circuit or remote integrated circuit. A sending application hardware module sends messages to a receiving application hardware module without its sending logic having been constructed with a priori knowledge of the address of or the path to said receiving application hardware module. A dispatch logic located on the local integrated circuit that routes at least one or more.

Abstract: A circuit for delaying an input signal includes first and second delay units. The input signal is switched to the first delay unit which is configured to delay the input signal by k cycles of a first clock signal so as to generate a value xt—k and transfer the input signal to the second delay unit. The second delay unit includes a converter and a second shift register. The converter is connected to the second shift register by n leads. The value xt—k and a value xt—k?1 are present at the converter, where xt—k?1 is the input signal delayed by k?1 cycles of the first clock signal, The converter is configured such that the value xt—k?1 is present on leads 1 to m and the value xt—k is present on leads m+1 to n. The second shift register is configured to successively output values present on leads 1 to n.

Abstract: The present invention relates to a signal directing means (1, 1?, 1?, 36) for dividing or combining signals. It comprises a bottom row first port (2), a first row first and second port (3, 4),and a bottom row signal connector (5).The signal directing means (1, 1?,1?, 36) further comprises a first row first and second amplifier (9; 9?; 10; 10?), each first row amplifier (9, 10; 9?, 10?) having a corresponding first and second terminal (9a, 10a; 9a?, 10a; 9b, 10b; 9b?, 10b), said first terminals (9a, 10a; 9a?, 10a?) being connected along the bottom row signal connector (5). The signal directing means (1, 1?, 1?, 36)also comprises a first row signal connector (11), where said second terminals (9b, 10b; 9b?, 10b) are connected along the first row signal connector (11). The second terminal (9b; 9b?) of the first row first amplifier (9, 9?) is connected to the first row first port (3) and the second terminal (10b; 10b?) of the first row second amplifier (10; 10?) is connected to the first row second port (4).

Abstract: An AC electric motor, an inverter and a controller are mounted on an electric powered vehicle. The controller includes a voltage deviation calculating unit, a modulation factor calculating unit, and a mode switching determination unit. The voltage deviation calculating unit calculates a voltage deviation between a first voltage command when the rectangular wave voltage control is executed and a second voltage command when pulse width modulation control is executed, by inputting a current deviation to a voltage equation of the AC electric motor. Modulation factor calculating unit calculates the modulation factor based on the first voltage command and the voltage deviation. The mode switching determination unit determines whether or not control mode of the AC electric motor from the rectangular wave voltage control to the pulse width modulation control is necessary, based on the modulation factor.

Abstract: This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.

Abstract: In a waveform generation apparatus, a coordinates information group showing original waveform data in a two-dimensional phase space having a time axis and a wave height value axis is expanded to an n-dimensional phase space (n>2) including a time axis and a wave height value axis using Takens' embedding theorem, and converted to a coordinates information group showing attractor data. In addition, an area of the attractor data is shown, and after one of the coordinates information is specified from the coordinates information group within the shown area, coordinate values corresponding to a time axis in the coordinates information are acquired as time information. Then, composite waveform data is generated by a predetermined waveform data being added to the original waveform data, and the generated composite waveform data is outputted from a position of the original waveform data on a time axis corresponding to the acquired time information.

Abstract: A distributed, reconfigurable statistical signal processing apparatus comprises an array of discrete-time analog signal processing circuitry for statistical signal processing based on a local message-passing algorithm and digital configuration circuitry for controlling the functional behavior of the array of analog circuitry. The input signal to the apparatus may be expressed as a probabilistic representation. The analog circuitry may comprise computational elements arranged in a network, with a receiving module that assigns probability values when an input signal arrives and communicates the probability values to one of the computational elements, the computational elements producing outputs based on the assigned probability values. The signal processing apparatus may be an analog logic automata cell or an array of cells, wherein each cell is able to communicate with all neighboring cells.

Abstract: Characteristics of a circuit element are predicted accurately by taking account not only of the temperature variation due to self-heating of the element but also of temperature variation due to heat transmission from an adjoining heater element.

Abstract: A method of processing a signal is disclosed.

Abstract: A noise generator for generating band-limited noise from a plurality of sinusoidal signals at the same level and equidistant frequency position in the noise spectrum is provided. A noise signal has a low crest factor and for this purpose the phase position of each individual sinusoidal signal is determined.

Abstract: A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

Abstract: Various embodiments of the present invention provide systems and methods for phase offset based spectral aliasing compensation. For example, a circuit for spectral aliasing reduction is disclosed that includes a phase shift circuit operable to phase shift an analog input signal and to provide a phase shifted analog signal; a first analog to digital converter circuit operable to provide a first series of digital samples corresponding to the analog input signal at a sampling frequency; a second analog to digital converter circuit operable to provide a second series of digital samples corresponding to the phase shifted analog signal at the sampling frequency; and an averaging circuit operable to average the first series of digital samples with the second series of digital samples to yield an average output.

Abstract: A self-oscillating switch circuit for amplitude modulation dimming for dimming a LED load. The self-oscillating switch circuit comprises a high-power input terminal (S2) for supplying a first power to the load and a low-power input terminal (S1) for supplying a second power to the load. The switch circuit further comprises a power switch semi-conductor device (Q1) configured for controlling a load current from at least one of the high-power input terminal (S2) and the low-power input terminal (S1) to the output terminal. A control semi-conductor device (Q2) is configured to control the power switch semi-conductor device (Q1) in response to a sensing voltage.

Abstract: A digital filter-decimator-tuner is configured to receive a complex signal input xk and output a complex USB signal yuk and a complex LSB signal ylk. It includes a USB processing path coupled to receive xk and output yuk, the USB processing path including a USB FIR filter configured to receive a portion of the xk signal and output a first USB intermediate filtered signal, a decimator configured to decimate the first USB intermediate filtered signal and output a second USB intermediate signal, a USB tuner configured to receive the second USB intermediate signal and a USB tuning signal and output a third USB intermediate signal, and a USB equalization filter configured to receive the third USB intermediate signal, and output yuk; and a parallel LSB processing path coupled to receive xk and output ylk. The USB and LSB processing paths may be implemented by the same hardware in one embodiment.

Abstract: Apparatus comprising an input connected to receive an input signal, a lookup table comprising a plurality of input entries and first and second output entries for each input entry. The look up table receives the input signal and returns a lower input entry, an upper input entry, the second output entry for the lower input entry, and the first output entry for the upper input entry. A first subtractor subtracts the lower input entry from the input signal to produce a first difference. A second subtractor subtracts the input signal from the upper input entry to produce a second difference. First and second multipliers multiply the first and second differences by the first output entry for the upper input entry and the second output entry for the lower input entry, respectively, to produce first and second products. An adder adds the first and second products to produce an output signal.

Abstract: Provided are a coefficient multiplier and digital delta-sigma modulator using the same. The coefficient multiplier has the average of output signals of respective dependent multipliers as an effective coefficient using a coefficient averaging technique without employing an adder that has a complex structure and occupies a large chip area. Accordingly, the coefficient multiplier has a simple hardware constitution and small chip area in comparison with a canonical signed digit (CSD) coefficient multiplier, and the digital delta-sigma modulator employing the coefficient multiplier has a simple structure and small size.

Abstract: A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein.

Abstract: A test control circuit according to an embodiment of the invention includes a test mode control unit that outputs a control signal according to a voltage trimming test signal, a decoding portion that receives the control signal and outputs a decoding signal, and a trimming signal adjusting portion that receives the decoding signal and outputs a trimming signal adjusted by a low level test signal.

Abstract: A storage device with automatic-switching function is disclosed. When the storage device is coupled to a USB interface, the power provided by the USB interface turns the USB/SATA converter on to convert data from the USB interface into SATA format and transmit to a hard disk. When the storage device is coupled to a SATA interface instead of the USB interface, the power provided by the USB interface does not turn the USB/SATA converter on to convert data. In this way, the data from the SATA interface directly transmit to the hard disk.

Abstract: In one embodiment, a low power voltage detection circuit includes a first voltage detection device that receives power from an input voltage and a second voltage detection device receives power from an output of the low power voltage detection circuit.

Abstract: The present invention relates to a system and method for implementing auto-configurable default polarity. More specifically, the present invention relates to a transceiver module comprising, for example, a single chip multi-sublayer PHY, where the single chip multi-sublayer PHY is adapted to implement auto-configurable default polarity. In one embodiment, the transceiver module comprises at least one program module adapted to be programmed with at least a default polarity setting. The single-chip multi-sublayer PHY comprises at least one selection register communicating with at least the program module, where the selection register is adapted to store at least the default polarity setting. The single chip multi-sublayer PHY further comprises at least one multiplexer communicating with at least the selection register and adapted to select one polarity from at least two possible polarities based at least in part on the default polarity setting.

Abstract: Circuits and methods for determining component ratios are provided. An analog to digital converter circuit may include comparison capacitors arranged in an upper group and a lower group for quantizing analog signals into the digital domain. In addition to determining the lower bits during an analog to digital conversion of an input sample, the lower group of comparison capacitors may also be used during calibration mode to quantize a ratio signal that represents the capacitor mismatches of the upper group rather than using a dedicated digital-to-analog converter to perform this function.

Abstract: A method of processing a signal is disclosed.

Abstract: A method of processing a signal is disclosed. The present invention includes receiving a downmix signal generated from plural channel signal and spatial information indicating attribute of the plural channel signal to upmix the downmix signal; obtaining inter-channel phase difference (IPD) coding flag indicating whether IPD value is used to the spatial information from header of the spatial information; obtaining IPD mode flag based on the IPD coding flag from the frame of the spatial information, the IPD mode flag indicating whether the IPD value is used to a frame of the spatial information; obtaining the IPD value of parameter band of parameter time slot in the frame, based on the IPD mode flag; smoothing the IPD value by modifying the IPD value by using IPD value of previous parameter time slot; and generating plural channel signal by applying the smoothed IPD value to the downmix signal.

Abstract: According to one embodiment, a system, apparatus, and method for receiving high-speed signals using a receiver with a transconductance amplifier is presented. The apparatus comprises a transconductance amplifier to receive input voltage derived from an input signal, a clocked current comparator to receive output current from the transconductance amplifier, and a storage element to receive a binary value from the clocked current comparator.

Abstract: A distributed, reconfigurable statistical signal processing apparatus comprises an array of discrete-time analog signal processing circuitry for statistical signal processing based on a local message-passing algorithm and digital configuration circuitry for controlling the functional behavior of the array of analog circuitry. The input signal to the apparatus may be expressed as a probabilistic representation. The analog circuitry may comprise computational elements arranged in a network, with a receiving module that assigns probability values when an input signal arrives and communicates the probability values to one of the computational elements, the computational elements producing outputs based on the assigned probability values. The signal processing apparatus may be an analog logic automata cell or an array of cells, wherein each cell is able to communicate with all neighboring cells.

Abstract: The invention relates to a device for determining the temporal position of an analogue trigger signal with relation to an analogue clock signal, comprising an analogue cross-correlator (30), which carries out an analogue cross-correlation between the trigger signal and clock signal to provide a fine resolution.