Abstract: Voltage regulator circuitry includes a first element, a second element, an amplifier and a reference voltage source. The first element converts an input voltage and outputs a predetermined output voltage. The second element outputs a current in proportion to a current based on the outputted voltage from the first element. The amplifier amplifies a differential voltage between a reference voltage and a voltage in proportion to the output voltage, the amplifier which controls the first element based on the differential voltage. The reference voltage source outputs the reference voltage which adapts to a comparison between the current outputted from the second element and a reference current.

Abstract: Apparatus and method are disclosed for measuring a load current supplied to one or more integrated circuit cores. The apparatus includes a power gating field effect transistor (FET) comprising a gate, a source, and a drain, wherein the source is coupled to a voltage rail, wherein the drain is coupled to a load, and wherein the gate is configured to receive a gating voltage to selectively turn on the power gating FET to allow a load current to flow between the voltage rail and the load; and a differential amplifier configured to generate a current-related voltage related to the load current by applying a gain to an input voltage based on a drain-to-source voltage of the power gating FET, wherein the gain varies inversely with the input voltage in response to variation in temperature or gate-to-source voltage of the power gating FET.

Abstract: A CMOS logarithmic current generator includes current mode circuitry having a design principle based on a Taylor's series expansion that approximates an exponential function. A MOSFET circuit provides a function generator core cell having a biasing current Ib. The FETs of the circuit are matched and are biased in the weak inversion region. Additional transistors are used to convert a pair of input currents to a pair of voltages to provide an output current based upon a current mode logarithmic function. The biasing current Ib can be varied to provide a variable gain in the circuit.

Abstract: Certain embodiments of the invention may be found in an ultra low power dosimeter assembly. The ultra low power dosimeter assembly may comprise a low power voltage source and a table circuit. The table circuit may be adapted to convert an input voltage to a second voltage level. The second voltage level may correspond to noise dose. The ultra low power dosimeter assembly may also comprise a switch adapted to trigger a control circuit. The control circuit may provide progressive attenuation of an output signal as the second voltage level increases. In certain embodiments, the control circuit may also be adapted to send one or more warning signals to a user of the ultra low power dosimeter. The one or more warning signals may be sent when the control circuit determines the second voltage level has reached one or more pre-determined threshold voltage levels.

Abstract: In a semiconductor integrated circuit apparatus and a radio-frequency power amplifier module, a log detection portion including multiple-stage amplifier circuits, multiple level detection circuits, adder circuits, and a linear detection portion including a level detection circuit are provided. Output current from the log detection portion and output current from the linear detection portion are multiplied by different coefficients and the results of the multiplication are added to each other to realize the multiple detection methods. For example, current resulting from multiplication of the output current from the log detection portion by ×6/5 is added to the output current from the linear detection portion to realize a log detection method and, current resulting from multiplication of the output current from the log detection portion by ×? is added to current resulting from multiplication of the output current from the linear detection portion by ×3 to realize a log-linear detection method.

Abstract: Exemplary embodiments of the invention disclose receiver baseband filtering. In an exemplary embodiment, the filter device may comprise a continuous-time filter and a discrete-time filter operably coupled to the continuous time-filter. The discrete-time filter may include a passive infinite impulse response filter operably coupled between the continuous-time filter and an amplifier. The discrete-time filter may also include an active infinite impulse response filter operably coupled between an output of the amplifier and an input of the amplifier. The discrete-time filter may be configured to combine an output of the active infinite impulse response filter and an output of the passive infinite impulse response filter to form a composite signal. Furthermore, the amplifier may be configured to receive and amplify the composite signal.

Abstract: A circuit includes, an attenuator responsive to an input signal and a feedback signal, a variable gain low-noise amplifier responsive to the attenuator and to the feedback signal, a tracking filter, a frequency converter, and an RSSI responsive to the variable gain amplifier to generate an output signal to which the feedback signal is responsive. The frequency converter may be a mixer having a single-ended input and a differential output. The circuit may further include an analog baseband block responsive to the mixer to filter out high frequency signals. The tracking tuner performs bandpass filtering operation on the output signals of the variable gain low-noise amplifier.

Abstract: An input signal is applied to a ratiometric gain/attenuator circuit. A nulling circuit is arranged to null the input signal with an output from the ratiometric gain/attenuator circuit. The ratiometric gain/attenuator circuit may include a gain stage in series with a ratiometric attenuator. By implementing the attenuator ratiometrically, the gain may be compensated with reference to a ratio of component values. A limiting stage with an absolute reference may precede the gain stage, and a pair of detector cells may arranged at the inputs to the nulling circuit.

Abstract: A received signal strength indicator according to an aspect of the invention may include a gain calibration section including a calibration limiter, a calibration load unit and a comparison and adjustment unit. The calibration load unit is connected to output terminals of the calibration limiter, and generating an output differential voltage whose gain is a unit gain when a predetermined input differential voltage is input to the calibration limiter, and a comparison and adjustment unit comparing the input differential voltage with the output differential voltage, and adjusting an output of a variable current source included in the calibration limiter so that the input differential voltage becomes identical to the output differential voltage.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: A logarithmic linear variable gain CMOS amplifier includes first and second differential pairs of transistors forming a differential input, with each differential pair of transistors including a common source node. A pair of diode-connected load transistors is connected to the first and second differential pairs of transistors, and a third differential pair of transistors is connected to the pair of diode-connected load transistors. The third differential pair of transistors include respective gates connected together and in parallel to gates of the first and second differential pairs of transistors. First and second current mirrors are respectively connected to the common source nodes of the first and second differential pairs of transistors for programmably injecting respective bias currents thereto, with a sum of the respective bias currents remaining constant.

Abstract: A logarithmic detector circuit including a drive circuit to receive a modulated input signal and generate a buffered modulated signal, a signal shaping circuit coupled to the drive circuit and configured to shape a voltage range of the buffered modulated signal to generate a shaped modulated signal, and a detecting circuit to detect the shaped modulated signal to generate an output signal substantially proportional to a logarithm of an amplitude of the modulated input signal.

Abstract: The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

Abstract: A wireless communication system uses a transmission power detection circuit. The transmission power detection circuit has excellent linearity of detection output for transmission output power and can obtain detection output not having temperature dependence. The transmission power detection circuit has a rectifying detection part that includes plural amplifiers connected in series and obtains detection output by taking out rectified outputs from emitters of input transistors of amplifiers of individual stages and synthesizing them. A compensation voltage generating circuit has a dummy amplifier having a construction similar to the amplifiers constituting the rectifying detection part and a coefficient circuit that changes output of the dummy amplifier at a specified ratio, and generates voltage for compensating temperature characteristics.

Abstract: One embodiment of the present invention is directed to an apparatus for reducing errors affecting the intercept of a logarithmic device, the apparatus including a first switching device coupled to an input of the logarithmic device. The first switching device for switches the input of the logarithmic device between an input signal and a reference signal. The apparatus further includes a polarity switching device coupled to an output of the logarithmic device. The polarity switching device is configured to switch the polarity of an output signal of the logarithmic device when the logarithmic device is receiving one of the input signal and the reference signal. The apparatus further includes a low pass filter coupled to the polarity switching device.

Abstract: A continuous-time filter comprising at least one amplifier and at least one passive element. The amplifier comprises at least one input terminal and at least one output terminal and the passive element is positioned between the terminals. In addition the amplifier is provided with a transconductance gain. The filter comprises circuit means suitable for correlating the transconductance gain of the amplifier with the passive element.

Abstract: A demodulating logarithmic amplifier rectifies a radio frequency signal prior to amplification through progressive stages. A full wave linear or squaring rectifier receives a waveform signal at the input and provides a rectified signal that is proportional to an envelope or a square of the envelope of the waveform signal at the output. The rectified signal is then fed to a series of limiting amplifier stages where the signal is progressively amplified. After each individual amplifier stage, the partially amplified signal is passed through a voltage-to-current converter to create a current signal. All the current signals are subsequently summed to produce an amplified current output signal that is representative of the logarithm of the envelope of the input signal.

Abstract: A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.

Abstract: Fault detection circuitry is provided for a PWM driver responsive to a PWM input signal to produce a PWM output signal, and includes a first circuit producing a scaled switching signal as a scaled representation of the PWM input signal. A second circuit is configured to produce a combined switching signal as a combination of the PWM output signal and the scaled switching signal, and a third circuit is configured to convert the combined switching signal to an analog output signal indicative of one or more fault conditions associated with the PWM driver. A number of comparators may be included with each responsive to the analog output signal and to a different one of a corresponding number of different references voltages, to produce a fault signal indicative of a particular one of the one or more fault conditions.

Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as an inductor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

Abstract: A parallel-summation logarithmic amplifier is described that uses a novel topology of cascaded and parallel amplifiers to achieve extremely high bandwidth. Included in the topology is a unique delay matching scheme for logarithmic amplifiers that is amenable to fabrication in integrated circuit form. The result is flat group delay over broad frequency ranges and different power levels. The resulting log amplifier is suitable for radar applications and for use in high data rate fiber-optic networks. Also described is a unique design process that yields a set of amplifier gains that closely approximate a logarithm. Also described is the novel idea of using a parallel feedback amplifier (PFA) in piecewise-approximate logarithmic amplifiers. This innovation allows for the design of broadband amplifiers with significantly different gains and similar phase characteristics, which is extremely useful when designing high-frequency logarithmic amplifiers.

Abstract: A signal strength detecting device includes a logarithmic amplifier and an amplitude detector. A constant current source whose current is proportional to the absolute temperature is used as a current source for biasing the logarithmic amplifier. In contrast, a constant current source whose current is not proportional to the absolute temperature is used as a current source for biasing the amplitude detector. This makes it possible to solve a problem of a conventional signal strength detecting device of being unable to detect the signal strength of a received signal correctly because it employs a constant current source whose current is proportional to the absolute temperature as the current source for biasing the amplitude detector, and hence the collector current output from differential amplifiers constituting the amplitude detector can vary in response to the absolute temperature even if the signal strength of the received signal is kept constant.

Abstract: In order to provide a circuit arrangement (100) for generating and amplifying a DC signal, referred to as level voltage, whose value is essentially proportional to the logarithm of the voltage amplitude of the input signal, the circuit arrangement comprising an amplifier circuit having at least two amplifier stages (10; 20; 30), it is proposed that at least a differential amplifier stage (40), in particular non-negatively fed back, is arranged parallel to the last amplifier stage (30), particularly parallel to the collector circuits of the last amplifier stage (30), the differential amplifier stage (40) precedes at least a multiplier stage (50) for multiplying the output signals of the differential amplifier stage (40), for generating two differential amplifier output signals which are to be multiplied by each other, and alternatively to the differential amplifier (40), the collector currents of the transistors (36, 38) of the rectifier circuit (35) of the last amplifier stage (30) are used, and at least a cu

Abstract: To provide a circuit arrangement (100) and a method for generating and amplifying an amplitude-limited DC signal whose level voltage is substantially proportional to the logarithm of the voltage amplitude of an input signal, by which the level indication, i.e.

Abstract: A control signal is conditioned such that it produces a conditioned control signal that is the sum of two exponentially varying components. The resulting conditioned control signal, applied to an amplifier circuit, produces a gain that varies linearly in dB with changes in the voltage of the control signal.

Abstract: A multiple differential pair circuit is disclosed having a transconductance, gm, proportional to the bias current, I0, for any transistor technology. The transistors utilized to construct each of the differential transistor pairs in a multiple differential pair circuit operate in a non-exponential voltage-current (V-I) region. As multiple differential pair circuits are linearized, the effective transconductance, gm, becomes (i) linearly dependent on bias current, and (ii) insensitive to the voltage-current (V-I) characteristics of the utilized devices. Methods and apparatus are disclosed that provide a linear transconductance, gm, with respect to the bias current, I0, using differential pairs of transistors where each transistor operates in a non-exponential voltage-current (V-I) region, such as MOS transistors.

Abstract: A circuit and method for generating a generally logarithmic transfer function based upon switching signals. The circuit includes a plurality of transistors and a switch operatively connected to each transistor in the programmable set. A line is in communication with each switch for carrying switching signals thereto thereby selecting which of the transistors will contribute to the generally logarithmic function. Preferably, the circuit is a portion of a programmable gain amplifier, and a digital code controls the gain. The gain can be generally logarithmic as a result of which transistors which are selected to contribute to the generally logarithmic transfer function. For example, there may be a plurality of sets of transistors where the values of the transistors in each set are such that when all the transistors of the set are selected to contribute to the generally logarithmic gain, the set of transistors provides a gain having a value approaching m.

Abstract: An exponentiator circuit (24) is provided that includes a first transistor device, that includes a BJT (80) and a BJT (84) configured in a Darlington configuration, and a second transistor device that includes a BJT (88) and a BJT (92) also configured in a Darlington configuration. The first transistor device is coupled between a reference voltage and a summing node, while the second transistor device is coupled between an output node and a summing node. A programmable current iI is provided to the first transistor device and the second transistor device such that the base-to-emitter voltages of the two devices are provided at a different level. This results in the generation of a first current through the first transistor device and an output current through the second transistor device. An input current is provided at the summing node which is equivalent to the sum of the first current and the output current. The overall gain of the exponentiator circuit (24) is approximately exponential.

Abstract: Signal generating apparatus comprises a linear series of Hall-effect switches (44) arranged as a plurality of linear arrays in discrete probes (46a, 46b . . . 46n) which are butted end to end. Each switch is closed when in proximity of an actuating magnet (40) movable along the series of switches. In each array a resistance chain (66) is linked at intervals to the switches. Movement of the magnet along an array thereby gives a progressively changing voltage on an output line (5) from the resistance chain as a cumulative signal indicating the position of the magnet. When the magnet moves from one array to the succeeding array after generating a maximum cumulative signal from said one array, that signal is maintained by a latch connection (56) between the two arrays. A cumulative signal representing the magnet position relative to the complete series of switches can thus be generated.

Abstract: A logarithmic level detector that provides a very accurate level detector output signal that is greatly insensitive to temperature and process spread. The logarithmic level detector includes a weighted summed reference circuit which is subtracted from a level output signal of the cascade of limiting amplifiers so as to form a relative level detector output signal, and further compensation circuitry at input and output side, and an overall gain stabilizing circuit.

Abstract: A two stage operational amplifier circuit comprises a first stage (31) having an input (2, 4) and an output, and a second stage (33) having an input and an output (19). The second stage input is coupled to receive the first stage output. A feedback path (41, 45, 47, 51) is coupled between the output and the input of the second stage. The feedback path (41, 45, 47, 51) comprises a low-frequency compensation path (41, 45) and high-frequency compensation path (45, 47, 51). The feedback path (41, 45, 47, 51) is compensated such that the frequency response of the second output of the second stage is substantially 6 dB per octave throughout the high-frequency region.

Abstract: A circuit arrangement having a logarithmic transfer function between an input signal and an output signal in a predefined level range of the input signal circuit which has a very low power consumption and low circuit complexity, includes a first pair of amplifier elements, namely transistors, forming a first differential amplifier and a second pair of amplifier elements, namely transistors, forming a second differential amplifier. The first pair of transistors have their emitters connected to each other and to a first current source, their collectors connected to working impedances subdivided by respective taps, and their bases receive the input signal between them. The second pair of transistors have their emitters connected to each other and to a second current source, their collectors connected to the collectors of the first pair of transistors, respectively, and their bases cross-connected to the taps of the working impedances.

Abstract: Addition is performed by a capacitive coupling or resistive coupling. A quantizing circuit is realized by plurality of thresholding circuits receiving an analog input voltages. Subtraction in performed by two MOSs of anti-polarity inputted analog input voltages to gates.

Abstract: Addition is performed by a capacitive coupling or resistive coupling. A quantizing circuit is realized by plurality of thresholding circuits receiving an analog input voltages. Subtraction is performed by to MOSs of anti-polarity inputted analog input voltages to gates.

Abstract: AC coupling is effected by a feedback circuit that detects a DC component in the coupled signal, and adjusts a DC subtraction signal accordingly. In one embodiment, a digital signal processor (DSP) analyzes the coupled signal for a remaining DC component, and controls the subtraction signal. Use of a DSP allows dynamic control of parameters including AC cutoff frequency, gain, and transfer function. Another embodiment provides accurately phase matched AC coupling across two or more signal channels.

Abstract: A logarithmic amplifier circuit including a first triple-tail cell for rectifying an initial input signal to produce a first rectified output signal and a first amplified output signal, a second triple-tail cell for rectifying the first amplified output signal of the first triple-tail cell to produce a second rectified output signal and a second amplified output signal; and an adder for adding the first rectified output signal and the second rectified output signal. Each of the first and second triple-tail cells has first, second and third transistors whose emitters or sources are coupled together, said first and second transistors forming a differential pair. The differential pair and third transistor are driven by a single tail current. A base or gate of the third transistor are applied with ad c tuning voltage. Reduction of the circuit scale and total current consumption, low-voltage operation, and the logarithmic characteristics tuning can be realized.

Abstract: A logarithmic amplifier gain stage for supplying, in response to an instantaneous input signal, an output signal corresponding to a logarithmic value of the input signal. The gain stage includes a transistor amplifier having an input that receives the input signal and an intermediate output that supplies an intermediate output signal. A full-wave detector having an input coupled to the intermediate output of the transistor amplifier receives the intermediate output signal and supplies the output signal wherein the detector includes a rectifier comprising transistors having different effective emitter areas.

Abstract: A logarithmic amplification circuit is provided which is composed of a differential amplifier, a plurality of full-wave rectifiers including two half-wave rectifiers connected so as to have their input signals inverse in phase to each other and respectively receiving an output signal of the differential amplifier, and an adder for adding the output signals of the full-wave rectifier. Each of the half-wave rectifiers includes a differential transistor pair only one of which has an emitter resistor.

Abstract: A DMA control system continuously grants permission to access the I/O device and memory to continue data transfer in a cycle steal mode when there is a continuous stream of DMA requests from a number of I/O devices by producing a logical sum of the DMA requests.

Abstract: A logarithmic amplifier circuit is provided, which contains a differential amplifier, a first rectifier for rectifying an initial input signal and for generating a first rectified output signal, a second rectifier for rectifying an amplified output signal from the differential amplifier and for generating a second rectified output signal, and an adder for adding the first and second rectified output signals to produce an output signal having a logarithmic characteristic. The first and second rectifiers each is made of a triple-tail cell. The cell contains first, second and third emitter- or source-coupled transistors and a constant current source for driving the transistors. An input signal is applied across bases or gates of the first and second transistors, and a dc voltage is applied to a base or gate of the third transistor. An output current is outputted through the coupled collectors or drains of the first and second transistors or through the collector or drain of the third transistor.

Abstract: A logarithmic amplifying circuit with a reduced power dissipation and suitable for applying to an integrated circuit. The logarithmic amplifying circuit has cascade-connected differential amplifiers, a rectifier connected to each if the amplifiers and an adder for adding the output currents of the rectifiers. Each of the rectifiers has a differential pair composed of a plurality of transistors emitter-coupled or source-coupled, a constant current source for a tail current of the differential pair and an offset voltage source for superimposing a DC offset voltage on a differential input voltage to be supplied to the differential pair.

Abstract: In a logarithmic intermediate frequency amplifier circuit including first through M-th intermediate frequency amplifiers which are connected in cascade and first through M-th double balanced differential circuits which are connected to the first through the M-th intermediate frequency amplifiers, respectively, each of the first through the M-th double balanced differential circuits comprises primary, secondary, and tertiary differential circuits. The primary differential circuit includes a pair of transistors each of which is one of NPN and PNP types and which are connected to a first constant current source. The secondary differential circuit includes a pair of transistors each of which is another one of NPN and PNP types and which are connected to a second constant current source. The tertiary differential circuit includes a pair of transistors each of which is the other one of the NPN and the PNP types and which are connected to a third constant current source.

Abstract: A logarithmic amplifying circuit with a wide input dynamic range using cascade-connected differential amplifiers, a rectifier connected to each of the amplifiers and an adder for adding the output currents of the rectifiers. The rectifiers each have a quadritail cell which consists of a single tall current source and four transistors. The transistors are emitter-connected or source-connected and driven by the tail current source. The bases or gates of the first and second transistors of the quadritail cell are connected to respective terminals of a differential input pair of the rectifier. The collectors or drains of the first and second transistors are connected in common to one terminal of a differential output pair of the rectifier, and the collectors or drains of the third and fourth transistors are connected in common to the other output terminal of the rectifier.

Abstract: A C-MOS logarithmic IF amplifier is provided which comprises a plurality of IF amplifiers cascade-connected to each other through a first coupling capacitor, a plurality of rectifiers each receiving a signal from the corresponding one of the plurality of IF amplifiers through a second coupling capacitor different in capacity from the first coupling capacitor, and an adder for adding the output signals of these rectifiers to each other. The first and second coupling capacitors are preferable to be connected in series to cascade-connect those IF amplifiers therethrough. Each of the rectifiers is applied with an output signal of the corresponding one of the IF amplifier from the connection point of the corresponding first and second coupling capacitors.