Abstract: Internal to the transistor, an additional, direct connection is made from the internal collector to the external collector of the transistor by a fixed shunt inductance. The external power supply V.sub.s is applied to the transistor collector through an adjustable external shunt element. The adjustable external shunt element allows the user to finetune the impedance matching circuit such that the transformation ratio of the output matching circuitry is minimized.
Abstract: An integrated power device comprises a power transistor (26) and a plurality of sense transistors (38), (40), (42), (44), and (46). Sense transistors (38), (40), (42), and (44) are constructed around the periphery of the active area occupied by power transistor (26). Sense transistor (46) is located within the interior of the active area occupied by power transistor (26) and contact is made to the necessary source region (64) of transistor (46) using a second level of metal interconnect to form a source contact (74).
Type:
Grant
Filed:
January 4, 1993
Date of Patent:
April 18, 1995
Assignee:
Texas Instruments Incorporated
Inventors:
Joseph A. Devore, Ross E. Teggatz, Konrad Wagensohner
Abstract: A push-pull-type amplifier circuit has three current mirror circuits CM1, CM2, CM3 and transistors M6, M7 connected between a reference current supply I.sub.R and output transistors M2, M3 for controlling an idling current flowing through the output transistors M2, M3 so as to be proportional to a current flowing through the reference current supply I.sub.R so that the idling current will be stabilized irrespective of variations in a power supply voltage. An operational amplifier which incorporates the push-pull-type amplifier circuit as an output stage circuit is highly stable in operation, and can be designed in a simple arrangement without having to take into account power supply voltage variations.
Abstract: A circuit configuration includes a final control element being adjustable as a function of a control current, wherein the function is subject to certain fluctuations and variations. A constant current source supplies an output current being equally subject to the certain fluctuations and variations. A multiplier is connected between the constant current source and the final control element, for varying the current output by the constant current source by a factor being dependent on a control signal, and for delivering the current output by the constant current source to the final control element as the control current.
Type:
Grant
Filed:
July 18, 1994
Date of Patent:
March 28, 1995
Assignee:
Siemens Aktiengesellschaft
Inventors:
Artur Bardl, Manfred Lindner, Emil Navratil
Abstract: An audio mixer circuit on an integrated circuit chip performs a calibration operation on power up which calibrates out most of the offset voltages of the operational amplifiers used in the mixer. The calibration logic includes a shared calibrate circuit which provides timing signals to each operational amplifier and its associated calibration circuitry. The calibration operation is performed by digitally controlling and changing the bias current into each of the operational amplifiers until the offset voltage is compensated. A class A flip-flop circuit is used in the digital counter of the calibration circuitry to drive a current digital-to-analog converter.
Abstract: A signal processing circuit that is subject to signal chatter is provided with signal chatter-elimination circuitry. Prior signal processing circuitry included a peak voltage detector which received a data input signal and provided a peak voltage representation of the input signal and a threshold-comparator that provided a threshold-comparison signal of a first output voltage magnitude when the peak voltage representation was below a predefined threshold voltage and of a second output voltage magnitude when the peak voltage representation was above the predefined threshold voltage.
Abstract: An operational amplifier bias system provides input offset voltage trim current with minimum offset thermal drift. The bias system includes a bias generator that provides bias current to the op amp. Correction circuitry responsive to the bias current provides an input offset trim current that compensates for offset drift error with change in temperature. The correction circuitry includes a resistive element, an input current mirror responsive to the bias current for providing a reference current to the resistive element to provide a temperature coefficient conversion current having a predetermined temperature coefficient, and a voltage reference that sets the resistance of the resistive element.
Abstract: The complementary multiplexer includes a first pass-gate, formed from a single PMOS transistor, and a second pass-gate formed from a single NMOS transistor. The gates of the PMOS and NMOS transistors are connected directly to a select input line. No inversion of the select input signal is required. A compensation circuit is connected to outputs of the pass-gates for compensating any voltage differences between signals received through the first pass-gate as opposed to those received through the second pass-gate. Full CMOS and bi-CMOS implementations are described herein. An exclusive OR-gate circuit, incorporating a bi-CMOS implementation of the multiplexer, is also described herein.
Abstract: A toner depositing amount measuring apparatus for measuring the amount of toner deposited on a photosensitive drum includes a light source for irradiating the surface of the photosensitive drum with light and a photoelectric converting section for receiving the reflected light and converting the received reflected light into an electric signal. A logarithmic calculation is applied to the output signal of the photoelectric converting section in a logarithm-compressing section. The temperature characteristics of the logarithm-compressing section are compensated for in a temperature compensating section. The amount of the toner deposition is calculated in a toner depositing amount calculating section based on a difference between the data during non-deposition of the toner and the data during deposition of the toner, the data being obtained from the logarithm-compressing section.