Abstract: A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

Abstract: An arrangement and a method for improving the efficiency of a multistage switching amplifier using a resonant circuit element is presented. The multistage amplifier comprises a pre-driver amplifier, a final stage amplifier and a series L-C arrangement coupled between the pre-driver amplifier and the final stage amplifier. The series L-C arrangement forms a parallel L-C resonant circuit with a gate to source capacitor of an input transistor of the final stage amplifier. An oscillation of energy takes place between the gate to source capacitor of the input transistor of the final stage amplifier and the series L-C arrangement. This oscillation of energy provides the final stage amplifier with driving current and improves efficiency of the overall multistage amplifier arrangement.

Abstract: The mixer of a transmit chain of a wireless transmitter (such as the transmitter of a cellular telephone handset) is driven with low third harmonic in-phase (I) and quadrature (Q) signals. The low third harmonic I and Q signals have three or more signal levels, and transition between the these three or more signal levels at times such that each of the I and Q signals approximates a sine wave and has minimal third harmonic spectral components. In one example, reducing the third harmonic components of the I and Q signals simplifies design of amplifier stages of the transmitter and helps reduce receive band noise.

Abstract: An arrangement and a method for improving the efficiency of a multistage switching amplifier using a resonant circuit element is presented. The multistage amplifier comprises a pre-driver amplifier, a final stage amplifier and a series L-C arrangement coupled between the pre-driver amplifier and the final stage amplifier. The series L-C arrangement forms a parallel L-C resonant circuit with a gate to source capacitor of an input transistor of the final stage amplifier. An oscillation of energy takes place between the gate to source capacitor of the input transistor of the final stage amplifier and the series L-C arrangement. This oscillation of energy provides the final stage amplifier with driving current and improves efficiency of the overall multistage amplifier arrangement.

Abstract: An apparatus includes a processor and a device. The processor generates an output signal and a control signal. The device consumes power while operating in first and second states. The device consumes less power while in the first state than while in the second state. The processor: accounts for a transition time for the device to transition among a powered off state, the first state, and the second state; and generates the control signal based on the transition time. The device: in response to the control signal, transitions to the second state at a speed of periodicity of a periodic signal of the processor; subsequent to the transitioning to the second state, performs a function based on the output signal; and subsequent to performing the function, transitions from the second state to either the first state or the powered off state.

Abstract: There is disclosed a method and apparatus for generating an output signal comprising a replica of an input signal, comprising the steps of: generating a replica signal representing the low frequency content of the input signal; generating an error signal representing an error in the replica signal; combining the replica signal with the error signal to generate an output signal; and wherein the step of generating the error signal further includes the steps of: generating a delay signal being a delayed version of the input signal; and determining a difference between the output signal and the delay signal which difference is the error signal.

Abstract: The embodiments of the present circuit and method disclose a bridge rectifier and a driving circuit. The bridge rectifier having a first input, a second input, a first output, and a second output may comprise two high side diodes and two low side switches. The driving circuit may be coupled to the first input of the bridge rectifier and the second input of the bridge rectifier, and the driving circuit may be configured to provide a first driving signal and a second driving signal. The first driving signal may be coupled to a first low side switch and the second driving signal may be coupled to a second low side switch. The first driving signal may be limited to less than a first predetermined driving voltage and the second driving signal may be limited to less than a second predetermined driving voltage.

Abstract: A circuit for determining an average value of a quasiperiodic signal may include an integrator, a sample and hold circuit coupled to an output of the integrator, wherein the sample and hold circuit includes a sample and hold circuit output, a feedback path coupled to the sample and hold circuit output and configured to feedback the signal provided at the sample and hold circuit output as a feedback signal, a subtractor configured to form a difference signal representing the difference between the quasiperiodic signal and the feedback signal, wherein an output of the subtractor is coupled to an input of the integrator to thereby provide the difference signal to the input of the integrator.

Abstract: A method and apparatus is provided for standby voltage offset cancellation at inputs to a comparator within a receiver channel. Each of a first comparator input and second comparator input is isolated from an input signal such that each of the first and second comparator inputs attains a respective standby voltage level. A voltage level on one of the first and second comparator inputs is incrementally changed, while the output signal of the comparator is monitored. Upon detecting a state transition in the output signal of the comparator, the incremental changing of the voltage level on the one comparator input is stopped at a final voltage level setting. The final voltage level setting is stored in a computer memory for reference in setting of the voltage level at the one comparator input so as to compensate for the standby voltage offset at the inputs to the comparator.

Abstract: Exemplary embodiments of the invention disclose signal filtering. In an exemplary embodiment, a filter device may comprise a subtractor operably coupled between an input and an output and configured to receive an input signal comprising a desired component and at least one undesired frequency component. The filter device may further include a feedback loop configured to receive at least one of the input signal and an output signal from the subtractor and convey a feedback signal comprising at least one undesired component to the subtractor. Each undesired component of the feedback signal corresponds to an associated undesired component of the input signal. Furthermore, the subtractor subtracts the feedback signal from the input signal and convey the output signal.

Abstract: A start-up circuit for a high voltage power distribution circuit includes a transistor, a current source which generates ramped current, an operational amplifier which is connected between the current source and the transistor and controls the transistor, a capacitor which is fed the generated ramped current from the current source and is charged by the generated ramped current, the capacitor being connected to the non-inverting input of the operational amplifier, and a feedback capacitor connected from the transistor output to the non-inverting input of the operational amplifier, which is fed the generated ramped current from the capacitor and is discharged. The transistor is fully enabled when the feedback capacitor is fully discharged.

Abstract: Exemplary embodiments of the invention disclose signal filtering. In an exemplary embodiment, a filter device may comprise a subtractor operably coupled between an input and an output and configured to receive an input signal comprising a desired component and at least one undesired frequency component. The filter device may further include a feedback loop configured to receive at least one of the input signal and an output signal from the subtractor and convey a feedback signal comprising at least one undesired component to the subtractor. Each undesired component of the feedback signal corresponds to an associated undesired component of the input signal.

Abstract: A start-up circuit for a high voltage power distribution circuit includes a transistor, a current source which generates ramped current, an operational amplifier which is connected between the current source and the transistor and controls the transistor, a capacitor which is fed the generated ramped current from the current source and is charged by the generated ramped current, the capacitor being connected to the non-inverting input of the operational amplifier, and a feedback capacitor connected from the transistor output to the non-inverting input of the operational amplifier, which is fed the generated ramped current from the capacitor and is discharged. The transistor is fully enabled when the feedback capacitor is fully discharged.

Abstract: A circuit and method for producing an output voltage that replicates an input voltage. A circuit comprises an amplifier stage configured to amplify a difference between an input voltage and a feedback voltage. An output stage is configured to produce an output voltage equal to the input voltage. The output stage configured to be driven by the difference between the input voltage and the feedback voltage. The output stage further comprises a main supply current path configured to provide a first current from a main supply source, the first current providing at least a portion of the output voltage, and a current management circuit configured to provide a second current from an auxiliary supply source, the second current providing any remaining portion of the output voltage not provided by the first current.

Abstract: A robust decoder generates an output state from input signals related to the line-voltage signals of a three-phase power system, using a segment identification method based on zero-crossings derived from line-voltage difference signals. The robust decoder includes a basic decoder that provides a current output state based on the input signals, a state table that provides a presumed previous state based on the current output state of the basic decoder, a binary feed back loop including a state element for storing a previous output state, and a selector for providing the output state based on the stored previous output state and the presumed previous state. The robust decoder may be implemented as hardware or software in a digital power converter.

Abstract: The invention relates to a pulse shaping circuit for shaping electrical pulses driving an optical transmitter, e.g. a lased diode or an LED, and for providing electrical pulses having independently height and width-adjustable peaking at the edges thereof. The pulse shaping circuit of the present invention includes a high-pass RC filter with a differential output for providing transient electrical pulses from an input differential pulse, an adjustable voltage offset generating circuit, a differential amplifier for adjusting the width of the transient electrical pulses in dependence on the adjustable voltage offset, and a variable-gain current-steering amplifier for producing transient pulses with independently adjustable width and height.

Abstract: Input circuitry is provided for a high voltage operated radiation detector to receive pulses from the detector having a rise time in the range of from about one nanosecond to about ten nanoseconds. An integrator circuit, which utilizes current feedback, receives the incoming charge from the radiation detector and creates voltage by integrating across a small capacitor. The integrator utilizes an amplifier which closely follows the voltage across the capacitor to produce an integrator output pulse with a peak value which may be used to determine the energy which produced the pulse. The pulse width of the output is stretched to approximately 50 to 300 nanoseconds for use by subsequent circuits which may then use amplifiers with lower slew rates.

Abstract: One embodiment includes an apparatus comprising a closed loop feedback controller and a power output stage to couple to the closed loop feedback controller. The closed loop feedback controller and the power output stage are combined to form a single element.

Abstract: A DC offset cancellation circuit that is capable of canceling a DC offset voltage occurring between a pair of differential output signals of a differential amplification circuit, while preventing a signal waveform from being distorted due to accumulation of AC components and a photo-electric pulse conversion circuit that is capable of generating an electrical pulse signal that accurately reproduces a rise timing and a fall timing of an optical pulse signal by canceling the DC offset voltage are provided. A photo-electric pulse conversion circuit is provided with a photodiode, an I-V conversion circuit, a first differential amplification circuit having a DC offset cancellation circuit, a second differential amplification circuit, a reference voltage generation circuit, and a comparison circuit.

Abstract: A circuit including a first sensitive node, a first component connected between the first sensitive node and a first terminal of a first switch, said first switch controlled by a first control signal variable between a supply voltage level and a second voltage level, and a second switch including a first terminal connected to the first terminal of said first switch, and a second terminal connected to a clean voltage supply, said second switch controlled to connect the first node of said first switch to said clean voltage supply when said first switch is in a non-conducting state.

Abstract: In a method and system for controlling a device coupled to an information handling system, an object is defined to include a hardware and software component having a corresponding hardware operating state and a software operating state. The hardware component is operable to receive at least one hardware input, which is indicative of a target hardware operating state. The software component is operable to receive at least one software input, which is indicative of a target software operating state. A coordination component is included in the software component to receive the hardware and software inputs, and control the operating state of the device in response to the target hardware operating state and the target software operating state.

Abstract: High-gain synchronizer circuitry and methods are provided that reduce the meta-stable resolve time of a synchronizer circuit. The high-gain synchronizer is made up of high-gain latch circuits. The high-gain latch circuits are made up of a series of inverters that at least initially increase in size and that are connected in a closed loop. In accordance with the invention, the time that the high-gain synchronizer remains in the meta-stable state is minimized through the use of the high-gain latch circuits.

Abstract: Method and system are disclosed for providing an improved linearity Gilbert mixer. The Gilbert mixer of the present invention includes a conventional mixer core coupled to a high linearity, multistage amplifier. The multistage amplifier includes two or more transistor stages connected together in a global feedback arrangement. The global feedback provides a greater loop gain for the amplifier than the local feedback arrangement, thereby increasing the linearity of the amplifier. In addition, having more than one transistor stage in the amplifier serves to increase the isolation of the RF input signal from the LO input signal. Furthermore, by providing parallel output stages in the multistage amplifier, several mixer cores may be driven from the same source while sharing the feedback mechanism.

Abstract: An offset correction analogic circuit capable of compensating the offset of a digital baseband is described. The circuit comprises analog means to receive an output differential signal issued from a differential signal path. The differential signal path may be a baseband filter as used in digital communication systems. The baseband filter inputs an input differential signal having an offset to be compensated. The output differential signal is fed into an analog integrator to generate a pulsed signal either on a first output line or on a second output line according to the polarity of the output differential signal. The pulsed signal is then integrated into a switched capacitor and a differential compensation offset signal is issued. The frequency of the pulsed signal is preferably proportional to the voltage value of the output differential signal. The compensation offset signal may be summed with the input differential signal into a summing circuit.

Abstract: A feedback control system and method thereof are provided. The feedback control method includes (a) comparing the level of a reference signal with the levels of first and second signals, (b) if the levels of the first and second signals are lower than the level of the reference signal, generating a first control signal, if the levels of the first and second signals are higher than the level of the reference signal, generating a second control signal, and if the level of the reference signal is between the level of the first signal and the level of the second signal, generating a third control signal, (c) controlling the level of an output signal in response to the first through third control signals, and (d) outputting the controlled output signal and generating the first signal and the second signal.

Abstract: An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure.

Abstract: A transition delay circuit having an input terminal and an output terminal is disclosed. According to one embodiment, the transition delay circuit also includes a first MOS capacitor, a second MOS capacitor, and a delay circuit. The first MOS capacitor includes a first terminal connected to the input terminal of the transition delay circuit and a second terminal that is connected to the output terminal of the transition delay circuit. The second MOS capacitor includes a first terminal connected to the input terminal of the transition delay circuit and a second terminal that is connected to the output terminal of the transition delay circuit. The second MOS capacitor has a different polarity than the first MOS capacitor. The delay circuit includes a first terminal connected to the input terminal of the transition delay circuit and a second terminal that is connected to the output terminal of the transition delay circuit.

Abstract: A circuit for controlling an electronic semiconductor switching device to limit the in-rush current when an expansion board is plugged into an electronic system. An integrated thin-film capacitor is used in a high-voltage feedback circuit by attenuating the output voltage, which can be substantially greater than the breakdown voltage of the capacitor, with an integrated voltage divider. An adequate slew rate is obtained using a low capacitance by providing a high-impedance internal feedback node that is coupled to the gate of a power FET with a voltage buffer.

Abstract: The invention relates to a balanced circuit arrangement for converting an asymmetric analogous input signal (S1) into a symmetrical output signal (S2, S3). A first amplifier (2) is provided, whereby the non-inverting input thereof is connected to the analogous input signal (S1) and the output signal (S2) thereof is fed back to the inverting input thereof in a negative feedback. Moreover, a second amplifier (3) is provided, whereby the non-inverting input thereof is connected to ground, the inverting input thereof is connected to the output signal (S2) of the first amplifier (2) by means of a series resistor (R2) and the output signal (S3) thereof is fed back to the inverting input thereof in a negative feedback and by means of a negative feedback resistor (R1). The negative feedback resistor (R1) and the series resistor (R2) are provided with the same resistance value. The aim of the invention is to process higher maximum levels of the source signal and to suppress noises of the second amplifier.

Abstract: A multi-path unity gain buffer circuit and method are implemented in a slew amplifier. The multi-path unity buffer has a high frequency signal path and a low frequency signal path. The high frequency signal path has a differential amplifier powered for providing a high frequency, low accuracy buffering operation. The low frequency signal path is coupled to the high frequency signal path. The low frequency signal path has an operational amplifier powered to provide a low frequency, high bandwidth buffering operation. An output of the operational amplifier is fed back to an input of the operational amplifier through a current varying element that varies current levels of the input of the operational amplifier to remove a level shift of an output signal of the differential amplifier.

Abstract: A DC offset cancellation circuit that is capable of canceling a DC offset voltage occurring between a pair of differential output signals of a differential amplification circuit, while preventing a signal waveform from being distorted due to accumulation of AC components and a photo-electric pulse conversion circuit that is capable of generating an electrical pulse signal that accurately reproduces a rise timing and a fall timing of an optical pulse signal by canceling the DC offset voltage are provided. A photo-electric pulse conversion circuit is provided with a photodiode, an I-V conversion circuit, a first differential amplification circuit having a DC offset cancellation circuit, a second differential amplification circuit, a reference voltage generation circuit, and a comparison circuit.

Abstract: An amplifier stage for a buffer with negative feedback includes an input stage having an input terminal, an output terminal, a first and a second supply terminal, a biasing branch, a first and a second balancing branch each comprising an active transistor for supplying, at the output terminal, a current depending on the current difference in the first and second balancing branches. The biasing branch and the first and second balancing branches are connected in parallel between the first and second supply terminals. The input terminal divides the biasing branch into two input branches having a constant-current generator. Each active transistor is connected to a corresponding current generator for receiving a control voltage correlated with a voltage at the terminals of the current generator.

Abstract: An apparatus including a driver and an adjustment circuit. The driver circuit may be configured to generate an output signal in response to a clock input signal and an adjustment signal. The adjustment circuit may be configured to generate the adjustment signal in response to the output signal. The adjustment signal may be configured to correct a duty cycle of the output signal.

Abstract: A multi-stage, low-offset, fast-recovery, comparator system and method for: reducing the input offset voltage of the zeroing amplifier by a factor essentially equal to gain of the zeroing amplifier; reducing the input offset voltage of the combined main and zeroing amplifiers by a factor essentially equal to the product of the gains of the main and zeroing amplifiers; and amplifying the input signal to the amplification stage in accordance with the gain of the main amplifier to generate an amplified high-resolution signal.

Abstract: The common-mode feedback circuit generates currents representing the output voltages of a fully differential amplifier, and sums these current to produce a summation current. Based on the comparison of the summation current to a reference current, the common-mode feedback circuit generates a feedback voltage for stabilizing the fully differential amplifier.

Abstract: A leakage current correcting circuit for reducing a leakage current flowing into an output of a circuit in a high impedance state. The configuration includes a correcting unit having a current detecting circuit for detecting a leakage current and outputting a current equal to a detected leakage current, and a current supply circuit for receiving the output current from the current detecting circuit as an input and causing a current for offsetting the leakage current flowing into the output of the circuit in a high impedance state.

Abstract: An integrated circuit has a first circuit section and a second circuit section. The first circuit section has a local ground and is coupled to an external ground of a power supply for the first circuit section. The first circuit section adds an offset potential to the local ground potential when the first circuit section is on, due to an IR drop between the local ground and the external ground. The second circuit section has a signal-generating device and an offset correction circuit. The signal-generating device is referenced to the local ground potential and provides an output signal related to an input signal applied thereto. The offset correction circuit subtracts an offset adjust value from one of the input signal and the output signal to reduce offset error in the output signal caused by switching the first circuit section on and off.

Abstract: A circuit arrangement, in particular in DECT systems, for the regeneration of an input signal containing characteristic digital data sequences with N>1 allowed discrete values per digital position, having conversion means that produce a regenerated digital output signal from the comparison of the input signal with at least N−1 reference level, at least one integration element for obtaining the at least one N−1 reference level by integration of the segments of the input signal consisting of the characteristic data sequences, a drivable switching means for the activation or, respectively, deactivation of the integration of the input signal, a checking means that respectively activates the integration process by driving the switching apparatus at the beginning of a characteristic data sequence in the signal curve and, when the end of the data sequence is recognized, deactivates it again in order to avoid a shifting of the at least N−1 reference levels, as well as at least one delay elem

Abstract: A method and apparatus for changing the open-loop frequency response of an amplifier in a line driver when the load to the line driver is removed. The load is detected by measuring the current to the load. When the current falls below a predetermined amount, the load is assumed to be disconnected and the open-loop frequency response of the amplifier is changed to shift a dominant pole of the line driver to a sufficiently low frequency to ensure stability of the line driver.

Abstract: The AGC circuit and method especially applicable in circuits where fast response and stability of the system is necessary, such as where input signals are speech patterns. A gain feedback loop repeatedly adapts the gain and a long term average energy E.sub.mean of the output signal until it approaches a predetermined level. In each pass through the gain feedback loop the long term average energy E.sub.mean is increased by a gain compensation parameter directly proportional to a gain change, thereby rapidly adapting the long term average energy E.sub.mean to converge to the predetermined level.

Abstract: An electric circuit having a switchable feedback branch switchable between a first feedback state, in which the circuit arrangement has a frequency response that is stable with respect to an oscillation tendency, and a second feedback state, in which the circuit arrangement has a frequency response that is unstable with respect to an oscillation tendency. The circuit includes a switchable frequency response compensation circuit which during the first feedback state of the feedback branch can be controlled to an ineffective state and during the second feedback state of the feedback branch can be controlled to an effective state, and in the effective state causes such compensation of the frequency response of the circuit arrangement in the second feedback state that the circuit arrangement in the second feedback state remains stable with respect to an oscillation tendency.

Abstract: A signal processor utilizes a globally nonlinearly coupled array of nonlinear dynamic elements. In one embodiment of the invention, these elements take the form of bistable overdamped oscillators. The processor exploits the phenomenon of stochastic resonance to amplify a weak periodic signal embedded in noise. In this signal processor, a system or plurality of nonlinearly coupled overdamped oscillators is subject to a weak periodic signal embedded in a noise background. For communication or detection applications, this weak signal component is the signal of interest. A reference oscillator is chosen from the plurality of overdamped oscillators, and is given a time scale for relaxation that is longer than the remaining oscillators. The output of the reference oscillator is analyzed for signal processing purposes in response to the signal and noise.

Abstract: A simple semiconductor circuit by which analog data or multilevel data can be fetched and stored. The circuit receives a first signal and converts the first signal into a second signal composed of multilevel. The second signal is fed back to the circuit. The circuit is constituted of a first circuit which converts the first signal into a signal group composed of multiple quantized signals and second circuit which converts the signal group into the second signal. In addition, the first or/and second circuits are constituted of one or more neuron MOS transistors.

Abstract: The apparatus and the method representing an improved power management system are disclosed. The apparatus incudes a feedback control system with a delay element. The delay element introduces the oscillation frequency outside the input frequency band into the feedback control system. Therefore, the apparatus emulates a very efficient pulse width modulator (PWM) with a feedback. The apparatus additionally includes a pulse shaper amplifier that squares the pulse of the output signal.

Abstract: In a differential circuit including first and second transistors, a constant current circuit causes a constant current to flow through the first transistor. A variable current circuit causes a variable current to flow through the second transistor. A differential input voltage is given to drive the first and the second transistors and to produce an output signal in the form of an output current which may be either a differential output current across two output electrodes or a variable output current flowing through an output electrode. Each of the first and the second transistors may be bipolar transistors or MOSFET's. A relationship between the differential input voltage and the output signal is specified by a peculiar characteristic dependent on the bipolar transistors or the MOSFET's. Therefore, the differential circuit may be incorporated in an LSI circuit.

Abstract: Briefly, in accordance with one embodiment of the invention, a circuit includes: at least one differential amplifier. The differential amplifier is coupled in a circuit configuration so that the differential output voltage signal of the differential amplifier circuit includes a scalable second-order harmonic component of the differential input voltage signal applied to the differential amplifier circuit. Briefly, in accordance with another embodiment of the invention, a method of applying a differential input voltage signal to a differential amplifier circuit to produce a differential output voltage signal includes the step of: driving the differential amplifier circuit so that the differential output voltage signal of the differential amplifier circuit includes a second-order harmonic component of the differential input voltage signal.

Abstract: An analog front end for signal processing circuit such as a hard-disk data read channel having a calibration circuit for canceling DC offset is described. First, the DC offset is cancelled from a positive phase input to an A/D converter (ADC). Second, a DC offset is cancelled separately from a negative phase input to the A/D converter. The combined positive and negative phases form an amplified analog signal that is used as the differential input to the A/D converter. Finally, the DC offset in a path that encompasses the system analog input through the system digital output is cancelled. Controlling the buffer amplifier bias makes trimming unnecessary. It also enables faster calibration. Further, the two differential phase lines, i.e., the positive phase line and the negative phase line, are each calibrated in turn. As such, a common calibration circuit may be used, thereby avoiding circuit duplication.

Abstract: The invention exploits the phenomenon of stochastic resonance in a nonlinear dynamic system to enhance the system's response to a weak periodic signal locally corrupted by background noise. The invention is designed to enhance the signal-to-noise ratio (SNR) in the system's output power spectrum at the periodic signal's frequency. This technique utilizes an array of nonlinear dynamic elements whose individual outputs are specifically coupled to other array elements. The coupling is found to substantially enhance the output SNR over what would be expected from a signal processor based upon a single such element. This principle has the potential to substantially enhance the performance of arrays of nonlinear devices; in fact, the nonlinear array can be expected to yield an output SNR that is very close to that obtainable by an array of ideal linear devices, so that the coupling actually "linearizes" the nonlinear system.

Abstract: An impedance multiplier circuit comprises an input impedance having a certain value of impedance and a circuit coupled to this input impedance for multiplying its value by a multiplication factor. This multiplying circuit comprises a first and a second voltage follower amplifier and a first and a second scaling impedance. The input impedance is coupled between the input of the first voltage follower amplifier and the output of the second voltage follower amplifier with the first and second scaling impedances establishing a voltage division between the output of the first voltage follower amplifier and the input of the second voltage follower amplifier. In this way, the second voltage follower amplifier provides active negative feedback, and effectively multiplies the input impedances's impedance by a factor of one plus the quotient of the second scaling impedance to the first scaling impedance.

Abstract: A highly stable linear integrated circuit amplifier (11) is incorporated in a circuit (10) employing transformer (18) feedback providing thermal gain stability determined solely by the transformer turns ratio.