Abstract: Systems, devices, computer-implemented methods, and computer program products to facilitate contactless screening of a qubit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a scanner component that establishes a direct microwave coupling of a scanning probe device to a qubit of a quantum device. The computer executable components can further comprise a parameter extraction component that determines qubit frequency of the qubit based on the direct microwave coupling.

Abstract: Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.

Abstract: A superconducting circuit is disclosed for fast digital readout of on-chip diagnostics in an array of devices in an integrated circuit. The digital readout comprises a digital RSFQ multiplexer to select the readout channel. This permits a large number of devices to be tested with a minimum of input and output lines. The devices may comprise digital devices (such as elementary RSFQ cells), or analog devices (such as inductors, resistors, or Josephson junctions) with a SQUID quantizer to generate a digital signal. The diagnostic array and the digital multiplexer are preferably configured to operate as part of the same integrated circuit at cryogenic temperatures.

Abstract: A tri-stable storage loop useful in reciprocal quantum logic (RQL) gate circuits and systems has control and signal input lines. When alternating stable current storage states are induced in the storage loop by an alternating input provided to the control input line, provision of a positive SFQ pulse on the signal input line while the storage loop stores a positive current changes the storage loop from alternating between a positive-current state and a null-current state to alternating between a negative-current state and the null-current state, and provision of a negative SFQ pulse on the signal input line while the storage loop stores a negative current changes the storage loop from alternating between the negative-current state and the null-current state to alternating between the positive-current state and the null-current state.

Abstract: A technique relates to a microwave device. A pump resonator, at a first pump resonator end, is connected to both a dispersive nonlinear element and a first stub. The pump resonator, at a second pump resonator end, is capacitively coupled to a pump port, where the first stub is terminated in an open circuit. A quantum signal resonator, at a first quantum signal resonator end, is connected to both the dispersive nonlinear element and a second stub. The quantum signal resonator, at a second signal resonator end, is capacitively coupled to a signal port, where the second stub is connected to ground.

Abstract: A technique relates to qubit drive and readout. A first lossless microwave switch is connected to a quantum system. A second lossless microwave switch is connectable to the first lossless microwave switch. A quantum-limited amplifier is connectable to the second lossless microwave switch.

Abstract: A probabilistic digitizer for extracting information from a Josephson comparator is disclosed. The digitizer uses statistical methods to aggregate over a set of comparator readouts, effectively increasing the sensitivity of the comparator even when an input signal falls within the comparator's gray zone. Among other uses, such a digitizer may be used to discriminate between states of a qubit.

Abstract: A mechanism relates a superconductor circuit. A ? circuit includes a first node connecting a Purcell capacitor to a qubit coupling capacitor, a second node connecting the Purcell capacitor to a readout coupling capacitor, and a third node connecting the qubit coupling capacitor to the readout coupling capacitor. A qubit is connected to the first node and has a qubit frequency. A readout resonator connects to the third node combining with the Purcell capacitor to form a filter. Capacitance of the Purcell capacitor is determined as a factor of the qubit frequency of the qubit and blocks emissions of the qubit at the qubit frequency. Capacitance of the Purcell capacitor causes destructive interference, between a first path containing Purcell capacitor and a second path containing both the qubit coupling capacitor and readout coupling capacitor, in order to block emissions of the qubit at the qubit frequency to the external environment.

Abstract: Methods and apparatuses are provided for controlling the state of a qubit. A qubit apparatus includes a qubit and a load coupled to the qubit through a filter. The filter has at least a first pass band and a first stop band. A qubit control is configured to tune the qubit to alter an associated transition frequency of the qubit from a first frequency in the first stop band of the filter to a second frequency in the first pass band of the filter.

Abstract: Methods and apparatuses are provided for storing a quantum bit. One apparatus includes a first phase qubit, a second phase qubit, and a common bias circuit configured to provide a first bias to the first phase qubit and a second bias to the second phase qubit, such that noise within the first bias is anti-correlated to noise within the second bias.

Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.

Abstract: A superconducting integrated circuit, comprising a plurality of superconducting circuit elements, each having a variation in operating voltage over time; a common power line; and a plurality of bias circuits, each connected to the common power line, and to a respective superconducting circuit element, wherein each respective bias circuit is superconducting during at least one time portion of the operation of a respective superconducting circuit element, and is configured to supply the variation in operating voltage over time to the respective superconducting circuit element.

Abstract: Systems and methods are provided for reading an associated state of a qubit. A first soliton is injected along a first Josephson transmission line coupled to the qubit. A velocity of the first soliton is selected according to a physical length of the qubit and a characteristic frequency of the qubit. A second soliton is injected at the selected velocity along a second Josephson transmission line that is not coupled to the qubit. A delay associated with the first soliton is determined relative to the second soliton.

Abstract: One embodiment of the invention includes a quantum processor system. The quantum processor system includes a first resonator having a first characteristic frequency and a second resonator having a second characteristic frequency greater than the first characteristic frequency. A qubit cell is coupled to each of the first resonator and the second resonator. The qubit cell has a frequency tunable over a range of frequencies including the first characteristic frequency and the second characteristic frequency. A classical control mechanism is configured to tune the frequency of the qubit cell as to transfer quantum information between the first resonator and the second resonator.

Abstract: A pressure detection apparatus (30) detects, among a plurality of superconductor thin films (11 to 14) having different critical pressures at which a transition from a superconductor to an insulator occurs, the superconductor thin films (12 to 14) that have undergone the transition to the insulator with ammeters (242, 252, 262); and to detect, as an internal pressure of a housing (10), the maximum critical pressure among the critical pressures of the detected superconductor thin films (12 to 14).

Abstract: One embodiment of the invention includes a quantum processor system. The quantum processor system includes a first resonator having a first characteristic frequency and a second resonator having a second characteristic frequency greater than the first characteristic frequency. A qubit cell is coupled to each of the first resonator and the second resonator. The qubit cell has a frequency tunable over a range of frequencies including the first characteristic frequency and the second characteristic frequency. A classical control mechanism is configured to tune the frequency of the qubit cell as to transfer quantum information between the first resonator and the second resonator.

Abstract: The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (Ic1) and the second Josephson junction having a second critical current (Ic2); providing a working current to the first Josephson junction, the working current transmitting to the second Josephson junction through the series of the Josephson junctions; wherein the working current is sufficiently high to trigger the second Josephson junction while sufficiently low to not disturb super-conductivity of the series of intermediate Josephson junctions.

Abstract: The disclosure generally relates to a method and apparatus for providing high-speed, low signal power amplification. In an exemplary embodiment, the disclosure relates to a method for providing a wideband amplification of a signal by forming a first transmission line in parallel with a second transmission line, each of the first transmission line and the second transmission line having a plurality of superconducting transmission elements, each transmission line having a transmission line delay; interposing a plurality of amplification stages between the first transmission line and the second transmission line, each amplification stage having an resonant circuit with a resonant circuit delay; and substantially matching the resonant circuit delay for at least one of the plurality of amplification stages with the transmission line delay of at least one of the superconducting transmission lines.

Abstract: A fluxonic device including a closed loop transmission line; an additional transmission line and a junction at which the closed loop transmission line and the additional transmission line meet. An apparatus including a fluxon container for containing one or more fluxons; a fluxon interface along which a fluxon can propagate; a junction where the fluxon container and fluxon interface meet; and a controller for controlling a fluxon at the junction. An electromagnetic radiation generator comprising: a fluxon transmission line having a length, a depth and a width and including a perturbation in the length-wise direction; a mechanism for applying a driving electric current in a depth-wise direction; and a magnetic field generator for generating a magnetic field in a width-wise direction.

Abstract: In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding.

Abstract: Objects of the present invention are to provide an integration circuit which produces no integration leak so that the bit accuracy is improved in a sigma-delta modulation circuit or a delta modulator circuit, which is based on a single flux quantum circuit that uses a flux quantum as an information carrier, and to provide a method for reducing thermal noise and quantization noise. According to the present invention, an integration circuit is formed by Josephson junctions and an inductor to reduce the integration leak, and a plurality of modulator circuits are connected to one another so as to add up each output. As a result, it is possible to reduce the influence of thermal noise exerted upon the bit accuracy, the thermal noise having no correlativity to one another.

Abstract: A control system architecture for quantum computing includes an array of qubits, which is divided into a plurality of sub-arrays based on a first direction and a second direction, the second direction intersecting the first direction, a plurality of control lines each coupled to a corresponding sub-array of qubits in the first directions a plurality of enable/unenable lines each coupled to a corresponding sub-array of qubits in the second direction, a controls signal source that generates a control signal, wherein the control lines are used to apply the control signal commonly to one or more sub-arrays of qubits in the first direction, an enable/unenable signal source that generates a enable signal, wherein the enable/unenable lines are used to apply the enable signal independently to the corresponding sub-array of qubits in the second direction to set a bias point of each qubit of the corresponding sub-array of qubits in the second direction between a first position, in which the qubit is unenabled and not r

Abstract: Supercooled electronics often use Rapid Single Flux Quantum (RSFQ) digital circuits. The output voltages from RSFQ devices are too low to be directly interfaced with semiconductor electronics, even if the semiconductor electronics are cooled. Techniques for directly interfacing RSFQ digital circuits with semiconductor electronics are disclosed using a novel inverting transimpedance digital amplifier in conjunction with a non-inverting transimpedance digital amplifier to create a differential transimpedance digital amplifier that permits direct interfacing between RSFQ and semiconductor electronics.

Abstract: A single electron-transistor is used to read out charge states of two coupled qubits formed by two Cooper pair boxes. Detection is made about a gate voltage shift of the peak of the current that flows in the single electron transistor in accordance with the charge states. Since the current peak position varies depending on the particular charge state, all four charge states can be independently measured, or read out.

Abstract: Objects of the present invention are to provide an integration circuit which produces no integration leak so that the bit accuracy is improved in a sigma-delta modulation circuit or a delta modulator circuit, which is based on a single flux quantum circuit that uses a flux quantum as an information carrier, and to provide a method for reducing thermal noise and quantization noise. According to the present invention, an integration circuit is formed by Josephson junctions and an inductor to reduce the integration leak, and a plurality of modulator circuits are connected to one another so as to add up each output. As a result, it is possible to reduce the influence of thermal noise exerted upon the bit accuracy, the thermal noise having no correlativity to one another.

Abstract: A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions defines a different island. An ancillary device is coupled to the first qubit. In a first example, the ancillary device is a readout mechanism respectively capacitively coupled to a first and second island in the plurality of islands of the first qubit by a first and second capacitance. Quantum nondemolition measurement of the first qubit's state may be performed. In a second example, the ancillary device is a second qubit. The second qubit's first and second islands are respectively capacitively coupled to the first and second islands of the first qubit by a capacitance. In this second example, the coupling is diagonal in the physical basis of the qubits.

Abstract: A first qubit having a superconducting loop interrupted by a plurality of Josephson junctions is provided. Each junction interrupts a different portion of the superconducting loop and each different adjacent pair of junctions in the plurality of Josephson junctions defines a different island. An ancillary device is coupled to the first qubit. In a first example, the ancillary device is a readout mechanism respectively capacitively coupled to a first and second island in the plurality of islands of the first qubit by a first and second capacitance. Quantum nondemolition measurement of the first qubit's state may be performed. In a second example, the ancillary device is a second qubit. The second qubit's first and second islands are respectively capacitively coupled to the first and second islands of the first qubit by a capacitance. In this second example, the coupling is diagonal in the physical basis of the qubits.

Abstract: A Superconducting Quantum Interference Device (SQUID) is disclosed comprising a pair of resistively shunted Josephson junctions connected in parallel within a superconducting loop and biased by an external direct current (dc) source. The SQUID comprises a semiconductor substrate and at least one superconducting layer. The metal layer(s) are separated by or covered with a semiconductor material layer having the properties of a conductor at room temperature and the properties of an insulator at operating temperatures (generally less than 100 Kelvins). The properties of the semiconductor material layer greatly reduces the risk of electrostatic discharge that can damage the device during normal handling of the device at room temperature, while still providing the insulating properties desired to allow normal functioning of the device at its operating temperature. A method of manufacturing the SQUID device is also disclosed.

Abstract: A clock recovery circuit (10) for a superconductor system that enables the phase of a system clock to be instantaneously reset without any pulse interaction. The clock recovery circuit (10) includes a Josephson transmission line oscillator loop (14) of length 2T, where T is equal to one clock period. First and second data inputs (16, 18) are for injecting a data pulse onto the oscillator loop (14). A pulse generator (24) is for injecting an initial clock pulse onto the oscillator loop (14) that is output as periodic clock signals. An output tap (12) is for outputting the data pulse from one of the first and second data inputs (16, 18), and the periodic clock signals in the absence of the data pulse. When the data pulse is input on one of first and second output taps (32, 34), the clock phase is instantaneously reset.

Abstract: An on-chip current regulator for a superconducting logic circuit isolates the superconducting logic circuit from external noise, reduces the effects of process fluctuations on the performance of the logic circuit and significantly reduces total circuit power requirements. The on-chip current regulator in accordance with the present invention includes one or more hysteretic Josephson junctions each connected in parallel with a resistor forming a resistively shunted junction (RSJ) or includes a self-shunting junction. One RSJ may be coupled between an off-chip current regulator and the hysteretic Josephson junction that functions as a current limiting resistor and provides improved isolation from external noise.

Abstract: A single flux quantum (SFQ) pulse is generated (502) by injecting a superconductor output signal as a first signal at a “start” input (108) coupled to a superconductor delay element (104). The SFQ pulse is reflected (504) back and forth between first and second superconductor reflectors (102, 106) coupled to opposite ends of the superconductor delay element, thereby generating a time-disperse plurality of SFQ pulses at an output (110) coupled to the superconductor delay element. Thereafter, a second signal is input at a “stop” input (112) coupled to one of the first and second superconductor reflectors, thereby interrupting (506) the reflecting of the SFQ pulse at the one of the first and second superconductor reflectors, thus ending the generating of the time-disperse plurality of SFQ pulses at the output.

Abstract: A method for fabricating a closed-form Josephson junction includes etching the inner shape of the closed-form junction on the chip, depositing a negative photoresist material over the etched chip, and flood exposing the backside of the chip with ultraviolet radiation. The photoresist is developed and then baked onto the chip. The baked photoresist serves as a mask for subsequent etching of the exterior of the closed-form Josephson junction. A shaped Josephson junction is fabricated with junction widths between about 0.1 &mgr;m and about 1 &mgr;m and an inner diameter ranging between about 1 &mgr;m and about 1000 &mgr;m.

Abstract: The problem of the disclosed technology is as follows. Although a single flux quantum circuit can fabricate a high-speed sequential circuit with ease, the initialization of the circuit is required for guaranteeing the normal operation of the circuit. However, a prior-art circuit has no initializing function, or requires the restructuring of another logic system. For solving the foregoing problem, one Josephson junction is inserted to a flux quantum storage inductor constituting the existing logic circuit, so that a pulse for performing the circuit initialization is injected to the connection point by means of a comparator.

Abstract: A Josephson junction transmission line (50) for transmitting single flux quantum pulses. The transmission line (50) includes a current source (53), a plurality of isolation inductors (52, 54) electrically coupled in series along the transmission line (50), and a plurality of Josephson junction circuits (60, 70) electrically coupled in parallel along the transmission line (50). Each of the Josephson junction circuits (60, 70) includes only a Josephson junction (62, 72) and a parasitic inductor (64, 74) coupled in series. The Josephson junction circuits (60, 70) do not include a damping resistor in order to reduce timing uncertainty and to enhance propagation speed.

Abstract: A Josephson junction transmission line (50) for transmitting single flux quantum pulses. The transmission line (50) includes a current source (53), a plurality of isolation inductors (52, 54) electrically coupled in series along the transmission line (50), and a plurality of Josephson junction circuits (60, 70) electrically coupled in parallel along the transmission line (50). Each of the Josephson junction circuits (60, 70) includes only a Josephson junction (62, 72) and a parasitic inductor (64, 74) coupled in series. The Josephson junction circuits (60, 70) do not include a damping resistor in order to reduce timing uncertainty and to enhance propagation speed.

Abstract: The problem of the disclosed technology is as follows. Although a single flux quantum circuit can fabricate a high-speed sequential circuit with ease, the initialization of the circuit is required for guaranteeing the normal operation of the circuit. However, a prior-art circuit has no initializing function, or requires the restructuring of another logic system.

Abstract: A superconductor circuit (50) for providing active timing arbitration between SFQ pulses. The superconductor circuit (50) includes a first superconducting transmission line (52) having at least one inductor (54) for transmitting first input pulses, and a second superconducting transmission line (62) having at least one inductor (64) for transmitting second input pulses that are correlated to the first input pulses. The first and second superconducting transmission lines (52, 62) are coupled together in order to generate a flux attraction between the first and second input pulses for reducing relative timing uncertainty.

Abstract: A superconducting power circuit comprises a bridge circuit, comprising superconducting switch elements having two or more Josephson junctions incorporated at each side of a rhombus-shaped bridge line, the superconducting switch elements being freely switchable by an outside magnetic field; and a control section which uses the outside magnetic field to switch one pair of the superconducting switch elements, arranged on opposite sides of the bridge circuit, to a superconductive state, and switch another pair of the superconducting switch elements to a normal-conductive state; the superconducting power circuit enables a large low-voltage dc current to be converted with high efficiency.

Abstract: In a superconductive single flux quantum logic circuit having two superconductive closed loops each comprising a Josephson junction and one or more inductors, a load inductance part is comprised of an inductor and a Josephson junction and two or more means for supplying a signal current are included. The load inductance part is made by one or more inductors and means for applying flux via the inductors is included.

Abstract: A switching circuit, comprising: a first node for receiving a first voltage; a second node 502 for providing an output; a third node for receiving a second voltage; a capacitance 506 coupled between the second node 502 and the third node; means for intermittently charging the capacitance 506 to provide a first output voltage from the second node 502; and a switch 501 connected between the first node and the second node 502 for isolating the second node 502 from the first node when open and for discharging the capacitance 506 to provide a second output voltage when closed.

Abstract: The present invention is a superconductive logic gate assembly (50, 100), a superconductive NOR gate assembly (10), and a superconductive random access memory (150). A superconductive logic gate assembly in accordance with the invention includes a plurality of logic inputs (INPUTS 1-N), each logic input being coupled to a SQUID (16) and each SQUID including at least one resistance (22) which eliminates hysteresis in an output of the SQUID produced in responding to a change in signal level at the logic inputs to the SQUID, a DC bias (20) coupled to each SQUID, and an output circuit (14) coupled to each SQUID for providing a logic output (OUTPUT) in response to the logic inputs.

Abstract: The present invention is a superconductive logic gate assembly (50, 100), a superconductive NOR gate assembly (10), and a superconductive random access memory (150). A superconductive logic gate assembly in accordance with the invention includes a plurality of logic inputs (INPUTS 1-N) each logic input being coupled to a SQUID (16) and each SQUID including at least one resistance (22) which eliminates hysteresis in an output of the SQUID produced in responding to a change in signal level at the logic inputs to the SQUID, a DC bias (20) coupled to each SQUID, and an output circuit (14) coupled to each SQUID for providing a logic output (OUTPUT) in response to the logic inputs.

Abstract: There is disclosed a bifrequency output device. The bifrequency output device comprises Josephson junctions, a resistor for generating a given voltage in response to a pulse current which is supplied from the outside, and a time delay element for delaying the voltage generated by the resistor during a given time period and then providing it to the superconducting elements, so that the bifrequency output device outputs different low frequency and low voltage and high frequency and high voltage depending on the initial condition of the superconducting elements constituting the Josephson junctions and the voltage with a given delay time which is induced to the superconducting elements.

Abstract: A circuit embodying the invention includes two toggle flip-flops formed using Josephson junctions sharing a common inductive element. One flip-flop is responsive to "zero" input signals (IN.phi.) and the other flip-flop is responsive to "one" input signals (IN1). Each flip-flop has two outputs. The two outputs of the flip-flop responsive to IN.phi. may be identified as A.phi. and B.phi. and the two outputs of the flip-flop responsive to IN1 may be identified as A1 and B1. The inductive element is settable to either one of two states by controlling the flow of a bias current therethrough. Depending on the state of current conduction through the inductive element, an IN.phi. input signal will produce an output at either A.phi. or B.phi. and an IN1 input signal will produce an output at either A1 or B1. If, and when, the inductive element is in a first state, an IN.phi. or IN1 input will cause a corresponding output at A.phi.

Abstract: The present invention discloses a method for amplifying voltage to which a test will be given in Josephon junction having external current, and more particularly, to a method for amplifying voltage in Josephon junction in which the voltage in a simple Josephon junction having an external current can be amplified by inserting an external colored noise into the external current.

Abstract: A three-terminal device constructed from a Josephson junction with one or more asymmetric control lines is disclosed. The device is constructed with high temperature superconducting materials. The junction can be a bicrystal, SNS (Superconducting-Normal-Superconducting) or any other type of high temperature superconductor junction. The control line is either a conducting or superconducting material which is electrically isolated from the junction but inductively coupled into the junction. A portion of the control line is approximately directly above the junction and has current which at least partially flows parallel or nonparallel to current flowing across the junction. The control line current alters the magnetic field within the junction which changes the critical current of the junction. The junction is in a superconducting or resistive state depending on whether the bias current of the junction is greater than or less than the control current.

Abstract: A sensitive detector and detector system with multi-state element or elements employing the phenomenon of stochastic resonance to enhance signal-to-noise ratio (SNR) and detector sensitivity. Signal output is enhanced by the addition of external noise at the input. A single detector element has these improved outputs. Several stochastic resonance elements may be connected in arrays to further increase SNR of the output, increase detector sensitivity, and linearize the relation between input and output.

Abstract: A switch for controlling the throughput of a signal between a pair of input channels and a pair of output channels is provided which receives an input signal from each of the pair of input channels. The switch transmits an output signal to each of the pair of output channels. Four line channels are provided within the switch. Each of the four line channels connects one of the pair of input channels and one of the pair of output channels. Four line channel switches are also provided, one line channel switch provided on each of the line channels. Each of the four line channel switches is controlled by a signal to open or close the four line channels.

Abstract: A Josephson junction voltage standard based on rf controlled dc SQUID's is proposed. A microwave signal is injected using rf control lines. A D/A converter based on series-connected rf controlled SQUID's is described.

Abstract: A Josephson logic circuit includes a Josephson element inserted between an input terminal and a reference electric potential such as ground, a resistor inserted between the input terminal and an input of the next stage of the Josephson circuit, and a current source which supplies an offset current to the Josephson element. By adjusting the offset current, the Josephson logic circuit can be operated as an AND circuit, an OR circuit, or a majority logic circuit having a high input sensitivity.