Abstract: In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.

Abstract: The present invention relates to the field of communications on rail trains. A PicoBlaze-based MVB controller includes a pMVB controller, a traffic memory, an ARM adapter, and a bus arbiter. The pMVB controller, the traffic memory, ARM adapter, and the bus arbiter are connected to an external bus BUS1. The pMVB controller is connected to the traffic memory. The ARM adapter is connected to an external ARM processor and the bus arbiter. The traffic memory can store network communication data and input control information, and send them to the pMVB controller. The pMVB controller responds to the control information, and sends the communication data, and after it is encoded, to the MVB bus via the external bus BUS1. The pMVB controller also decodes data received from the pMVB bus and triggers an interrupt. The bus arbiter is responsible for bus arbitration in accordance with the instructions from the pMVB controller.

Abstract: In one embodiment, a circuit includes at least one transistor with a base and collector being electrically connected to a ground, and at least one current source being configured to apply four different currents (A, B, C, and D) to the emitter. A sum of the currents A and C are substantially equivalent to a sum of the currents B and D, or a sum of the currents A and D are substantially equivalent to a sum of the currents B and C. The circuit outputs first, second, third, and fourth voltage potentials between the emitter and the base during application of the currents A, B, C, and D, respectively.

Abstract: A buffer circuit including an input terminal capable of receiving an input signal and an output terminal capable of being connected to a capacitive load, including an output circuit a series connection, between two terminals of application of a power supply voltage, of a first MOS transistor, a first and a second resistor of adjustable values, and a second MOS transistor, and means for controlling said first and second transistors receiving the input signal The buffer circuit further includes means for comparing the voltage on the output terminal of the circuit with at least one threshold voltage, the comparison means being connected to said control means.

Abstract: To provide, with a simple structure, a voltage controlled oscillator, etc., whose center oscillation frequency is stable even if there is a change in the temperature. A delay element includes: a delay generating part which adds a delay amount to an input signal to generate an output signal; and a delay control part which controls the delay. The delay control part has a delay adjusting circuit which outputs a first control signal for adjusting the delay amount, and a temperature compensating circuit which outputs a second control signal for compensating property changes caused by the temperature. The delay control part outputs a third control signal obtained by synthesizing the first control signal and the second control signal to the delay generating part to control the delay amount. The delay control part obtains the third control signal by having the delay adjusting circuit and the temperature compensating circuit connected in series.

Abstract: Method and apparatus for a dynamically reconfigurable system monitor (20) are described. A system monitor (20) has registers (206) accessible via a reconfiguration port (201). At least one of the registers may be dynamically reconfigured via the reconfiguration port (201) to select a channel to be monitored or to store an alarm value to be used in monitoring by the system monitor (20). Additionally, the system monitor (20) may be embedded in a columnar block architecture.

Abstract: Method and system for periodically measuring the junction temperature of a semiconductor device. The junction exited by at least two sequential predetermined currents of different magnitudes. The voltage response of the junction to the at least two currents is measured and the temperature of the junction is calculated, while substantially canceling ohmic effects, by using the voltage response and a correction factor obtained by periodically. Whenever desired, the junction is exited by a set of at least four sequential different currents having known ratios. The voltage response to the set is measured and the correction factor is calculated by using each voltage response to the set.

Abstract: An on-chip temperature detection device includes: a bipolar type power transistor; a mirror transistor in which a collector current, which is proportional to a collector current of the power transistor, flows; a current detection section that detects the collector current of the mirror transistor; a voltage detection section that detects a voltage between a base and an emitter of the power transistor; and a calculation section that calculates a chip temperature of the power transistor, based upon the collector current of the mirror transistor detected by the current detection section, and upon the voltage between the base and the emitter of the power transistor detected by the voltage detection section.

Abstract: Method and system for periodically measuring the junction temperature of a semiconductor device. The junction is excited by at least two sequential predetermined currents of different magnitudes. The voltage response of the junction to the at least two currents is measured and the temperature of the junction is calculated, while substantially canceling ohmic effects, by using the voltage response and a correction factor. Whenever desired, the junction is excited by a set of at least four sequential different currents having known ratios. The voltage response to the set is measured and the correction factor is calculated by using each voltage response to the set.

Abstract: A system (300, 500) for scrambling digital samples (115, 200, 250, 260, 270) of multimedia data, including audio and video data samples, such that the content of the samples is degraded but still recognizable, or otherwise provided at a desired quality level. The samples may be in any conceivable compressed or uncompressed digital format, including Pulse Code Modulation (PCM) samples, samples in floating point representation, samples in companding schemes (e.g., ?-law and A-law), and other compressed bit streams. The quality level may be associated with a particular signal to noise ratio, or quality level that is determined by objective and/or subjective tests, for example. A number of LSBs can be scrambled in successive samples in successive frames (FRAME A, FRAME B, FRAME C). Moreover, the parameters for scrambling may change from frame to frame. Furthermore, all or part of the scrambling key (310) can be embedded (340) in the scrambled data and recovered at a decoder (400, 600) to be used in descrambling.

Abstract: The low voltage to high voltage level shifter has falling-edge 1-shot circuits 34 and 36 coupled to the outputs OUT and OUT_B of cross gate-connected transistors 24 and 26 and pull-down transistors 20 and 22. The falling-edge 1-shot circuits 34 and 36 output a narrow pulse when the outputs OUT and OUT_B transition from a high state to a low state. These pulses are used to set and reset a flip-flop 38. The flip flop 38 provides an output that is only dependent on the very fast fall times of the outputs OUT and OUT_B. This allows the level shifter to be designed for optimal transitional performance without the sacrifice of a potentially long propagation delay on the output nodes.

Abstract: A D flip-flop latches a reference clock signal in response to an output signal fed back from an output circuit. A pulse generating circuit generates a pulse in response to the output signal fedback from the output circuit. From the latched signal and the pulse generated by the pulse generating circuit, a count pulse is generated. The count pulse is output to an up/down counter. Based on the counting result of the up/down counter, a digital-to-analog conversion circuit generates a delay control signal. Using this delay control signal, the delay circuit synchronizes its output signal with the reference clock signal. It is possible to synchronize the output data signal with the reference clock signal regardless of variations in the reference clock signal, source voltage, and ambient temperature.

Abstract: A piezoelectrically controlled superconducting switch is provided for use in superconducting devices and piezoelectric devices. This switch includes a substrate, a superconductor which is bonded to the substrate, and a piezoelectric subassembly which has a load applicator and voltage source for straining the superconductor and for changing its superconductor curve of resistivity versus temperature.