Abstract: Integrated circuit (IC) packages with multiple clock sources are disclosed. A disclosed IC package includes a first die having a first clock source and a first clock tree and a second die having a second clock source and a second clock tree. The first clock source and the second clock source may be coupled to the second clock tree and the first clock tree, respectively, through a plurality of interconnects to form a clock tree network on the IC package. The clock tree network may be operable to be driven by either the first clock source or the second clock source.

Abstract: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.