Specific Identifiable Device, Circuit, Or System Patents (Class 327/524)
  • Patent number: 10382011
    Abstract: The present invention relates to a capacitance multiplier topology suitable for both positive and negative capacitance multiplication having a minimum configuration consisting of a current feedback amplifier (CFOA), two resistors and a reference capacitor, with each C-multiplier having a respective capacitance amplification constant k which is externally adjustable. Such a capacitance multiplier has less parasitic components, occupies a smaller chip area with higher simulated capacitance value.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 13, 2019
    Assignee: YEDITEPE UNIVERSITESI
    Inventor: Ali Umit Keskin
  • Patent number: 10210803
    Abstract: A pixel circuit and driving method thereof, and a display device are provided. The pixel circuit comprises a light-emitting element, a first, second, third, and fourth transistors, and a capacitor element. The first transistor is configured to time-sharingly receive a data voltage and a power supply voltage under control of a first voltage signal. The second transistor is configured to detect and compensate a threshold voltage deviation of the first transistor under control of a first scanning signal. The third transistor is configured to provide a driving current generated by the first transistor to the light-emitting element under control of a light-emitting signal. The fourth transistor is configured to transmit a reset signal to an anode of the light-emitting element under control of a second scanning signal. The capacitor element is configured to store the data voltage transmitted to the first transistor. The light-emitting element is configured to emit light.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: February 19, 2019
    Assignees: SHANGHAI TIANMA AM-OLED CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Tong Wu, Zeyuan Chen, Yue Li, Dongxu Xiang, Renyuan Zhu, Gang Liu
  • Patent number: 10068694
    Abstract: Integrated circuits and coupled inductors with isotropic magnetic cores, and methods for fabricating integrated circuits and coupled inductors with isotropic magnetic cores are provided. In an embodiment, a method for fabricating an integrated circuit is provided. The method includes providing a semiconductor substrate and forming an isotropic magnetic core bottom yoke over the semiconductor substrate. Further, the method includes forming an inductor coil over the isotropic magnetic core bottom yoke. Also, the method includes forming isotropic magnetic core sidewalls over the isotropic magnetic core bottom yoke and around the inductor coil. The method includes forming an isotropic magnetic core top yoke over the isotropic magnetic core sidewalls and over the inductor coil.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 4, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lulu Peng, Donald Ray Disney
  • Patent number: 9906383
    Abstract: The semiconductor device according to an exemplary embodiment includes: a driver configured to output first and second signals complementary to each other through first and second nodes, respectively; and a receiver detector configured to detect whether a reception circuit of an active state is connected to the first node and the second node according to a voltage of the first node and a voltage of the second node. The receiver detector is configured to compare the voltage of the first node with a first reference voltage, compare the voltage of the second node with a second reference voltage, and detect whether the reception circuit of the active state is connected according to a comparison result of the voltage of the first node and a comparison result of the voltage of the second node.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Chiwon Kim
  • Patent number: 9842526
    Abstract: A flat panel display includes a signal generator to generate data signals to respective data lines via an output terminal or to generate a control signal for controlling switches. The signal generator includes a first voltage supply unit to supply, to the output terminal, a voltage of a first voltage sources, a voltage stabilizing unit to raise or drop the voltage supplied to the output terminal, and a second voltage supply unit to supply, to the output terminal, a voltage from a second voltage source, after the voltage of the output terminal is raised or dropped.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: December 12, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Byeong-Doo Kang
  • Patent number: 9817456
    Abstract: A first aspect provides in a supply voltage control module, a method of providing instructions for setting a supply voltage comprising obtaining information on a supply voltage need of a load and based on that information, determining a supply voltage that is to be provided to the load. Subsequently, an instruction is sent to a power supply module to supply the determined supply voltage to the load. A need for a supply voltage of a load, like an integrated circuit, may not only depend on design of the load, but also on parameters of the manufacturing process and the level of activity of the load. By obtaining information on a supply voltage need of the load and using that information to determine a supply voltage to be provided to the load, a feedback loop is created by instructing a point of load power supply to provide the supply voltage determined.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: November 14, 2017
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Björn Olsson, Anders Aronsson, Per Ingelhag, Fredrik Larsson
  • Patent number: 9813816
    Abstract: An audio plug detection structure is disclosed, which is adapted for an audio jack corresponding to an audio plug and includes a first and second connection points, a time-varying signal generation circuit, and a comparison circuit. The time-varying signal generation and comparison circuits are connected to the first connection point. When the audio plug is inserted into the audio jack, the first connection point is connected to a first pole of the audio plug and the second connection point is connected to a second pole different from the first pole of the audio plug. Therefore, the time-varying signal generation circuit, the first connection point, an inner impedance circuit of the audio plug and the second connection plug form a loop. The comparison circuit outputs a determination signal indicating the audio plug is inserted by detecting a change of a time-varying signal generated by the time-varying signal generation circuit.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: November 7, 2017
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Tsung-Peng Chuang
  • Patent number: 9165882
    Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Shen Lin, Jerry Chang-Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai, Chi-Yeh Yu, Kuo-Nan Yang
  • Patent number: 9118335
    Abstract: A novel and useful millimeter-wave digitally controlled oscillator (DCO) that achieve a tuning range greater than 10% and fine frequency resolution less than 1 MHz. Switched metal capacitors are distributed across a passive resonator for tuning the oscillation frequency. To obtain sub-MHz frequency resolution, tuning step attenuation techniques are used that exploit an inductor and a transformer. A 60-GHz fine-resolution inductor-based DCO (L-DCO) and a 60 GHz transformer-coupled DCO (T-DCO), both fabricated in 90 nm CMOS, are disclosed. The phase noise of both DCOs is lower than ?90.5 dBc/Hz at 1 MHz offset across 56 to 62 GHz frequency range. The T-DCO achieves a fine frequency tuning step of 2.5 MHz, whereas the L-DCO tuning step is over one order of magnitude finer at 160 kHz.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: August 25, 2015
    Assignee: Technische Universiteit Delft
    Inventors: Wanghua Wu, John Robert Long, Robert Bogdan Staszewski
  • Publication number: 20150081094
    Abstract: A general-purpose peripheral interface according to an exemplary embodiment of the present invention includes a pair of complementary connectors including at least one input terminal, at least one output terminal, and at least one power supply terminal and ground terminal, wherein when a connector of a peripheral device is combined to a connector of a control device, an identification voltage in a voltage range varying according to a type of the peripheral device is shown in the input terminal. Here, the voltage ranges may be set not to overlap each other when the types of the peripheral devices are different. The type of the peripheral device may be one of an input type, an input-output mixed type, and an output type.
    Type: Application
    Filed: May 21, 2012
    Publication date: March 19, 2015
    Applicant: ROBOTIS CO., LTD.
    Inventors: Byoung-Soo Kim, In Yong Ha
  • Patent number: 8954764
    Abstract: An integrated circuit (IC) includes a first power supply node that is arranged to receive a first power supply signal. The IC also includes process detection circuits. Each process detection circuit provides a process detection output signal such that a value associated with the process detection output signal is a function of process variation at a location of the process detection circuit outputting the process detection signal. The IC also includes a processing unit that executes processor-executable instructions to provide at least one voltage control signal, based, at least in part, on the process detection signals. The voltage control signal(s) include a first voltage control signal is associated with a target voltage for the first power supply signal.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: February 10, 2015
    Assignee: CSR Technology Inc.
    Inventors: Victor Pinto, Eyal Raz
  • Publication number: 20140191796
    Abstract: According to an aspect of the present invention, in a semiconductor device, a plurality of commands for specifying a circuit configuration of an analog front-end unit are transmitted from a processing unit to the analog front-end unit, an analysis is performed on the plurality of commands received by the analog front-end unit, and when a circuit configuration of the analog front-end unit which is to be updated and is determined according to the plurality of commands includes a forbidden condition that has been previously set, updating processing of the circuit configuration according to the plurality of commands is stopped.
    Type: Application
    Filed: January 3, 2014
    Publication date: July 10, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Yutaka YOSHIZAWA
  • Publication number: 20140184314
    Abstract: A coulomb counter is provided. In the coulomb counter, a current generated on charge or discharge of a secondary battery is converted into a voltage by a resistor, and the voltage is amplified by an amplifier circuit. The voltage amplified by the amplifier circuit is converted into a current by a voltage-current converter circuit, and the current is input to a cumulative addition circuit. The cumulative addition circuit charges a capacitor with the current input from the voltage-current converter circuit and generates a signal corresponding to a voltage generated across the capacitor. One terminal of the capacitor is connected to an output of the voltage-current converter circuit through a switch, and the other terminal of the capacitor is supplied with a constant potential. By on/off of the switch, supply of electric charge to the capacitor and storage of the electric charge can be controlled.
    Type: Application
    Filed: December 20, 2013
    Publication date: July 3, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Jun Koyama
  • Patent number: 8710902
    Abstract: Provided are a trimming circuit which does not need a dedicated terminal to which a current for cutting a fuse is input, and also a semiconductor device including the trimming circuit. The trimming circuit includes: an input terminal connected to a pad which is an external terminal of an internal circuit; a fuse provided between a power supply terminal and an output terminal; and a diode provided between the input terminal and the output terminal. The trimming circuit performs trimming by applying, to the pad, such a voltage that the diode is biased in the forward direction.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: April 29, 2014
    Assignee: Seiko Instruments Inc.
    Inventors: Atsushi Sakurai, Kazuaki Sano, Fumihiko Maetani, Satoshi Abe
  • Patent number: 8710916
    Abstract: An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: April 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, David R. Bearden, Andrew C. Russell, Shayan Zhang
  • Publication number: 20140097886
    Abstract: Systems, methods, and apparatus for controlling power semiconductor devices are described. According to one embodiment of the disclosure, there is disclosed a system. The system may include at least one power source for selectively providing power to one or more power semiconductor devices controlled by a gate driver. The gate driver may include at least one controller coupled to at least one power semiconductor device interface via a first channel and a second channel configured to provide galvanic isolation of information communicated between the controller and the at least one power semiconductor device interface.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Mark E. Shepard, Todd David Greenleaf, Alan Carroll Lovell
  • Patent number: 8692561
    Abstract: A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Divya Kumar, Anuwat Saetow, Robert B. Tremaine
  • Patent number: 8689244
    Abstract: A communication system according to one aspect of the present invention, comprises one or more integrated circuits. The one or more integrated circuits comprise at least one of a local integrated circuit and a remote integrated circuit. At least one sending application hardware module located on the local integrated circuit has a sending logic that controls the sending of messages from the sending application hardware module. At least one receiving application hardware module is located on at least one of the local integrated circuit or remote integrated circuit. A sending application hardware module sends messages to a receiving application hardware module without its sending logic having been constructed with a priori knowledge of the address of or the path to said receiving application hardware module. A dispatch logic located on the local integrated circuit that routes at least one or more.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: April 1, 2014
    Assignee: Objective Interface Systems, Inc.
    Inventors: William Beckwith, Steven Deller, Joe G. Thompson
  • Publication number: 20140028380
    Abstract: A microcontroller includes first and second modules. The first module can operate in a mode that causes interference with operation of the second module. A control circuit on the first module and a control circuit on the second module coordinate operation of the first and second modules to prevent the interference from causing the second module to function incorrectly.
    Type: Application
    Filed: August 29, 2012
    Publication date: January 30, 2014
    Applicant: ATMEL NANTES S.A.S.
    Inventors: Sebastien Jouin, Romain Oddoart, Mickael Le Dily, Jerome Poidevin
  • Publication number: 20140025858
    Abstract: A hardware trie structure includes a tree of internal node circuits and leaf node circuits. Each internal node is configured by a corresponding multi-bit node control value (NCV). Each leaf node can output a corresponding result value (RV). An input value (IV) supplied onto input leads of the trie causes signals to propagate through the trie such that one of the leaf nodes outputs one of the RVs onto output leads of the trie. In a transactional memory, a memory stores a set of NCVs and RVs. In response to a lookup command, the NCVs and RVs are read out of memory and are used to configure the trie. The IV of the lookup is supplied to the input leads, and the trie looks up an RV. A non-final RV initiates another lookup in a recursive fashion, whereas a final RV is returned as the result of the lookup command.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: Netronome Systems, Inc.
    Inventors: Gavin J. Stark, Bruce Alexander Wilford
  • Publication number: 20140015598
    Abstract: Semiconductor device packages comprise a first semiconductor device comprising a heat-generating region located on at least one end thereof. A second semiconductor device is attached to the first semiconductor device. At least a portion of the heat-generating region extends laterally beyond at least one corresponding end of the second semiconductor device. A thermally insulating material at least partially covers the end of the second semiconductor device. Methods of forming a semiconductor device packages comprise attaching a second semiconductor device to a first semiconductor device. The first semiconductor device comprises a heat-generating region at an end thereof. At least a portion of the heat-generating region extends laterally beyond an end of the second semiconductor device. The end of the second semiconductor device is at least partially covered with a thermally insulating material.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Steven Groothuis, Jian Li, Shijian Luo
  • Publication number: 20130342264
    Abstract: An integrated circuit has a circuit part and a trimmable resistor, the resistance whereof may be modified by Joule effect. The trimmable resistor has first and second connection terminals coupled to the circuit part, and an intermediate terminal that divides the trimmable resistor into two portions. The first and the second connection terminals and the intermediate terminal are coupled to respective pads configured to receive electrical quantities designed to cause, in use, a respective trimming current flow in each portion. In this way, a substantially zero voltage drop is maintained between the first and second connection terminals while current is flowing in the resistor to change an electrical characteristic of the resistor, such as resistance or thermal coefficient.
    Type: Application
    Filed: June 21, 2013
    Publication date: December 26, 2013
    Inventors: Antonello Santangelo, Stefania Maria Serena Privitera
  • Patent number: 8593327
    Abstract: In an A/D conversion circuit and an imaging device, an upper counter acquires a first upper count value by performing counting using one output signal, which constitutes a first lower phase signal output from a delay circuit, as a count clock. After values of bits constituting the first upper count value are inverted, the upper counter acquires a second upper count value by performing counting using one output signal, which constitutes a second lower phase signal output from the delay circuit, as a count clock, and further performing counting based on an upper count clock output from a lower counter. A modification unit modifies a logic state of a count clock to a predetermined state when the count clock of the upper counter is switched.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 26, 2013
    Assignee: Olympus Corporation
    Inventor: Yoshio Hagihara
  • Publication number: 20130307611
    Abstract: A multi-chip package includes first and second semiconductor chips each configured to perform first and second operations having different current consumptions. The first and second semiconductor chips perform the first operation in response to an enable control signal transmitted from one of the first and second semiconductor chips to the other and transmitted from the other back to the one.
    Type: Application
    Filed: August 10, 2012
    Publication date: November 21, 2013
    Inventors: Won-Kyung KANG, Sam-Kyu WON
  • Publication number: 20130285736
    Abstract: An integrated circuit comprises a circuit module, a first function circuit, and a second function circuit. The first function circuit is configured to he operational in response to a first type logic signal at a first pin and the second function circuit is configured to be operational in response to a second type logic signal at the first pin. The type of logic signal at the first pin is determined by the circuit module. Based on the determined type of logic signal, the circuit module is configured to activate the appropriate function circuit and provide function related signaling for operation at a second pin. The circuit module allows the pins of the integrated circuit to be shared between the first and second function circuits, thus minimizing the number of pins required for multi-functional circuits on the integrated circuit.
    Type: Application
    Filed: June 27, 2013
    Publication date: October 31, 2013
    Inventors: Marc LOINAZ, Stefanos Sidiropoulos, Whay Sing Lee
  • Publication number: 20130214849
    Abstract: Disclosed are a terminal device and a method for realizing an analogue circuit in the terminal device. The terminal device includes control device and programmable analogue circuit device. The control device includes: acquisition module, configured to acquire the configuration data information corresponding to the function index and the parameter index of a target analogue circuit, wherein the configuration data information is configured to indicate the on/off state of an interconnection switch between CABs; downloading module, configured to download the configuration data information to the programmable analogue circuit device; and restart module, configured to restart the programmable analogue circuit device. The programmable analogue circuit device includes: a configurable analogue array module, configured to configure the parameters and/or the connection relationship of the CABs by using the configuration data information.
    Type: Application
    Filed: August 22, 2011
    Publication date: August 22, 2013
    Applicant: ZTE Corporation
    Inventor: Weiwei Ma
  • Patent number: 8493376
    Abstract: Disclosed is a driver circuit structure integrated in a display panel. The driver circuit structure includes a plurality of transistors and a backup transistor. After completing the driver circuit structure, the disclosure inspects it to find an inactive transistor. The inspection process first, isolates the electrical connection between the inactive transistor and the first electrode line and/or the electrical connection between the inactive transistor and the second electrode line. Next, the source electrode of the backup transistor and the first electrode line and/or electrically connecting the drain electrode of the backup transistor and the second electrode line are electrical connected.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: July 23, 2013
    Assignee: AU Optronics Corp.
    Inventors: Kuo-Chang Su, Chun-Hsin Liu, Min-Feng Chiang
  • Publication number: 20130147552
    Abstract: A class-D amplifier includes a quantized amplifier, having no quantization error feedback circuit, coupled to receive a digital input signal, according to which an output signal is generated to be switched between power rails. The digital input signal is pre-compensated to correct an error. A low-pass filter is configured to operate on the output signal to generate a filtered output signal.
    Type: Application
    Filed: November 12, 2012
    Publication date: June 13, 2013
    Applicant: OP Global Holdings Limited
    Inventor: OP Global Holdings Limited
  • Publication number: 20130123111
    Abstract: A device and a method of thermal management. In one embodiment, the device includes an integrated circuit, including: (1) a conductive region configured to be connected to a voltage source, (2) a transistor having a semiconductor channel with a controllable conductivity and (3) first and second conducting leads connecting to respective first and second ends of said channel, wherein a charge in the conductive region is configured to substantially raise an electrical potential energy of conduction charge carriers in the semiconductor channel and portions of said leads are located where an electric field produced by said charge is substantially weaker than near the semiconductor channel.
    Type: Application
    Filed: January 10, 2013
    Publication date: May 16, 2013
    Applicant: ALCATEL-LUCENT USA INC.
    Inventor: ALCATEL-LUCENT USA INC.
  • Patent number: 8421520
    Abstract: A fuse circuit includes an electric fuse coupled to a first voltage source; a low resistance unit coupled to the electric fuse and having a junction which is capable of breaking down; and a switching unit coupled between the low resistance unit and a second voltage source.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: April 16, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jun Gi Choi
  • Patent number: 8402175
    Abstract: The present invention relates to a method and an apparatus for determining an external connection device connected to a portable terminal. A multi-connector, and a charging cable and a data cable having the same are disclosed. According to the method, a logic level of the external connection device is determined when the external connection device is connected to the portable terminal. The external connection device is distinguished according to the logic level and performing control corresponding to the external connection device.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: March 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jeong Ho Hwang
  • Publication number: 20130038380
    Abstract: A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
    Type: Application
    Filed: August 11, 2011
    Publication date: February 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edgar R. Cordero, Divya Kumar, Anuwat Saetow, Robert B. Tremaine
  • Publication number: 20130002342
    Abstract: A semiconductor apparatus includes first and second chips sharing first and second data channels. The first and second chips output normal data of the respective chips through the first and second data channels in a normal operation, and the first chip outputs test data of the first chip through the first data channel, and the second chip outputs test data of the second chip through the second data channel in a test operation.
    Type: Application
    Filed: August 27, 2011
    Publication date: January 3, 2013
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Byung Deuk JEON
  • Publication number: 20120326769
    Abstract: Architecture for supporting ZIF or LIF/IF systems includes 4N pins, 2N ADCs, a determination unit and a processing unit, N being a positive integer. The 2N ADCs include a y-th ADC for converting a differential analog signal received by a (2y?1)-th pin and a 2y-th pin into a y-th digital signal, y being positive integers ranging from 1 to 2N. The determination unit determines whether the digital signals are ZIF signals, LIF signals or IF signals. The processing unit performs an ZIF system processing on the ZIF signals, performs a LIF system processing on the LIF signals, and performs an IF system processing on the IF signals.
    Type: Application
    Filed: November 18, 2011
    Publication date: December 27, 2012
    Applicant: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chin-Tai Yang, Chun-An Tsai
  • Publication number: 20120326768
    Abstract: A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.
    Type: Application
    Filed: June 21, 2011
    Publication date: December 27, 2012
    Applicant: LSI CORPORATION
    Inventors: Dipankar Bhattacharya, Ashish V. Shukla, John Christopher Kriz, Makeshwar Kothandaraman, Pankaj Kumar, Pramod Parameswaran
  • Patent number: 8310252
    Abstract: A test circuit tests a nonvolatile circuit element having multiple intermediate states. The test circuit includes a waveform generator configured to apply a waveform to the circuit element connected to the test circuit. The waveform includes stress pulses applied to the circuit element over time. A detector detects a parameter of the circuit element as the waveform is applied to the circuit element.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: November 13, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Matthew D Pickett, Dmitri Borisovich Strukov
  • Patent number: 8311785
    Abstract: Methods and apparatus to minimize saturation in a ground fault detection device are disclosed. An example method includes connecting a capacitor simulator to a node of the ground fault detector device to prevent saturation, and monitoring power-line conductors for ground fault conditions with the ground fault detector device. An example apparatus to simulate a saturation capacitance in a ground fault device includes a sense coil induced by power-line conductors, and at least one of an amplifier or a current detector including an input connected to the sense coil and an output connected to a ground fault detector. The example apparatus also includes a saturation capacitor simulator connected to a node of at least one of the amplifier or the current detector to prevent saturation.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: November 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Artur J. Lewinski, Ross Teggatz, Thomas Edward Cosby
  • Publication number: 20120206175
    Abstract: There are numerous types of dividers that have been employed at various frequency ranges. For many very high frequency ranges (i.e., above 30 GHz), dividers in CMOS have been developed. However, many of these designs use multiple stages. Here, however, a single stage divider has been provided that is adapted to operate at very high frequencies (i.e., 120 GHz). To accomplish this, it uses parasitic capacitances in conjunction with inductor(s) to form an LC tanks so as to take advantages of parasitics that normal degrade performance.
    Type: Application
    Filed: February 15, 2011
    Publication date: August 16, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Richard Gu, Daquan Huang
  • Publication number: 20120161854
    Abstract: A data input/output device includes a buffer that accumulates data, and a data receiver that receives data input in synchronization with a first clock in accordance with a second clock whose generation source is different from a generation source of the first clock. The data input/output device further includes a data input part that accumulates data received by the data receiver in the buffer, and a data output part that sequentially outputs data accumulated in the buffer at an output interval depending on the amount of data accumulated in the buffer in such a manner that a predetermined data amount is the unit of the output.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 28, 2012
    Applicant: Sony Corporation
    Inventor: Isao Hidaka
  • Patent number: 8193834
    Abstract: This document discusses, among other things, a multiple accessory detection apparatus and methods for identifying accessories coupled to a multi-pin connector of an electronic device. The apparatus can include a first reference generator, a second reference generator, a plurality of switches to couple an output of the second generator to an accessory device and a comparator. The comparator can generate identifying information about the accessory device using the reference information received from the first reference generator and test information received using the second reference generator.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: June 5, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Gregory Maher, Brewster Porcella, Hrvoje Jasa
  • Publication number: 20120133423
    Abstract: A semiconductor apparatus may include a plurality of through-semiconductor chip lines which pass through a plurality of stacked semiconductor chips. An uppermost semiconductor chip among the plurality of stacked semiconductor chips is configured to transfer its internal information signal to an assigned corresponding through-semiconductor chip line, and at least one semiconductor chip other than the uppermost semiconductor chip is configured to logically combine respective internal information signals transferred through through-semiconductor chip lines and their internal information signals and sequentially transfer resultant signals to assigned corresponding through-semiconductor chip lines. The at least one semiconductor chip other than the uppermost semiconductor chip logically combines the internal information signals transferred through the through-semiconductor chip lines from adjoining semiconductor chips and its internal information signals.
    Type: Application
    Filed: June 29, 2011
    Publication date: May 31, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Ju Young KIM
  • Publication number: 20120105134
    Abstract: A pin sharing method for controlling a plurality of functions of a chip via a versatile pin of the chip is disclosed. The pin sharing method includes dividing a voltage range of the versatile pin into a plurality of sections according to the plurality of functions, and assigning the plurality of sections to correspond to a plurality of modes of the plurality of functions.
    Type: Application
    Filed: January 18, 2011
    Publication date: May 3, 2012
    Inventor: Ming-Hung Chang
  • Publication number: 20120105135
    Abstract: An electrical circuit for emulating a capacitance, comprises a physical capacitor which is charged by charge flow from the input of the electrical circuit. An amplifier amplifies the voltage at the input of the electrical circuit such that the physical capacitor is charged with a larger change in voltage than the change in voltage at the input. This implements an effective multiplication of capacitance. A reset system resets the physical capacitor without drawing charge from the input of the electrical circuit. This extends the voltages which can be provided to the input.
    Type: Application
    Filed: November 2, 2011
    Publication date: May 3, 2012
    Applicant: NXP B.V.
    Inventor: Hans Halberstadt
  • Publication number: 20120044015
    Abstract: In a process automation controller, a universal digital input module is provided. The universal digital input module comprises a plurality of digital input channels, each channel to sink a first current at a first voltage level associated with an input having a digital high value and to sink a second current at a second voltage level associated with the input having a digital high value, wherein the first current is greater than the second current and wherein the first voltage is less than the second voltage.
    Type: Application
    Filed: August 17, 2010
    Publication date: February 23, 2012
    Applicant: Invensys Systems Inc.
    Inventor: Ashish Magu
  • Patent number: 8120367
    Abstract: An analog input device including a scanning circuit including a first insulation transformer insulating an analog signal inputted from a thermocouple, a power supply section charging a test voltage used for disconnection detection of the thermocouple, a second insulation transformer in which the scanning circuit and the power supply section are connected in parallel, and a control circuit for outputting a pulse signal to be inputted to the second insulation transformer. The second insulation transformer insulates and transfers a drive pulse for switching the scanning circuit and a power supply pulse for feeding power to the power supply section. The control circuit carries out a timing control so that the drive pulse and the power supply pulse are not outputted at the same time. Accordingly, an insulation transformer for application of a test voltage is not required, and thus the total number of the components is reduced to a great extent and reductions in costs and size thereof are realized.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: February 21, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshihiro Akeboshi, Seiichi Saito, Tetsuya Nagakawa
  • Patent number: 8119958
    Abstract: A matrix of explosive cells can include plural explosive cells formed in an array in a common substrate. Each cell can be formed as a recess filled with explosive material. An ignition device has an addressable ignition source for each cell. This matrix can be used in combination with a projectile guidance system. The projectile guidance system includes an antenna, a transceiver and a control processor. A method of guiding a projectile can include firing a projectile at a target, tracking the projectile and the target, determining a desired change in a flight path of the projectile, transmitting guidance commands to effect the desired change in the projectile's flight path to the projectile, receiving the guidance commands onboard the projectile and selectively igniting an explosive cell in a matrix of addressable explosive cells contained in a common substrate using the guidance commands.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: February 21, 2012
    Assignee: Lockheed Martin Corporation
    Inventors: Christian Adams, Kenneth S. Gurley, Tara Y. Rohter, Patrick A. Nelson
  • Publication number: 20120025898
    Abstract: A circuit device includes an option pad, a first power source pad, and a first ground pad, wherein the option pad, the first power source pad, and the first ground pad are formed over various portions of a top surface of the circuit device, and a function of the circuit device is determined by coupling the option pad with one of the first power source pad and the first ground pad through a wire bond.
    Type: Application
    Filed: October 7, 2010
    Publication date: February 2, 2012
    Applicant: RICHWAVE TECHNOLOGY CORP.
    Inventor: Tse-Peng Chen
  • Publication number: 20120019309
    Abstract: This document discusses, among other things, an audio jack detection circuit configured to be coupled to an audio jack receptacle of an external device. The audio jack detection circuit configured to receive to receive audio jack receptacle information, to disable an oscillator when the audio jack receptacle information indicates that the audio jack receptacle is empty, and to enable the oscillator when the audio jack receptacle information indicates that the audio jack receptacle includes an audio jack.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 26, 2012
    Inventors: John R. Turner, Seth M. Prentice, Oscar Freitas, Wonsoo Moon
  • Publication number: 20120001679
    Abstract: An embodiment of an electrically trimmable electronic device, wherein a resistor of electrically modifiable material is formed by a first generally strip-shaped portion and by a second generally strip-shaped portion, which extend transversely with respect to one another and are in direct electrical contact in a crossing area. The first and second portions have respective ends connected to own contact regions, coupled to a current pulse source and are made of the same material or of the same composition of materials starting from a same resistive layer of the material having electrically modifiable resistivity, for example, a phase-change material, such as a Ge—Sb—Te alloy, or polycrystalline silicon, or a metal material used for thin-film resistors. The trimming is performed by supplying a trimming current to the second portion so as to heat the crossing area and modify the resistivity thereof, without flowing longitudinally in the first portion.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 5, 2012
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Stefania Maria Serena PRIVITERA, Antonello SANTANGELO
  • Publication number: 20110316612
    Abstract: A monolithic power switch provides a semiconductor layer, a three dimensional FET formed in the semiconductor layer to modulate currents through the semiconductor layer, and a toroidal inductor with a ceramic magnetic core formed on the semiconductor layer around the FET and having a first winding connected to the FET.
    Type: Application
    Filed: June 24, 2011
    Publication date: December 29, 2011
    Inventor: L. Pierre de Rochemont