Abstract: The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.

Abstract: A comparator circuit with reduced current consumption, and other circuits utilizing the same, are provided. The comparator circuit may achieve reduced current consumption by preventing current flow via a switching transistors responsive to the voltage level of the input signal.

Abstract: An input power supply voltage level detection circuit and method are presented. The circuit includes a main detector core and a two-inverter buffer block that can include a first inverter and a second inverter. The circuit receives a voltage input signal and outputs a voltage output signal that is substantially equal to either the voltage input signal or ground, depending on whether the voltage input signal has reached a threshold voltage. The threshold voltage is defined by component characteristics of the main detector core and the two-inverter buffer block. The circuit can receive a hysteresis input signal, tied to the voltage input signal or the ground, that allows the threshold voltage to have a first threshold value when the voltage input signal increases and a second threshold value when the voltage input signal decreases. A power down input signal can also be received that allows the circuit to be powered down.

Abstract: A low-voltage detection circuit detects a terminal voltage of a power supply terminal. The low-voltage detection circuit includes a first voltage-dividing circuit, a second voltage-dividing circuit, and a comparator. The second voltage-dividing circuit includes a bias circuit and a metal-oxide-semiconductor (MOS) transistor. The comparator compares and receives a voltage generated by the first voltage-dividing circuit and a voltage generated by the second voltage-dividing circuit to generate a voltage detection signal.

Abstract: A modulated Class E transmitter is disclosed. In one embodiment of the invention, the modulated Class E oscillator achieves high coil currents (˜1A) and voltages (˜500V) with low power components by precisely timed injection of current when the oscillating current in the inductor passes through zero. A detector circuit is used to trigger the current injection at the appropriate instant regardless of changes in the resonant frequency of the system. Its phase can be adjusted to compensate for propagation delays in the drive circuitry, while amplitude modulation is accomplished by switching in additional reactive conductance to increase the current injected into the tank circuit.

Abstract: In general, the embodiments introduce a pre-charge state between an idle state (when no data in being transmitted) and an active state (when data is being transmitted). In the pre-charge state, both differential signals are pre-charged to the common mode voltage, which is also the crossover voltage. Similarly, an additional pre-charge state is inserted between the active state and the idle state when the signals transition from active to idle. Because both signals for each bit, including the first and last bits, are being driven from the same voltage level, the quality of the first and last bits are improved to be similar in quality to the middle bits.

Abstract: In a power supply device including a full-wave rectifying and smoothing circuit powered from a commercial AC power supply via two power supply lines, a switching regulator for separating and stepping down the output from the full-wave rectifying and smoothing circuit to output a desired DC voltage, and two capacitors after the full-wave rectifying and smoothing circuit for the terminal noise suppression purpose, a zero-cross detection circuit includes a transistor of which the emitter is connected to the low-voltage output terminal of the full-wave rectifying and smoothing circuit for outputting a zero-cross detection signal from the collector; a first resistor is connected between the base and emitter of the transistor; a second resistor is connected between one of the power supply lines and the base of the transistor; and a third resistor is connected between the other power supply line and the emitter of the transistor.

Abstract: A window comparator is disclosed having a 1st and a 2nd voltage input wherein the window comparator is fully differential with respect to the 1st and 2nd voltage inputs. Two differential pairs control the state of a zero-crossing comparator in response to the difference between the 1st and 2nd voltage inputs.

Abstract: In a power supply device including a full-wave rectifying and smoothing circuit powered from a commercial AC power supply via two power supply lines, a switching regulator for separating and stepping down the output from the full-wave rectifying and smoothing circuit to output a desired DC voltage, and two capacitors after the full-wave rectifying and smoothing circuit for the terminal noise suppression purpose, a zero-cross detection circuit includes a transistor of which the emitter is connected to the low-voltage output terminal of the full-wave rectifying and smoothing circuit for outputting a zero-cross detection signal from the collector; a first resistor is connected between the base and emitter of the transistor; a second resistor is connected between one of the power supply lines and the base of the transistor; and a third resistor is connected between the other power supply line and the emitter of the transistor.

Abstract: A technique is provided for identifying waveform period or specific events during a waveform period. A periodic waveform is an input signal for a comparator, voltage divider and a balanced load. The circuitry produces a square waveform that has the same period as the input waveform, but is phase shifted based upon time required for the input waveform to cross positive and negative offsets from a zero axis. The resulting timing signals may be used for analysis of the input waveform, such as for RMS calculations based upon sampling of the input waveform.

Abstract: A system and method for accurately measuring a pulse run length in a high frequency (HF) data signal while utilizing a low analog-to-digital conversion (ADC) sampling rate. Four bits are added to the most significant end of an oscillator's accumulator register so that the oscillator generates a sawtooth clock waveform ranging in phase from zero (0) to 32&pgr; radians. An interpolator detects a first zero-crossing transition of the HF data signal at the leading edge of the pulse run length, and a phase detector measures a first phase increment at that time. The MSBs of the accumulator register is then initialized to place the measured first phase increment in a range between zero (0) and 2&pgr; radians. The accumulator register then accumulates phase increments until the interpolator detects a second zero-crossing transition of the HF data signal at the trailing edge of the pulse run length, and the phase detector measures a second phase increment when the second zero-crossing transition is detected.

Abstract: The present invention relates a current zero crossing detecting circuit including a PWM driving half bridge circuit, which generates an output signal (OUT) and a signal synchronous with the high impedance condition of said PWM driving half bridge circuit. Said inventive circuit has the characteristic of comprising detecting means (DFLIP, COMP) synchronous with said signal synchronous with the high impedance condition of said PWM driving half bridge circuit and said output signal (OUT), and said detecting means generating a direction signal (DIR_COR) showing the current direction flowing in said pulse width modulation circuit.

Abstract: An apparatus for minimal phase delay and zero crossing filtering, obtaining a filtered signal without phase delay and glitch by combining a zero crossing filter and a hysteresis zero crossing filter. The zero crossing filter and the hysteresis zero crossing filter both receive an input signal and a reference signal and respectively output a zero-delay signal with glitches and a hysteresis signal with phase delay. A phase-protect filter then receives these two signals and outputs the filtered signal. When the zero-delay signal has a change of state and the hysteresis signal is at the first state, the filtered signal is at the second state. When the zero-delay signal has a change of state and the hysteresis signal is at the second state, the filtered signal is at the first state. When the zero-delay signal has no change of state, the filtered signal remains unchanged.

Abstract: There is provided an input circuit with reduced electrical power consumption, which processes an input signal given thereto for removing the noise components contained therein and regulating the voltage level thereof as well, and then supplies an output signal therefrom to a subsequent semiconductor integrated circuit. The input circuit 101 is made up of the Schmitt buffer 111, a pull-down resistance 113, an N-transistor 115, a P-transistor 121, an N-transistor 122, a P-transistor 131, an N-transistor 132, an exclusive OR gate 141, and a bus driver 151. The Schmitt buffer 111 is a buffer which has two threshold levels i.e. upper and lower thresholds, and changes the level of the output signal OUT depending on whether the voltage of an input signal IN is higher or lower than these two threshold levels.

Abstract: A circuit and method for clocking counters in a polyphase dc motor is provided in which the motor is capable of operating at two or more operating states, spin-up and regulation. The system clock is connected to the clocking circuit through dividers to produce a first clock signal having a low frequency for operating the counter at spin-up, and a second clock signal having a higher frequency for operating the counter at regulation. The clocking circuit includes a switch for connecting the first clock signal to the clock input of the counter when the motor is at spin-up, and for connecting the second clock signal to the clock input when the motor is at regulation. The switch is controlled by a switch control circuit that ensures that switching does not occur when the counter is timing the motor by only allowing the switching to occur when the counter is at an end of a timing cycle and before the counter resets. An at-speed circuit is used to determine whether the motor is at spin-up or at regulation.

Abstract: A low current drain switch interface circuit includes an input terminal (105), coupled to a first terminal (201) of a diode (115). A voltage follower circuit (211) is coupled to a second terminal (203) of the diode (115). A current source (215) is coupled between an output terminal (213) of the voltage follower circuit (211) and a power supply terminal (111). A mechanical switch (101) is coupled to the input terminal (105). The voltage follower circuit (211) outputs a voltage (119) indicative of a physical state of the mechanical switch (101).

Abstract: An integrated circuit comprises at least one differential input stage. The differential input stage includes an input circuit and a shaping circuit. The input circuit comprises a first portion and a second portion for providing two pairs of differential signals. The propagation times of the first and second circuit portions are preferably substantially identical. The shaping circuit differentiates each of the two pairs of differential signals and combines them to obtain a single binary type of signal.

Abstract: An improved output voltage detection circuit for a traffic signal controller which is capable of minimizing an operational characteristic variation with respect to the operational temperature variation and enabling a compact product.

Abstract: A comparator circuit has first and second inputs and an output and includes means for operating the comparator in alternate autozero and comparator phases. During an autozero phase, the inputs of the comparator are clamped to a reference potential and during a compare phase, input signals are applied to the input of the comparator. Control signals are applied to the inputs of the comparator during a portion of the compare phase. The control signals determine the state of the comparator output when the input signals applied to the inputs of the comparator are below a predetermined level.

Abstract: The invention concerns a process for detecting the zero crossings of a data signal by employing of a comparator. To be able to accurately detect zero crossings even when the data signal is distorted due to transmission over a system with filtering characteristics, an auxiliary voltage corresponding to half the value of the difference between the measured maximum value of the data signal and the measured minimum value is generated. An additional voltage is formed by comparing a reference quantity that is proportional to the auxiliary voltage with the respective instantaneous value of the data signal and is added to the auxiliary voltage to form a total voltage. The total voltage is used to form the reference voltage of the comparator.

Abstract: A low pass filter comprises a complementary signal generator circuit for receiving an input pulse signal to output a first and a second signals having phases inverse to each other, a first CR circuit inputted with the first signal, a second CR circuit inputted with the second signal, a flip-flop circuit, a set circuit, and a reset circuit. In the low pass filter, the set circuit detects an output signal of the first CR circuit by the threshold voltage value thereof to set the flip-flop circuit in accordance with a detection result, and the reset circuit detects an output signal of the second CR circuit by the same threshold voltage value to reset the flip-flop circuit in accordance with a detection result.

Abstract: A circuit provides a restart signal to indicate a zero crossing of a continuous varying signal. A zero phase signal is generalized based on a zero crossing of the continuous varying signal. The continuous varying signal is sampled and held in accordance with the zero crossing. The continuous varying signal is converted to complementary signals, and these complementary signals are in turn converted to a signal appropriate for CMOS circuits.

Abstract: A edge detector for the production of output signal in a manner dependent on positive and negative edges of a square wave signal comprises a differential amplifier with two base-coupled transistors (Q1, Q2). Each emitter of such transistors is connected via a constant current source (S1 and, respectively, S2) with a supply voltage line (10) and the emitter currents of the transistors are split up between two collectors, of which the first ones are connected with one another and, via a third constant current source (S3), with ground (12). Two output loops each comprise a series circuit composed of a resistor (R3, R4) and the collector-emitter path of an output transistor (Q3, Q4) between ground (12) and the supply voltage line (10). In the case of each of such output transistors (Q3, Q4) the base is connected in each case with a second collector of the base-coupled transistor (Q1, Q2) so that the switching state of the output transistors (Q1, Q2) is set by the voltage at each second collector.

Abstract: A zero-crossing circuit and method, in which the sign of inputs to a comparator is reversed after each zero crossing of the input signal. This means that delay introduced by the comparator does not affect the duty cycle of the output signal, so precision synchronization remains possible.

Abstract: A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition.

Abstract: An accurate peak-to-peak detector, readily implemented in CMOS and consuming low power. The peak-to-peak detector includes a clamp portion (circuit) followed by a peak-detect portion (circuit), each of which circuits includes at least one active component (e.g., transistor). The clamp circuit receives an input signal having an alternating current (AC) component via an input coupling capacitor which outputs a voltage on a line to the peak-detect circuit. The clamp circuit includes either a passive load element (e.g., a resistor), or an active load element (e.g., a CMOS transistor), so that the clamp circuit bleeds current from the input coupling capacitor, and any slow drift in the DC level of the input voltage will be followed. The peak-detect circuit follows the voltage output by the coupling capacitor, and includes either a passive load element (e.g., a resistor) or an active load element (e.g.

Abstract: A device which reshapes sinusoidal signals with a singularity to generate square-wave signals and detects the singularity in an unambiguous and reliable manner. The sinusoidal pulses are reshaped into square-wave pulses in such a way that the edges of the square-wave pulses always occur at the same location regardless of the height of the sinusoidal signal. This is achieved in that a change in the edges of the square-wave signals is initiated whenever the sinusoidal signal crosses the zero-axis. The required signal processing and logical comparisons, which also enable a definite detection of reference marks, are carried out in a suitable circuit arrangement.

Abstract: In one aspect of the present invention, a zero crossing detecting circuit is disclosed. The circuit includes a first comparator having an inverting and non-inverting input connected to an input signal. The non-inverting input of the first comparator is further connected to the first comparator output to provide a feed forward path. A second comparator is additionally included having an output connected to the first comparator inverting input. This provides the inverting input of the first comparator with a reference voltage that is substantially equal to that of the first comparator non-inverting input; thereby, providing the first comparator with balanced inputs.

Abstract: A circuit to detect the crossing of at least one voltage threshold by an input voltage of an integrated circuit has two arms mounted in negative feedback configuration, each comprising a forward biased diode in series with a current generator. The current generator of an arm is controlled in voltage by the other arm. An inverter calibrated to detect a crossing of a given threshold is connected at input to the connection point between the diode and the generator of one of the arms.

Abstract: An accurate and stable low voltage detect circuit that provides a low voltage detect signal with minimal variation over process and temperature without trimming requirements. The power supply voltage is divided by a resistor voltage divider and compared to the output voltage of a bandgap reference circuit at the inputs of a comparator. The output of the comparator indicates power-on when the voltage divided power supply raises above the bandgap reference voltage. The low voltage detect circuit of the present invention will generate a correct low voltage detect signal even at power supply voltages too low for much of the rest of the circuit to operate properly. At low enough Vcc voltages, a transistor switch disconnects the resistor voltage divider from Vcc, causing all voltages taps off of the resistor voltage divider to drop to ground. Additionally, especially designed bandgap reference and comparator circuits ensure proper operation of the low voltage detect circuit at low power supply voltages.

Abstract: A signal conditioning circuit is described for detecting zero crossings in the output of an inductive or variable reluctance sensor, which comprises a circuit (20, 30) for converting the output signal of the sensor into a signal having substantially frequency independent amplitude and the same frequency as the sensor output signal and a circuit (40) for detecting zero crossings of the converted output signal. The circuit for converting the output signal of the sensor comprises a comparator (30) for comparing the instantaneous value of the output signal of the sensor with a reference signal, a resettable integration circuit (20) having a storage capacitor (26) for integrating the output of the sensor with respect to time, and an electronic switch (26) means responsive to the output signal of the comparator (30) for resetting the integration circuit by discharging the storage capacitor (24).

Abstract: An arrangement for controlling a zero crossing switch in order to connect a source of zero crossing AC voltage to and disconnecting it from an AC load line is disclosed herein along with its method of operation. To this end, means are provided for producing externally controlled command signals intended to control when the switch connects and disconnects the load line to and from the AC voltage. At the same time, a specific window of time is selected, which window begins a particular period of time prior to and includes at least certain zero crossing points of the AC voltage. Internally controlled command signals are produced in response to the AC voltage and externally controlled signals for actually controlling when the switch connects (ON) and disconnects (OFF) the load to and from the AC voltage.

Abstract: A first input signal has successive zero amplitude crossings. A first comparator generates a first bilevel output signal responsive to the first input signal. The first comparator has a hysteresis characteristic which is switched on at each said zero crossing of the first input signal and switched off prior to each occurrence of the next following zero crossing. A second input signal has successive zero amplitude crossings and is displaced in phase relative to the first input signal. A second comparator generates a second bilevel output signal responsive to the second input signal. The hysteresis characteristic is switched on by level transitions of the first bilevel output signal and switched off by level transitions of the second bilevel output signal. The first and second input signals may be sinusoidal. The hysteresis characteristic may controlled by first and second flip/flops, which are set by the first bilevel output signal and reset by the second bilevel output signal.