Abstract: A drive device according to the present invention is located in a liquid crystal panel. The drive device is a source driver IC that drives a pixel region of the liquid crystal panel. The drive device includes a comparison circuit and a determination circuit. The comparison circuit detects a potential difference between a potential of a first analog power supply and a potential of a second analog power supply, an analog power supply input from the outside being divided into the first analog power supply and the second analog power supply. The determination circuit determines that it is an abnormal condition when the potential difference detected by the comparison circuit is greater than or equal to a predetermined threshold value.

Abstract: A method for controlling a temperature of an electronic device which includes a semiconductor chip is provided. The temperature control method includes measuring a temperature of a measurement point using the electronic device, comparing the temperature of the measurement point with a target temperature varying according to a period of time when the semiconductor chip operates using the electronic device, and decreasing a clock frequency of the semiconductor chip using the electronic device when the temperature of the measurement point is higher than the target temperature.

Abstract: A sensor circuit for obtaining physical quantities with a small margin of error even when the temperature varies is provided. The sensor circuit includes a sensor, a sampling circuit for obtaining a voltage value or a current value of a signal output from the sensor during a predetermined period and holding the value, and an analog-to-digital converter circuit for converting the held analog voltage value or current value into a digital value. The sampling circuit includes a switch for obtaining the voltage value or the current value and holding the value. The switch includes a transistor including an oxide semiconductor in a channel formation region.

Abstract: Exemplary embodiments are related to detecting a reverse-boosting operation of a battery charger. A device may include a plurality of switches for receiving an input voltage at an input port and conveying an output voltage. The device may also include a first sensing device coupled to the input port configured to detect if an input current is less than a threshold current. Further, the device may include a second sensing device selectively coupled to the input port to detect if the input voltage is less than a threshold voltage.

Abstract: A differential circuit includes a first input part; a second input part; a reference voltage input part, the reference voltage input part being common to form differential pairs; a current source that drives the differential pairs; a current mirror that generates a first output current and a second output current, according to a current that flows through the reference voltage input part according to at least one voltage difference of first and second voltage differences; a first output part that outputs a signal according to the first voltage difference, according to a current that flows through the first input part according to the first voltage difference and the first output current; and a second output part that outputs a signal according to the second voltage difference, according to a current that flows through the second input part according to the second voltage difference and the second output current.

Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

Abstract: A differential circuit characterized by including a first input part to which a first input voltage is input; a second input part to which a second input voltage is input; a reference voltage input part to which a reference voltage is input, the reference voltage input part being common to form differential pairs by pairing with respective ones of the first input part and the second input part; a current source that drives the differential pairs; a current mirror that generates a first output current and a second output current, according to a current that flows through the reference voltage input part according to at least one voltage difference of a first voltage difference between the first input voltage and the reference voltage and a second voltage difference between the second input voltage and the reference voltage; a first output part that outputs a signal according to the first voltage difference, according to a current that flows through the first input part according to the first voltage difference

Abstract: Apparatus, systems and methods are provided for protecting a processing system from electromagnetic interference. An integrated circuit comprises a sensing arrangement configured to sense an interference signal and an interference detection module coupled to the sensing arrangement. The interference detection module is configured to detect when a power level associated with the interference signal is greater than a threshold value. In one embodiment, the interference detection module generates an interrupt for a processing system when the power level associated with the interference signal is greater than the threshold value.

Abstract: An MIPI interface is connected to two sensor sources that each may be transferring both high and low speed information, typically video information in the high speed state. The clock signals are monitored and when one of the clock signals exceed a threshold, an analog switch between the MIPI interface and the sensors, may connect the other source to the MIPI interface.

Abstract: A method and an arrangement are provided for balancing the switching transient behavior of parallel connected power semiconductor components. The method includes providing a switch signal to the parallel connected power semiconductor components for changing the state of the components, forming control signals for each of the parallel connected components from the switch signal, and determining, during the change of state of the power semiconductor component, the voltage induced to an inductance in the main current path of the component in each of the parallel connected components. The method also includes comparing each of the induced voltages with a predetermined threshold voltage, measuring time differences between the time instants at which the induced voltages crosses the threshold voltage, and modifying one or more of the control signals on the basis of the measured time differences in the respective following state change for balancing the switching transient behavior.

Abstract: A half-power buffer amplifier includes a buffer stage having a first-half buffer stage and a second-half buffer stage. An output of the first-half buffer stage is controllably fed back to a rail-to-rail differential amplifier, and an output of the second-half buffer stage is controllably fed back to the rail-to-rail differential amplifier. A switch network controls the connection between the outputs of the buffer stage and an output node of the half-power buffer amplifier in a manner such that a same pixel, with respect to different frames, of a display panel is driven by the same rail-to-rail differential amplifier.

Abstract: A semiconductor integrated circuit has a sampling circuit which samples a potential of an input terminal, a dynamic comparator having a standby and a comparison mode which compares the potential of the input terminal and a reference potential, a switch for input signals connected between the input terminal and the dynamic comparator, a capacitor for comparator having one end connected between the switch for input signals and the dynamic comparator and another end connected to a fixed potential, and a timing control circuit which controls a timing to sample by sampling circuit, a timing to switch modes of dynamic comparator, and a timing to make switch for input signals conducting or blocking state. The timing control circuit makes the switch for input signals blocking state from conducting state before the dynamic comparator switches from standby mode to comparison mode, and terminates sampling by sampling circuit after switching modes.

Abstract: A chopper type comparator including a first power supply line to which a first power source is supplied, a second power supply line to which a second power source having lower voltage than the first power source is supplied, a reference voltage input part to which a reference voltage is input, a target comparison voltage input part to which a target comparison voltage is input, a comparing part configured to compare the size between the reference voltage input from the reference voltage input part and the target comparison voltage input from the target comparison voltage input part, an output part configured to output a comparison result of the comparing part, and a resistance value setting part configured to set resistance values of the first power supply line and/or the second power supply line.

Abstract: A disclosed timer circuit for clocking a predetermined time includes an oscillator and a frequency dividing unit for dividing a frequency of an oscillating signal output from the oscillator. A comparing unit determines whether a short-time mode instruction is received by comparing a voltage received at an external terminal with a predetermined voltage. A switch causes the oscillating signal to bypass a part of the frequency dividing unit in response receiving the short-time mode instruction.

Abstract: Power savings are achieved for digital data transport over short distances by using the characteristics of resonant LC circuits. Economy of circuit elements is achieved by enabling a single pair of resonant circuits to drive large numbers of digital data lines or nodes in parallel. This maximizes power efficiency and minimizes area and cost. Resistance is minimized by insuring that all switches in the current path are fully “ON” whenever significant current is flowing through them. All other parasitic resistances in the circuits, consisting primarily of parasitic interconnect resistances, are minimized. This enables the data transmission circuits to achieve maximum Q or quality factor, which minimizes power dissipation.

Abstract: The present invention relates to a buffer circuit of a semiconductor memory device, and includes a common bias supply unit and a plurality of interface units having a differential amplifying structure. Each interface unit receives an input signal and differentially amplifies the input signal and a common bias. The common bias supply unit is driven by a reference voltage to provide the common bias signal to each of the interface units. The buffer circuit makes it possible to reduce the area occupied by the buffer circuit in a semiconductor memory device.

Abstract: A high-side driver in a driver circuit for driving a half-bridge stage having high- and low-side power switching devices series connected at a switched node, the high-side driver driving the high-side power switching device.

Abstract: A power on control device and method are used at an adaptor providing a constant voltage. The power on control device includes a first voltage converting circuit, a second voltage converting circuit, a third voltage converting circuit, and a comparison module. The first voltage converting circuit receives the constant voltage and generates a reference voltage. The second voltage converting circuit receives the constant voltage and generates operating voltages. The third voltage converting circuit receives the operating voltages and generates preparatory voltages corresponding to the operating voltages according to the operating voltages. The comparison module outputs a power good signal when all the preparatory voltages are larger than the reference voltage.

Abstract: Methods and apparatus for properly biasing differential comparators are provided. Using a feedback relationship, a bias for a main stage that receives a first differential input of the comparator is produced. Separately, a feedback relationship produces a bias for a main stage that receives a second differential input. These biases, produced as a result of the feedback relationship between bias stages and stages that replicate the main stages, are applied to the main stages. The outputs of the differential comparator are differential outputs with improved common-mode rejection as a result of the feedback and replica biasing.

Abstract: A semiconductor integrated circuit has a sampling circuit which samples a potential of an input terminal, a dynamic comparator having a standby and a comparison mode which compares the potential of the input terminal and a reference potential, a switch for input signals connected between the input terminal and the dynamic comparator, a capacitor for comparator having one end connected between the switch for input signals and the dynamic comparator and another end connected to a fixed potential, and a timing control circuit which controls a timing to sample by sampling circuit, a timing to switch modes of dynamic comparator, and a timing to make switch for input signals conducting or blocking state. The timing control circuit makes the switch for input signals blocking state from conducting state before the dynamic comparator switches from standby mode to comparison mode, and terminates sampling by sampling circuit after switching modes.

Abstract: An amplifier includes: an operation amplifier including a positive input terminal and a negative input terminal; and a detector which detects that a difference between a voltage of the positive input terminal and a voltage of the negative input terminal is equal to or exceeds a predetermined value and outputs a detection signal.

Abstract: A voltage detection and sequencing circuit is provided, preferably on a single semiconductor chip, for applying a plurality of voltages to an electrical system in a predetermined sequence. The circuit includes a plurality of subsystems each adapted to detect one of a plurality of supply voltages at an input terminal and to supply the supply voltage to at least one output terminal in a predetermined sequence as controlled by a sequencing means.

Abstract: Calibration circuitry and method for maintaining constant signal detection thresholds for multiple signal receivers that receive data signals in the form of current signals. A value of one of the incoming current signals having a predetermined signal pattern is detected and used to generate threshold control signals for each of the signal receivers to control the data signal detection thresholds.

Abstract: A semiconductor leakage current detector of the present invention includes a first analog switch which causes a current to be measured to flow or to be cut off, a second analog switch which causes a reference current to flow or to be cut off, an integral capacitance element which is connected by the first analog switch and the second analog switch and is charged with the current to be measured or the reference current, a discharge unit which discharges the integral capacitor, and a comparison unit which compares the reference voltage with each of an integral voltage generated in the integral capacitor by a reference current after the discharge of the integral capacitor and an integral voltage generated in the integral capacitance element by the current to be measured after the discharge of the integral capacitor.

Abstract: A semiconductor device includes a differential circuit for receiving a differential signal at an input terminal and a detection circuit for outputting a detection signal when a predetermined signal is inputted to the input terminal. The detection circuit detects whether the differential signal becomes outside an electric input standard and outputs the detection signal.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a first switched capacitor comparator to be charged to a first reference voltage and to compare an input signal to the first reference voltage and to generate a first output signal when the input signal reaches the first reference voltage. A second switched capacitor comparator to be charged to a second reference voltage and to compare the input signal to the second reference voltage and to generate a second output signal when the input signal reaches the second reference voltage. Time between the first output signal and the second output signal is slew rate of the input signal.

Abstract: A voltage calibration system includes three main units, which are a voltage level trimming unit, a trim detection unit, and a trim control unit. The three units work in conjunction with each other during a trimming operation in order to identify a tap voltage that is closest to a target voltage. In one embodiment, the voltage calibration system may be used to calibrate a voltage regulator. Upon commencement of calibration, the voltage regulator's feedback loop is open, and the target voltage is selected as the input for the feedback port of the amplifier. The voltage regulator serves as a voltage comparator that compares each tap voltage to the target voltage. When the calibration is complete, regulator's feedback loop is closed and the closest tap voltage to the target voltage is used as the regulator's input.

Abstract: Methods and apparatus for properly biasing differential comparators are provided. Using a feedback relationship, a bias for a main stage that receives a first differential input of the comparator is produced. Separately, a feedback relationship produces a bias for a main stage that receives a second differential input. These biases, produced as a result of the feedback relationship between bias stages and stages that replicate the main stages, are applied to the main stages. The outputs of the differential comparator are differential outputs with improved common-mode rejection as a result of the feedback and replica biasing.

Abstract: System and method for detecting a reference signal. A preferred embodiment comprises a latch (such as the latch 320) and a filter (such as the filter 325). The latch tracks a reference signal at its input and reflects the reference signal at its output. The filter can be coupled to the output of the latch and may inject a delay to help eliminate the effects of glitches and noise. When the reference signal reaches a specified value, a control signal from the filter causes the latch to store the reference signal. A delay imparted by the filter ensures that the latch does not store the reference signal until a finite amount of time after the reference signal reaches the specified value.

Abstract: A comparator circuit includes at least one transconductance stage that receives two test voltages and two reference voltages. The transconductance stage produces two test currents that are proportional to the test voltages and two reference currents. A switching circuit is coupled to the transconductance stage. The switching circuit has two output terminals that are coupled to a conventional comparator stage. The switching circuit can combine the test currents with the reference currents to realize a differential swing comparison mode and a common-mode comparison mode as required for testing differential signals. Moreover, by disabling appropriate output signals from the at least one transconductance stage, a single-ended comparison mode is realized. By using two identical transconductance amplifiers, the non-linearity of the transconductance stage is advantageously canceled out.

Abstract: An apparatus and method for comparing two input voltages. The apparatus being a comparator circuit comprising a pair of series connected polycrystalline transistors, two capacitors and a switch, the switch being connected between the point of series connection of the transistors and a node to which one side of each capacitor and the gates of the transistors are connected in common, with the other side of each capacitor being operably connected to a respective input.

Abstract: A signal amplitude comparator which includes a first differential input circuit that is biased, is configured to receive an input voltage and is configured to generate a first output current that is a non-linear function of the input voltage, a second differential input circuit which is biased similarly to the first differential input circuit, is configured to receive a reference input voltage and is configured to generate a second output current that generally tracks process, temperature and supply variation, and a comparator which is connected to the first differential input circuit and the second differential input circuit and is configured to receive the first output current from the first differential input circuit and the second output current from the second differential input circuit. The comparator is configured to compare the first and second output currents and generate an output which indicates whether the input voltage exceeds a pre-determined threshold value.

Abstract: An automatic input threshold selector includes a maximum value level decision circuit, and an input threshold setting circuit. The maximum value level decision circuit decides, among m+1 level layers defined by m maximum value decision levels, a level layer to which the maximum value of an input signal belongs. The input threshold setting circuit sets an input threshold by selecting one of n input threshold candidates in response to the level layer to which the input signal maximum value belongs. These circuits are implemented as a simple combination of a voltage comparator, logic gates and the like. This makes it possible to solve a problem of a conventional automatic input threshold selector in that its circuit scale and power consumption is rather large because it includes a peak-hold circuit and a bottom-hold circuit.

Abstract: A circuit configuration generates an internal supply voltage for integrated circuits at two different levels, each of which are constant. The selection of the levels is made solely on the basis of the magnitude of an external supply voltage. As a result, it is possible to switch back and forth between an operating mode, in which the internal supply voltage is at a usual value for operation, and a test mode, in which the internal supply voltage is at an elevated value. The invention is used particularly in semiconductor memories.

Abstract: An integrated circuit comprises at least one differential input stage. The differential input stage includes an input circuit and a shaping circuit. The input circuit comprises a first portion and a second portion for providing two pairs of differential signals. The propagation times of the first and second circuit portions are preferably substantially identical. The shaping circuit differentiates each of the two pairs of differential signals and combines them to obtain a single binary type of signal.

Abstract: A synchronization control scheme that provides a drive signal to a plurality of switching circuits and method of operation therefor.

Abstract: A current comparator arrangement has first and second inputs (100, 103), an output (105), and cross-coupled transistors (MP1, MP2) which form a latching circuit. The arrangement also includes current stores (MP3, MP4), the input currents to be compared being fed to the current stores in a selected forward differential order for storage therein during a first portion of a clock period in which the cross-coupled latching circuit is reset. During a second portion of the clock period the input current connections are reversed, thereby reversing their differential order, and the reverse order currents are supplied together with the stored forward order currents to the latching circuit. This cancels common mode and offset currents so that they do not affect the comparison of the input currents.

Abstract: A plurality of battery/voltage polarity switching circuits are constrained to operate in switching synchronism by a timing circuit associated with each polarity switching circuit that are interrelated to one another such that only the fastest response timing circuit is operative to supply a common synchronizing signal to all the polarity switching circuits.

Abstract: An address transition detector circuit according to the present invention comprises an input terminal, a one-shot pulse generator circuit having an input electrically connected to the input terminal, a first switching device electrically connected between a first and second nodes and brought into a conducting state in response to a one-shot pulse output from the one-shot pulse generator circuit, a second switching device electrically connected between a ground potential node and the second node and driven in response to a signal input to the input terminal, a plurality of switching devices parallel-connected between the first and second nodes and respectively driven in response to a plurality of address transition one-shot pulse signals, and power source potential supplying means for supplying a power source potential to the first node.

Abstract: A signal processing device for selectively producing as an output signal either a signal corresponding to an input signal r a signal which may be a fixed voltage level for muting purposes or a mixed signal. A current switch composed of pairs of differential transistors switches Among a plurality of current paths in accordance with a difference between the voltage levels of a pair of input signals varying in level in phase opposition to each other, or in accordance with a difference between the voltage levels of a reference voltage and a signal phase input signal. A load circuit composed of a plurality of resistors is connected in series with one of the current paths. A current bypass forming circuit which forms a current bypass of a constant current at a desired timing corresponding to a pulse signal with respect to the current path forming the load circuit effects the generation of an output signal not corresponding to the input signal, that is, a fixed voltage for muting the mixed signal.

Abstract: A circuit for unambiguously indicating the presence and comparative values of output signals from a plurality of sensors includes first and second comparators respectively providing first and second comparison signals having high or low logic levels. A source of reference voltages provides individual reference voltages to one input terminal of each of the comparators. A first sensor is arranged between a source of operating potential and a second input terminal of the first comparator. The first sensor switches the operating potential on and off of the second input terminal in accordance with the reception of energy by the first sensor to vary the output terminal of the first comparator between high and low logic levels when the reference potential exceeds the operating potential. A second sensor arranged is between the source of operating potential and the second input terminal of the second comparator.

Abstract: A comparator circuit, for a switched resistive network which may be combined with a transconductance amplifier, simultaneously and independently compares a plurality of input voltages to a reference voltage. The circuit comprises a current splitter having a current input, a plurality of comparator outputs, and a corresponding plurality of voltage inputs that control the fraction of the input current available at each comparator output. A reference output of the current splitter is provided as an input to a current mirror, and each of the comparator outputs of the current splitter is connected to a corresponding output of the current mirror. The current available at each of the current mirror outputs is a function of the reference input provided from the current splitter. The comparator circuit needs only one bias input and one reference input. The inclusion of a second biasing device with an associated mirror device produces a transconductance amplifier combined with the comparator circuit.