Abstract: A demodulation system and method is used in a sensor system, such as a fi optic sensor system, that senses optical signals and modulates a phase generated carrier having a carrier frequency .omega..sub.c to form a modulated carrier. The modulated carrier is preferably undersampled at three times the carrier frequency (3.omega..sub.c), thereby maximizing the sensors' demodulated bandwidth relative to the sensors' sampling frequency. The undersampled, modulated carrier is orthogonally demodulated by multiplying the undersampled, modulated carrier by cos(.omega..sub.c (t.sub.o)) and sin(.omega..sub.c)(t.sub.o)) to extract even and odd harmonic components of the signal of interest.

Abstract: The demodulator of this invention is directed toward improving S/N ratio of the demodulator resulting from increase in the peak value of a received signal due to fading. The demodulator is composed of a roll-off filter (not shown), variable amplifier 16, multiplier 10, compressor 11, variable dynamic range analog/digital converter 12, transversal filter 13, expander 14, tap coefficient control circuit 15, and signal level detector 17. Signal level detector 17 detects the magnitude of waveform distortion from the output of tap coefficient control circuit 15 and controls the gain of variable amplifier 16 and the dynamic range of analog/digital converter 12, thereby reducing nonlinear distortion in multiplier 10 that is caused by increases in the peak value due to waveform distortion.

Abstract: A receiver is arranged for receiving a transmitted quadrature amplitude modulated (QAM) signal representing successive symbols, and including an in-phase (I) component and a quadrature (Q) component. In such a receiver, a timing recovery system includes a source of samples representing the QAM signal produced at a fixed frequency. A first chain of processing circuitry for the I component includes a first demodulator, coupled to the sample source, for demodulating the I component of the QAM signal to baseband; and a first interpolator, coupled to the first demodulator and responsive to a control signal, for producing I component samples taken at times synchronized to the transmitted symbols.

Abstract: For demodulation of higher-level MQAM signals without knowledge of the transmitted symbols, the clock phase error is calculated first after the sampling of the baseband signal with a clock frequency corresponding to the MQAM signal, and the corresponding time shift of the baseband signal is compensated therewith by interpolation (clock synchronization). Subsequently, the carrier frequency deviation and the carrier phase deviation are calculated feedback-free according to the principle of the maximum likelihood theory using Fourier transformation or by convolution in the time domain, and thus the data sequence is compensated.

Abstract: A low cost, high performance near direct conversion FM receiver having a single local oscillator is configured to equalize in-phase and quadrature-phase IF signals. The receiver includes a downconverter and a processor. The downconverter receives an RF signal and downconverts the RF signal to an in-phase IF signal (IF.sub.I) and a quadrature-phase IF signal (IF.sub.Q). The processor digitizes IF.sub.I and IF.sub.Q, corrects these signals so that they are substantially equal in magnitude and substantially 90.degree. out of phase, and then downconverts the IF signals to baseband signals (I, Q).

Abstract: A method for correcting an amplitude error between an I signal and a Q signal which are outputted from a quadrature detector including a first multiplier for multiplying a reference signal and a measured signal, a first integrator for smoothing the output of the first multiplier to generate the I signal, a 90-degree phase shifter for generating an auxiliary reference signal from the reference signal, a second multiplier for multiplying the auxiliary reference signal and the measured signal, and a second integrator for smoothing the output of the second multiplier to generate the Q signal. The method includes the step of inputting the auxiliary reference signal, instead of the reference signal, to the first multiplier to obtain a first output signal and inputting the reference signal, instead of the auxiliary reference signal, to the second integrator to obtain a second output signal.

Abstract: The detector comprises a first distributor for distributing a signal wave, a 45 degree shifter for shifting a local oscillation, a first even harmonic mixer and a second even harmonic mixer for generating a mixed wave between a double frequency wave of said local oscillation wave and said signal wave. The present invention can be used for increasing the accuracy and downsizing of quadrature mixer used in a receiving transmitting apparatus of a wireless communication system.

Abstract: Digital demodulator for a quadrature-modulated signal (sq) which transmits a combination signal by amplitude and phase modulation. A quadrature-signal source provides a digitized in-phase component (I) and a digitized quadrature component (Q) of low frequency. A resolver converts the two components (I,Q) into a magnitude signal (b) and a first phase signal (p1). A first feedback control loop and a second feedback control loop that maintains the slope (mp) of the first phase signal (p1) at the zero value and the time average (pm1) at the zero phase position, whereby a third phase signal (p3) is formed. From the resulting signals (b, p3, p3') a decoder forms at least one of the required components (R,L,P).

Abstract: A low power zero-IF selective call receiver has a local oscillator (106) that generates an injection signal for a first mixer (104) and a pair of quadrature phase related injection signals (122, 124) for a pair of second mixers (112, 114). The first mixer converts the received carrier signal (102) to an intermediate signal (108). A digital phase shifter/divider (116) coupled to the local oscillator (106) generates the pair of quadrature phase related injection signals (122, 124) at the frequency of the intermediate signal (108) which also equals the frequency of the local oscillator (106) divided by an integer greater then 1. The pair of second mixers (112, 114) coupled to the digital phase shifter/divider (116) converts the in and quadrature phase components (122, 124) of the intermediate signal (108) to respective in and quadrature phase baseband signals (126, 128).

Abstract: A demodulator stage for direct demodulation of a phase quadrature modulated signal provides two baseband signals and comprises a matched 900.degree. coupler to which the modulated signal is fed and supplying two phase quadrature modulated signals. Two low-noise amplifiers with identical specifications each receive one of the phase quadrature modulated signals and supply an amplified signal. Two mixers each receive one of the amplified signals and a common local oscillator signal and supply the baseband signals. The 90.degree. coupler, the low-noise amplifiers and the two mixers can be integrated into the same MMIC. One application is to a receiver for frequency evasive phase quadrature modulated signals.

Abstract: A clock recovery circuit based upon an early-late gate approach is applied to high speed serial communication links using NRZ data. The circuit has no systematic phase offset and therefore requires no external phase adjustment circuits or mechanisms. The circuit is used in high speed integrated receivers for applications including fiber optics, disk-drive read/write electronics, mobile communications and high rate- twisted pair data transmission in multimedia systems. Quadrature samples are obtained and held which follow the shape of the NRZ data transition as a function of phase offset. The data signal is passed through the limiter giving rise to a sawtooth shaped phase error signal. A derivative of the error function is taken to provide a frequency error signal to provide for frequency detection and assistance in frequency acquisition of the phase lock loop circuit generating the recovered clock signal from a variably controlled oscillator.

Abstract: A device and a method correct deviation when transferring an information-carrying signal between a transmitter and a receiver. The transmitter can transmit with a plurality of frequencies generated by a voltage-controlled oscillator used for phase demodulation. The receiver demodulates the modulated information-carrying signal. A detector measures the deviation of the modulated information-carrying signal via the information-carrying signal demodulated in the receiver. The frequencies of the demodulated information-carrying signal can be adjusted so that the correct deviation is obtained, and a correct phase demodulation can be carried out.

Abstract: The invention provides a quadrature demodulator which removes unnecessary higher harmonic signals included in a demodulation output without giving rise to increase in number of externally connected parts and increase in current consumption. The quadrature demodulator includes a first double differential circuit to which a modulated signal and a first local signal are inputted, a first emitter follower circuit for effecting impedance conversion, a second double differential circuit to which the modulated signal and a second local signal having a phase shifted by 90-degrees from the first local signal are inputted, and a second emitter follower circuit connected to a pair of outputs of the second double differential circuit for effecting impedance conversion.

Abstract: When a signal modulated by a multi-subcarrier modulation scheme is to be demodulated, an amplitude detection unit sequentially detects the amplitudes of a subcarrier-synthesized signal to accurately set a symbol discrimination timing for the modulated signal within a short period of time. A reference amplitude storage unit stores a reference amplitude at a portion corresponding to a predetermined reference symbol portion included in the received signal. A correlation calculation unit sequentially calculates correlation values between amplitudes sequentially detected by the amplitude detection unit and the reference amplitude. A discrimination timing determination unit determines a symbol discrimination timing on the basis of time representing a maximum value of the correlation values sequentially calculated by the correlation calculation unit. When the signal modulated by the multi-subcarrier modulation scheme is to be demodulated, a phase detection unit detects a phase .theta.

Abstract: The number of oscillators required to construct a digital radiocommunication terminal can be reduced and a circuit used for the digital radiocommunication terminal can be reduced in size. For this purpose, the digital radiocommunication terminal for effecting information transmission using an N (integer)-phase-shift-keyed signal (identification symbol number N=4 upon .pi./4 shifted QPSK modulation), is constructed such that an oscillation frequency generated from a reference oscillator employed with a frequency synthesizer is selected to have a common multiple of a second intermediate frequency and an identification symbol phase N and is supplied to a detector for outputting received data therefrom.

Abstract: The phase of a received signal is detected by a phase detector at symbol intervals T relative to the phase of a local signal. The detected phase is input to delay circuits that are connected in series and each of which has the delay interval T. Phases .PSI..sub.n (where n=0, 1, . . . , N) with delays of 1 to N symbols are output to a metric calculating portion. The sum of a partial sequence {.DELTA..phi..sub.i ; i=n+1-q, n+2-q, . . . , n} of a N-symbol phase difference sequence candidate {.DELTA..phi..sub.n ; n=0, 1, . . . , N} is added to a detected phase .PSI..sub.n-q at a time point (n-q)T (where q=1, 2, . . . , N) so as to obtain an estimated value of the received signal phase .PSI..sub.n. The v-th power value of the absolute value of a difference .mu..sub.n (q) between the estimated value and the received signal phase is defined as a branch metric of q-symbol differential phase detection. .SIGMA..vertline..mu..sub.n (q).vertline..sup.v =.lambda..sub.

Abstract: In a digital data demodulating apparatus, total number of low-pass filters is reduced by supplying variable sampling clock signals to A/D converters coupled to the low-pass filters. The digital data demodulating apparatus for receiving/demodulating a transmission signal that is modulated by digital data in a predetermined modulation manner, includes: a detecting unit for detecting the transmission signal; a low-frequency component passing unit for causing a low-frequency component of the transmission signal detected by the detecting unit to selectively pass therethrough; an analog-to-digital (A/D) converting unit for A/D-converting the output from the low-frequency component passing unit into a digital transmission signal; a demodulating unit for demodulating the digital transmission signal from the A/D converting unit; and a switching unit for switching a frequency of a sampling clock produced from the A/D converting unit in response to an external switching instruction.

Abstract: To receive a response signal from a radio card, a card reader transmits a carrier (not modulated) to the radio card. In the radio card, a phase modulator phase-modulates the a sub-carrier with a response signal, thereby generating a PSK signal, and a phase modulator phase-modulates the carrier with the PSK signal, producing a PSK-PSK signal. The PSK-PSK signal is supplied to an antenna via a signal-extracting device. The antenna sends the PSK-PSK signal toward the card reader. In the card reader, a distributor distributes the PSK-PSK signal to a synchronous detector and an orthogonal detector. The detectors performs synchronous detection by using carriers which differ in phase by 90.degree.. Low-pass filters extract sub-carrier components from the outputs of the detectors. The sub-carrier components are delayed and detected by delay detectors and added together by an adder.

Abstract: In a reference signal adaptive estimation part 15, a received signal sample z.sub.n-2 at time (n-2) is phase rotated by M states .DELTA..phi..sub.n-1 at time (n-1), and the phase-rotated signal and a received signal sample z.sub.n-1 are used to calculate the following linearly predicted value of the received signal sample at time (n-1) that contains a fading variation at time n,z.sub.n-1 =(1+.lambda.)z.sub.n-1 -.lambda.z.sub.n-2 exp(j.DELTA..phi..sub.n-1).A square error between a signal phase-rotated .DELTA..phi..sub.n from the linearly predicted value z.sub.n-1 and a received signal sample z.sub.n is calculated as a branch metric in a branch metric calculating part 16 and this branch metric is used for decoding in a Viterbi decoding part 17. A prediction coefficient .lambda.

Abstract: A clock recovery circuit capable of outputting decision point data without causing any slip of a recovered clock in the case of operation in a continuous mode in a demodulator in which received signals are sampled by a fixed frequency clock to obtain the recovered clock and symbol data are demodulated by using this recovered clock. A shift register stores digital received signals obtained by an A/D conversion of quasi-coherent detection received signals, and a clock phase estimator calculates an estimated phase difference between an output value of a phase generator operated by the fixed frequency clock and a symbol clock of the received signals and outputs timing information and phase information of a decision point for discriminating the data of the received signals. An interpolator inputs the output signal of the clock phase estimator, takes in the digital received signals from the shift register and calculates decision point data by interpolation to output the same.

Abstract: For demodulating a phase-modulated signal having 2M states of a carrier (M being an integer), the signal is converted into two baseband signals in quadrature. For that, they are multiplied by a signal delivered by a local oscillator at a transposed carrier frequency. Then the baseband signals are digitized by sampling at the clock frequency of the modulating signal. The clock of the signal is recovered by adjusting the phase of a local clock, stabilized at a bit frequency. For that, a minimum value of the intersymbol interference is searched. The signal clock is recovered before the carrier is recovered. Devices for implementing the method are also disclosed.

Abstract: A first AFC apparatus receives and detects I and Q signals from a received first FSK signal with a local osc signal; demodulates the I and Q signals; F/V-converts I or/and Q signals into a voltage; compares it with a reference; and detects a frequency deviation direction of the local osc signal from the carrier signal according to the results of comparing and the demodulating. The local osc frequency is controlled by a given amount according to the result of the frequency deviation direction detection. A second AFC apparatus receives and detects I and Q signals using a first osc signal; FSK-modulates the I and Q signals with a second local osc signal having a lower frequency than the first local osc signal; and compares the frequency of the second FSK signal and the second local osc signal to supply a demodulation result. A frequency control for the first local osc signal is obtained by an averaging circuit averaging the modulation result.

Abstract: A demodulator (18) which receives digital representations of a received signal converts those signals into analog signals (53) in a pair of multiplying analog-to-digital converters (MDACs) (21, 22) The analog signals are then combined in combiner (26) by subtracting the first analog signal from the second analog signal (54). The summed signal is normalized (55) in quantizer (27). The output from the quantizer (27) is accumulated (56) in an n-bit accumulator (28) as regulated by a clock input (Fclock). The output of the accumulator (28) is used as a programming input (57) to the MDACs (21, 22).

Abstract: A received signal sample sequence is inversely modulated by a symbol sequence forming the trellis state at the immediately preceding time, by which a reference signal is generated. This reference signal and the inner product of the received signal sample at the current time and a candidate symbol phase are used as a branch metric to make a sequence estimation by the Viterbi algorithm.

Abstract: A frequency control circuit for a receiver of phase shift keying (PSK) modulated signals comprises intermediate frequency (IF) signal generation circuit for generating an IF signal from a local oscillation signal. A measurement circuit measures the frequency of the IF signal. A detection circuit detects the frequency shift due to the PSK modulation to output a frequency shift signal in response to a first control signal. A control circuit detects that the frequency of the IF signal is converged until the detection circuit can detect the frequency shift due to the PSK modulation.

Abstract: The invention relates to a method for demodulating a digitally modulated signal and to a demodulator. According to the method, a signal (S) to be received is mixed essentially to quadrature related I and Q baseband signals. For improving the interference tolerance of the demodulator, for instance, differences (.alpha.) between directional angles (.beta., .gamma.) of sequential shifts of a signal point on I/Q plane are measured from the baseband signals and said difference is utilized for decision-making concerning a received symbol.

Abstract: A complex baseband signal as long as one period of PN signal is divided into three sequences. The three partial signals are input to three correlators which then calculate the correlations between the three partial signals and three partial PN signals. The squares of the absolute values of outputs from the three partial correlators are summed and the peak of the resultant summed signal is detected, thereby performing initial acquisition and tracking of synchronization of PN signal. Outputs from the three partial correlators are added together by an adder for generating a correlation signal used for data demodulation. Since partial correlation signals output from three partial correlators have a phase difference corresponding to a frequency offset, and error signal corresponding to the frequency offset is provided by performing complex conjugate product operations on the partial correlation signals.

Abstract: A coherent phase-shift keying (PSK) detector in a receiver generates an unmodulated carrier signal, without attempting to synchronize the unmodulated carrier signal in frequency or phase to the carrier employed at the PSK transmitter. The instantaneous phase of the received PSK signal is detected with reference to the unmodulated carrier signal to create an instantaneous phase signal. Phase rotation due to frequency offset between the two carrier signals is detected and removed from the instantaneous phase signal, then a remaining phase offset is detected and removed. Data are recovered from the resulting instantaneous phase signal.

Abstract: A frequency-controlled circuit for automatically detecting a center frequency of a received signal whose frequency is shifted includes a frequency control unit for receiving the input signal and changing the frequency of the received signal into another frequency, a demodulating unit for demodulating a signal outputted from the frequency control unit, an incoming detecting unit for detecting whether a demodulated signal outputted from the demodulating unit is proper or improper and a level detecting unit for dividing a frequency band of the signal, obtained in the frequency control unit by adding a receive frequency band of the received signal to the center frequency of the received signal or subtracting the center frequency thereof from the receive frequency band thereof, into a plurality of narrower frequency bands and detecting respective power values of the divided frequency bands.

Abstract: A demodulator responsive to a symbol containing analog signal includes a pair of relatively inexpensive analog-to-digital converters for sampling I and Q channels of the signal only once per symbol. A derotator responsive to outputs of the converters and a digital signal representing frequency and phase corrections for an input to the demodulator operates in accordance with a CORDIC function to derive I and Q channel digital signals that are compensated by the corrections. A digital phase shifter responsive to at least one of the digital I and Q signals controls when the input is sampled by the converter.

Abstract: An intermediate frequency (IF) to baseband frequency signal converter for decoding an analog IF signal using phase information contained in the IF signal includes a first signal generator for generating an analog square wave signal from the IF signal. The signal converter also includes a second signal generator for generating a local phase reference signal, and a phase difference determinator for determining at a particular sampling interval a phase difference between a phase of the analog square wave signal and a phase of the local phase reference signal, wherein the phase difference represents a symbol which the signal converter has decoded from the IF signal.

Abstract: In detection of a frequency error of a local frequency for quadrature demodulation of a received signal by sampling (S2) each burst of the received signal by a sampling signal at a sampling period into a predetermined number 2m of sampled vectors, zeroth to (2m-2)-th phase errors are calculated (S3), each phase error accompanying a phase difference which is between two adjacent ones of the sampled vectors and is constant during each burst. Zeroth to (m-1)-th averages are calculated (S4(1)) as regards m consecutive ones of the phase errors with each average calculated starting at a q-th phase error of the phase errors and with q varied between zero and (m-1), both inclusive. A mean value of these m averages is calculated (S4(2)) and is divided (S5) by a divisor comprising the sampling period. The frequency error is given by a quotient of this division. The received signal is derived by reception of a transmitted signal subjected to digital angle modulation, such as GMSK or MSK modulation.

Abstract: A digitized quasi-phase synchronous phase detecting signal of the PSK signal is used to generate digitized quasi-synchronous phase detecting signal phase-corrected by phase correcting data and a first phase display data indicating the phase of the carrier of the PSK signal is generated from the phase-corrected digitized quasi-synchronous phase detecting signal. Alternatively, the digitized quasi-synchronous phase detecting signal of the PSK signal is used to generate second phase display data indicating the phase of the carrier of the PSK signal and third phase-corrected phase display data is generated from the second phase display data. The first or third phase display data is used to generate fourth phase display data indicating the phase assigned to the code of the PSK signal and a decoded digitized code is generated from the fourth phase display data.

Abstract: A technique of demodulating a .pi./4-DQPSK composite carrier waveform using a non-coherent discriminator based receiver is presented. In particular, a means of recovering .pi./4-DQPSK modulated data symbols using a dual output discriminator in conjunction with a dual binary amplitude detection process in a discriminator based receiver is discussed. Means which improve the bit error rate of the receiver over the prior art are presented. Additionally, an amplitude detection means which readily provides synchronization of the detected data symbols is discussed which was not heretofore possible with the 4-level slicer of the prior art.

Abstract: In a phase detector, an input signal (Si) is multiplied in a multiplier by two reference signals intersecting at right angles with each other. Signals obtained by multiplication are passed through filters and subjected to quadrature demodulation. An I signal and a Q signal obtained by quadrature demodulation are input to non-linear compression circuits and compressed by logarithmic conversion. Based on the compressed I and Q signals, a phase detection circuit detects the phase of the input signal (Si).

Abstract: A phase detection system in which an original modulation signal is detected from a first complex baseband signal obtained through orthogonal demodulation of an FM signal and output, a second complex baseband signal having cosine and sine components of a phase change .DELTA..phi. of the first complex baseband signal in a predetermined time interval .tau. is rotated until a rotation angle .theta. becomes .DELTA..phi., and rotation angle data indicative of the rotation angle .iota. is detected and output.

Abstract: An automatic frequency control apparatus includes a frequency converter, an analog/digital converter, extractor, a storage unit, a controller, and a local oscillator. The storage unit stores unique word frequency modulation models representing time waveforms obtained by modulating, with a unique word, three frequencies which are a frequency equal to that of a desired intermediate-frequency signal, a frequency slightly higher than that of the desired intermediate-frequency signal, and a frequency slightly lower than that of the desired intermediate-frequency signal.

Abstract: A QAM demodulator that samples an IF input modulated with data at a fractional complex sampling rate between one and two times the data rate. The use of a fractional sampling rate significantly reduces the number of components necessary to implement the demodulator, particularly in the equalizer section of the demodulator which corrects for channel distortion. The fractional sampling rate demodulator architecture of the invention provides a significant reduction in integrated circuit surface area needed in a VLSI implementation.

Abstract: Within the differential detection demodulator, the received signal is first quantized by a limiter amplifier and then subjected to frequency conversion by a frequency converter including: an exclusive OR element; a running average generator consisting of a shift register and an adder; and a comparator. In response to the output of the frequency converter, the phase comparator outputs a relative phase signal representing the phase shift of the received signal after frequency conversion relative to the phase signal representing the phase shift of the received signal after frequency conversion relative to the phase reference signal. The phase comparator includes: an exclusive OR element; an absolute phase shift measurement means consisting of an adder and D flip-flop arrays and; and a D flip-flop serving as a phase shift polarity decision means.

Abstract: Open-loop phase estimation methods and apparatus for coherent demodulation on mobile channels is disclosed. A PSK RF modulated signal is received, RF demodulated to obtain inphase and quadrature components thereof, and the inphase and quadrature components sampled and digitized periodically to provide inphase and quadrature components of the signal vector. A phase estimator strips the data contribution from each vector, leaving only a phase error measurement related to the true phase error. That phase error indication is averaged over a fixed window of time to determine an average phase estimate applicable to the signal vector at the middle of the window. Resulting one hundred eighty degree ambiguities are resolved, and then the applicable signal vector is phase corrected by the average phase estimate and result of the ambiguity resolution, with the following demodulation being responsive to the phase of the phase corrected signal vector.

Abstract: An I/Q-modulator or I/Q demodulator circuit in which the modulating signals (2, 3) are input through the output phase transfer branches of the circuit. In relation to the RF-characteristics, a series resistor (16) and a series inductance (20) in the phase transfer circuits are grounded with small capacitors (23, 25). A capacitor (17) having a high impedance at the modulating frequency is located between the branches. Tho modulating signals are not summed through the capacitor (17), and, thus, their phase difference is not weakened.

Abstract: A communication device (100) includes mixers (104) and (108) which mix a local oscillator (112, 106) with a received signal to produce in-phase (i) and quadrature (q) components. The direction of the phase of the signal is detected as it crosses the i and q axes. The direction of the phase rotation is kept track of by a bi-directional counter (123) in order to demodulate multi-level digital signals. A positive rotation increments the bi-directional counter (123). Conversely, a negative direction decrements the counter (123). The final count of the counter (123) is used by a decision device 124 to establish the content of the received information signal.

Abstract: A frequency/phase detector for a reference signal with a fixed frequency and a second signal with a variable frequency comprises essentially a frequency discriminator, already known, in which the output signal of a frequency-dependent phase-shifting circuit centered on said fixed frequency is applied, not directly to a demodulator circuit but through a summing circuit that receives in addition said reference signal.

Abstract: A demodulation circuit (10) performs quadrature demodulation on an IF input signal. The IF input signal processes through a preamplifier (12) to one input of a mixer (14). The mixer output goes to first and second multipliers (20, 22). A VCO (24) generates an oscillator signal that processes through a first multiplier (26) and first and second dividers (28, 30) to generate in-phase and quadrature recovered carrier signals that are applied to second inputs of the first and second multipliers which in turn produce the in-phase and quadrature demodulated baseband signals. A switching arrangement (32, 38, 40) for the multiplier and dividers provides the proper frequency signal to a second input of the mixer to generate sum and difference frequencies. A filter and amplifier at the output of the mixer removes the summation frequency leaving the difference frequency to the first and second multipliers.

Abstract: A frequency stabilizing circuit for a .pi./4 QPSK (Quadrature Phase Shift Keying) signal receiver has a voltage controlled oscillator (VCO) for outputting an oscillation signal whose frequency changes in response to a control voltage applied to the VCO. A mixer changes the frequency of an input .pi./4 shift QPSK signal. A counter measures the frequency of the .pi./4 shift QPSK signal from the mixer. A timing generator generates, on the basis of the oscillation signal from the VCO, a timing indicative of an interval during which the counter is to measure the frequency. A set data generator generates a frequency signal having a predetermined set frequency. A comparator compares the frequency measured by the counter and the set frequency of the set data generator to thereby output the resulting frequency deviation. A voltage data generator changes voltage data in association with the frequency deviation. A digital-to-analog converter transforms the voltage data to the control voltage.

Abstract: This invention relates to an abnormal synchronization preventing device used in a multiple value quadrature modulation type radio device and the abnormal synchronization preventing device includes a monitoring circuit for monitoring the carrier pull-out based on demodulated base band signals to output a carrier pull-out alarm signal, an abnormal synchronization detection circuit for sampling the reception signal level at a speed twice the transmission speed of reception data according to identification data and detecting abnormal synchronization according to whether or not the detection area of sampled data lies in a specified area, an abnormal synchronization preventing circuit for generating a signal for a preset period of time when abnormal synchronization is detected in a case where the carrier pull-out alarm signal is not output, and a selection circuit for receiving a reference signal used for generating a reference carrier frequency signal having a frequency close to the frequency of the carrier wave a

Abstract: A device for demodulating a signal modulated on two axes in phase quadrature using a .pi./4-QPSK type digital modulation technique employing alternately two phase-shifted constellations. The device includes: a voltage-controlled oscillator (28) supplying a local signal substantially at the carrier frequency; a demodulator means using the local signal and supplying, after filtering (30, 31), the phase component P and quadrature component Q of the demodulated received signal; a phase controller (32) producing a control signal (39) for controlling the oscillator (28) and including a phase estimator (33) producing a phase estimation signal E (35) involved in control of the oscillator (28), the phase estimation signal being derived from the phase component P and quadrature component Q of the demodulated received signal.

Abstract: A data receiver receives differential phase-shift keyed (DPSK) signals, and filters the signal by a process including frequency conversion, under the control of an estimated carrier frequency (f.sub.re), to produce a filtered output signal which is applied to a DPSK demodulator. The filtering compensates for the Doppler frequency errors, and reduces the phase error. The estimated frequency is determined by second and third controllable filters, which filter the DPSK carrier signal at frequencies above and below the estimated carrier frequency by an offset frequency which depends on the data rate. A first frequency error estimate is made in a processor coupled to the second and third filters, from the ratio of the amplitudes of the first and second filter output signals. A second-order tracking loop is coupled to the processor for averaging the frequency error estimate over a predetermined number of bits, to generate the estimate of the carrier frequency.

Abstract: An apparatus and method is provided of recovering a frequency modulated signal having a first component of the frequency modulated signal at a zero-RF spectral location and a second component of the frequency modulated signal at a zero-RF spectral location in quadrature relationship to the first component. The method includes the steps of: upconverting and summing the first and second components to produce a reference signal (100), time delaying the first and second components, upconverting and summing the delayed, upconverted first and second components to produce a delayed reference signal (101) in quadrature relationship to the reference signal; limiting the reference and delayed signal (102); and exclusive or-ing (103) the limited reference and limited delayed signal.

Abstract: A four quadrant multiplier circuit having a high dynamic range and capable of operating at low voltages includes a dual transconductance amplifier circuit (TAC) consisting of NPN transistors (20 to 23 and 64 to 67), coupled to a first input port (36), first and second folded Darlington circuits (57,58), and a resistive element (78). Each Darlington circuit includes first and second NPN transistors (68,70 and 69,71) whose emitter-collector paths are connected in series and a third PNP transistor (72,73) having its emitter-collector path connected between the collector of the first transistor (68,69) and the base electrode of the second transistor (70,71). The emitter-collector junction (76,77) of the first and second transistors (68,70 and 69,71) is connected to the base electrode of the third transistor (72,73). The resistive element (78) is connected between the base electrodes of the third transistors (72,73). A second input port (56) is connected to the base electrodes of the first transistors (68,69).