Abstract: An antenna device includes antennas to receive and transmit signals; and a processor to divide radiation patterns of combinations of the antennas into a predetermined number of characteristic patterns, and to calculate similarities of the characteristic patterns and a RSSI of each of the characteristic patterns. When the antenna device is in operation, the processor reads and analyzes RSSI of the signals received by the antennas, compares the RSSI of the signals of the antennas with the RSSI of the characteristic patterns, and determines a matched characteristic pattern group according to results of comparisons and the similarities of the characteristic patterns.

Abstract: The present invention provides a receiving circuit, wherein the receiving circuit includes a first ADC, an attenuator, a second ADC, a harmonic generation circuit and an output circuit. In the operations of the receiving circuit, the first ADC performs an analog-to-digital operation on an analog input signal to generate a first digital output signal, the attenuator reduces strength of the analog input signal to generate an attenuated analog input signal, the second ADC performs the analog-to-digital operation on the attenuated analog input signal to generate a second digital input signal, the harmonic generation circuit generates at least one harmonic signal according to the second digital input signal, and the output circuit deletes a harmonic component of the first digital input signal by using the at least one harmonic signal to generate an output signal.

Abstract: An analog beamformer includes: an input circuit configured to receive an input signal to generate a first input signal having the same phase as the input signal and a second input signal having a phase difference corresponding to a first phase with respect to the input signal; a first delay circuit configured to delay the first input signal to output a first delayed signal; a second delay circuit configured to delay the second input signal to output a second delayed signal; and an output circuit configured to output an output signal by summing the first delayed signal and the second delayed signal, wherein a first write signal has the phase difference corresponding to the first phase with respect to a second write signal, and a first read signal has the phase difference corresponding to the first phase with respect to a second read signal.

Abstract: An antenna device includes a first antenna group comprising multiple antennas, configured to receive and transmitting signals; a second antenna group comprising multiple antennas, configured to receive and transmitting signals; a processor coupled to the first antenna group by a first electronic switch, coupled to the second antenna group by a second electronic switch, configured to divide radiation pattern of antenna combination of the first antenna group and the second antenna group into a predetermined number of characteristic patterns, and further configured to calculate similarities of the characteristic patterns and the RSSI of each characteristic pattern; wherein when the antenna device is in operation, the processor reads and analyzes RSSI of the signals, and compares with the RSSI of the characteristic patterns, and then determines the matched characteristic pattern group according to results of the comparisons and the similarities of the characteristic patterns.

Abstract: According to some embodiments, a system for securing communications between an implantable wearable medical device (IWMD) and an external device (ED) is disclosed. The system includes a wireless radio frequency (RF) channel configured for communication between the IWMD and the ED. The system further includes a vibration-based side channel configured for verifying communication between the IWMD and the ED such that the RF channel is activated only when the IWMD detects a vibration signal generated by an ED.

Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase.

Abstract: A method for autonomous mower navigation includes receiving a return-to-zero encoded signal including a pseudo-random sequence, transforming the received signal to a non-return-to-zero representation, digitally sampling the non-return-to-zero signal representation in a time domain, filtering the sampled signal utilizing a reference data array based on the return-to-zero encoded signal to produce a filter output, and determining a location of the autonomous mower relative to a defined work area based on an evaluation of the filter output.

Abstract: A terminal in a communication system is provided. The terminal includes a transmitter configured to transmit a data frame including one preamble and a plurality of data blocks to another terminal by considering whether a preset signal is received, and a receiver configured to detect the preset signal from a signal received through an antenna while the data frame is transmitted by the transmitter.

Abstract: Embodiments described herein provide an electronic device, which includes a first oscillator configured to output a first clock signal, and a second oscillator that is co-located with the first oscillator on the electronic device. The electronic device further includes a first bandpass filter configured to filter a first input signal derived from the first clock signal received through a negative feedback loop, and to output a first signal component corresponding to the first signal spur. The electronic device further includes a signal reconstruction circuit configured to receive the first signal component and to combine the first signal component into a control signal for the first oscillator, and to feed the control signal combined with the first signal component to the first oscillator to mitigate the first signal spur exhibited in the first clock signal.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, by a first device, that a second device is within range for direct communications and that the second device is capable of performing transpositional modulation (TM) communications. Determining to use transpositional modulation to send data to the second device. Sending the data to the second device using a TM signal.

Abstract: Systems and methods are provided for detection and compensation of frequency drifts. Frequency related information may be determined for each of one or more channels in an input signal, and a frequency drift may be determined based on the determined frequency related information of the one or more channels. Frequency related adjustments may be determined based on the frequency drift, and the frequency related adjustments may be applied to different circuits used during one or more of: receiving of the input signal, processing of the input signal, processing of an intermediate signal generated based on the processing of the input signal, and generating of an output signal corresponding to the input signal. Applying the frequency related adjustments may be configured to meet one or more criteria.

Abstract: An example a processing system for a capacitive sensing device includes a reference transmitter coupled to a reference capacitance. The processing system further includes a charge accumulation circuit having an input coupled to the reference transmitter through the reference capacitance and configured to generate an integrated signal, a demodulator circuit having an input coupled to an output of the charge accumulation circuit and configured to demodulate the integrated signal to generate at least one demodulated signal, a sampling circuit having an input coupled to an output of the demodulator circuit and configured to sample the demodulated signal(s), a first reference buffer coupled to an output of the sampling circuit, the first reference buffer outputting a first voltage reference for the capacitive sensing device, and a second reference buffer coupled to the output of the sampling circuit, the second reference buffer outputting a second voltage reference for the capacitive sensing device.

Abstract: A transmitter for a high speed serial communications link, a serial communications link, and a receiver for a high speed serial communications link are disclosed herein. In one embodiment, the transmitter includes: (1) a communications interface connected to a transmission medium having multiple lanes, and (2) a safe mode circuit coupled to the communications interface and configured to send data over the transmission medium in a safe mode, wherein in the safe mode at least one of the lanes is dedicated to transmitting a link detect signal for link detection.

Abstract: A device, a circuit and a method are disclosed herein. The device includes a data receiving circuit and an oscillating signal generator. The data receiving circuit is configured to output a first output signal, a second output signal, and a phase error signal according to an oscillating signal and a modulated signal, in which the phase error signal indicates a phase difference between the oscillating signal and the modulated signal. The oscillating signal generator is configured to delay a phase of a first reference signal according to the phase error signal, to generate the oscillating signal.

Abstract: A reliable and precise measurement of tire tread wear, by using wide-band (UWB) pulses and analyzing the signature obtained by reflection of these pulses from the tread, in order to deduce its state of wear therefrom. The tire wear monitoring device (100) includes a control unit (110) for signal control and data processing, this control unit (110) being coupled to a generator of ultra wide band or UWB signals (120), which is itself coupled to an antenna for incident UWB pulse transmission (140), and an antenna for receiving the UWB pulses (150) reflected from at least one interface of the tire tread, the reception antenna (150) being coupled to a pulse signal receiver (180) which is itself coupled to the control unit (110).

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, by a first device, that a second device is within range for direct communications and that the second device is capable of performing transpositional modulation (TM) communications. Determining to use transpositional modulation to send data to the second device. Sending the data to the second device using a TM signal.

Abstract: A device, a circuit and a method are disclosed herein. The device includes a data receiving circuit and an oscillating signal generator. The data receiving circuit is configured to output a first output signal, a second output signal, and a phase error signal according to an oscillating signal and a modulated signal, in which the phase error signal indicates a phase difference between the oscillating signal and the modulated signal. The oscillating signal generator is configured to delay a phase of a first reference signal according to the phase error signal, to generate the oscillating signal.

Abstract: A signal detection method that allows characterization of a modulated signal to be efficiently determined. The method comprises the steps of receiving a data signal, processing the data signal to determine its value squaring the value of the signal; filtering the squared signal value to remove DC content; evaluating the resulting signal to determine if a single sinusoidal value remains; and determining that the presence of a single sinusoidal value as the resulting signal from the squaring and filtering steps indicates that the received data signal is a phase-shift key signal or conversely that the absence of such after a given number of cycle of squaring and filtering indicates a different modulation technique is present in the signal.

Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop.

Abstract: Embodiments of radio frequency (RF) front-end circuitry are disclosed where the RF front-end circuitry includes a tunable RF filter structure and a calibration circuit. The tunable RF filter structure includes (at least) a pair of weakly coupled resonators and defines a transfer function with a passband. The calibration circuit is configured to shape the passband so that the passband defines a center frequency. Additionally, the calibration circuit is configured to detect a phase difference at the target center frequency between the pair of weakly coupled resonators and adjust the phase difference of the pair of weakly coupled resonators at the target center frequency so as to reduce a frequency displacement between the center frequency of the passband and the target center frequency. In this manner, the calibration circuit calibrates the tunable RF filter structure to correct for errors in the center frequency of the passband due to component manufacturing variations.

Abstract: A method for operating a transceiver includes generating, by the transceiver, a first signal that includes an estimate of an interference signal leaked from a transmit path to a receive path of the transceiver. Generating the first signal includes obtaining a baseband transmit signal that includes a baseband of a transmit signal transmitted via the transmit path. Generating the first signal also includes calculating a harmonic phase that includes a phase of a harmonic of the baseband transmit signal. Generating the first signal also includes estimating a phase shift in accordance with an envelope of the baseband transmit signal. Generating the first signal also includes determining a phase of the first signal in accordance with the estimated phase shift and the calculated harmonic phase such that interference of a receive signal received via the receive path is reduced according to the first signal.

Abstract: A computing system includes: an inter-device interface configured to communicate content; and a communication unit, coupled to the inter-device interface, configured to process the content based on a polar communication mechanism utilizing multiple processing dimensions for communicating the content, including: generating a node result with a first orthogonal mechanism, and processing the node result from the first orthogonal mechanism with a second orthogonal mechanism.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, by a first device, that a second device is within range for direct communications and that the second device is capable of performing transpositional modulation (TM) communications. Determining to use transpositional modulation to send data to the second device. Sending the data to the second device using a TM signal.

Abstract: Component signal values are derived from component signals and fed to at least one fixed equalizer which generates equalizer output signals. The signals are fed to phase error detectors generating phase error signals. The phase error signals are combined with further phase error signals derived by further error detectors receiving signal values from further equalizers and/or the component signal values directly from sample units.

Abstract: Methods, systems, and apparatus for detecting a center frequency of an input signal, the input signal including a carrier signal modulated with a modulation signal. Detecting a frequency of a second signal. Determining a difference signal between the center frequency of the input signal and the frequency of the second signal. Modifying the frequency of the second signal based on the difference signal to provide the carrier signal. And, outputting the carrier signal.

Abstract: A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks.

Abstract: A channel estimation apparatus includes a de-map circuit to map multiple preambles corresponding to multiple channels into real part (I) and imaginary part (Q) in QPSK coordinate. The costas channel estimation circuit receives the real part (I) and the imaginary part (Q) to operate corresponding to one of the BPSK structure and the QPSK structure to proceed calculation of (Q?I)*Sign (I+Q) or Q*Sign (I)?I*Sign (Q) for outputting an output value, wherein Sign(x) represents a sign circuit taking a sign of the x value. The loop filter circuit filters the output value under time domain. The smooth circuit receives the output of the loop filter circuit to perform smooth processing under frequency domain and then feeds back the same to the de-map circuit to continue channel estimation of a next loop, wherein the phases of the preambles are adjusted according to a direction of the output value approaching to zero.

Abstract: A phase-locked loop (PLL) is provided. The PLL comprises a clock adjuster configured to receive an initial clock signal having an initial frequency and a mode control signal. The clock adjuster is configured to modify the initial clock signal into a modified clock signal based on the mode control signal. The PLL is configured such that a loop bandwidth is equal to a specified bandwidth. When the modified clock signal is changed, a loop gain of a loop filter is adjusted such that the loop bandwidth is substantially equal to the specified bandwidth. When the modified clock signal is changed, an oscillator tuning word (OTW) signal is modified into a normalized OTW signal such that the loop bandwidth is substantially equal to the specified bandwidth.

Abstract: Apparatus and method for performing low cost analog clock recovery within a high bandwidth radio frequency communications system. An analog data source is passed through a squaring loop typically utilized for carrier recovery. A squaring loop consists of an analog mixer to multiply one component of the complex signal with itself, a bandpass filter and phase lock loop. The addition of nonlinear gain compression enables clock recovery for higher order modulation schemes to exploit the fundamental phase differences of the individual components that construct the received signal. The output of the phase lock loop drives the Analog-to-Digital converter. It is desired that this signal converges to the symbol clock's frequency and phase of the transmitter, thereby sampling the received baseband signal at the desired symbol levels.

Abstract: An apparatus includes a lock detect circuit configured to receive a phase detect signal and generate a lock signal according to the phase detect signal. The phase detect signal is a single bit signal having a first value or a second value. A method includes receiving a phase detect signal using a lock detect circuit, and generating a lock signal according to the phase detect signal. The phase detect signal is a single bit signal having a first value or a second value.

Abstract: A circuit and a method for removing a frequency offset and a communication apparatus including the circuit, capable of removing the frequency offset by tracking rapidly and accurately in a payload section. A sequence of sample levels is obtained by sampling a frequency level of the baseband signal at every 0.5 symbol interval. Absolute values of differences between the frequency levels adjacent to each other at every 1 symbol are calculated as first difference absolute values. Absolute values of differences between the frequency levels adjacent to each other at every 1 symbol are calculated as second difference absolute values. When the first difference absolute values are greater than a predetermined first determination value or the second difference absolute values are less than a predetermined second determination value, the average value calculated is set as the frequency offset.

Abstract: A receiver unit of a communication device can employ multiple correlators for decoding the access address of a packet received from another communication device. A dynamically determined primary frequency offset is applied to a phase difference signal that is determined from an RF signal that comprises the packet. For each of a plurality of access address decoding chains of the receiver unit, a secondary frequency offset associated with the access address decoding chain is applied to the phase difference signal, the phase difference signal is correlated with a predetermined access address of the communication device, and a resultant correlation output is compared against a correlation threshold. One of the access address decoding chains that generated the correlation output that is greater than the correlation threshold is selected and the packet is demodulated based, at least in part, on the phase difference signal corresponding to the selected access address decoding chain.

Abstract: A non-coherent detection apparatus includes, inter alia, a correlation unit, a frequency offset estimator, and a signal detector. The correlation unit obtains a differential phase signal by multiplying a complex conjugate value of a delay signal obtained by delaying a received signal by (N+1) chips by the received signal, sums-up resultant values obtained by multiplying each component of the differential phase signal by each component of a correlation sequence and outputs a correlation signal. The frequency offset estimator estimates a frequency offset based on a value obtained by accumulatively summing-up the correlation signals corresponding to preamble portions of the received signal. The signal detector detects an original signal from the received signal based on a size of a real-number part of a resultant value obtained by multiplying the frequency offset estimated by the frequency offset estimator by the correlation signal corresponding to a PHY payload portion of the received signal.

Abstract: A multilevel QAM demodulator includes a phase difference calculation unit calculating a phase difference signal based on the common phase signal and orthogonal signal after the phase rotation compensation, a phase shift amount calculation unit calculating a phase shift amount indicating a degree of a phase shift based on the common phase signal and orthogonal signal after the phase rotation compensation and phase noise compensation, and a correction unit correcting the phase difference signal based on the phase shift amount. A phase rotation is performed for the phase noise compensation based on the phase difference signal corrected by the correction unit.

Abstract: A modified Costas control loop (80) using switched analog low pass filters (R2, C1, C2) (R3, C3, C4) and rectangular to polar conversion (341) computes an angular phase reference error that is processed by a digital loop filter (342) to control a counter (441) and a state machine (442) that are used to control the gating of a controllably conductive circuit (84) interposed between an AC source (81) and a phase-controlled load (83) such as a dimmable lamp.

Abstract: A Global Positioning System (GPS) receiver integrated with a cellular phone system, comprising a single-balanced mixer, a poly phase filter, a channel select filter, an analog-to-digital converter, a reference frequency source, and a PLL unit is disclosed. The single-balanced mixer downconverts a GPS signal to generate an in-phase signal I and a quadrature signal Q. The poly phase filter generates an IF signal based on the in-phase signal I and the quadrature signal Q. The channel select filter receives the IF signal to filter unwanted channel signals. The analog-to-digital converter converts the signal from the channel select filter to a digital output signal. The reference frequency source provides a reference frequency to the analog-to-digital converter. The PLL unit receives the reference frequency for generating a clock signal to the single-balanced mixer for downconversion.

Abstract: A Phased Locked Loop (PLL) circuit includes: a clock signal generating unit for generating a first clock signal and a second clock signal of which the phase differs from the first clock signal by ?/2; a computing unit for computing first phase comparison results showing the results of comparing the phases of a signal wherein the first clock signal is subjected to phase shifting with the PSK modulation signal and second phase comparison results showing the results of comparing the phases of a signal wherein the second clock signal is subjected to phase shifting with the PSK modulation signal based on first and second parameters, the first clock signal, the second clock signal, and the PSK modulation signal; a control direction setting unit for virtually controlling the control angle; a parameter control unit; and a reading control unit for controlling the timing of reading data from the PSK modulation.

Abstract: A demodulation apparatus that can support various oscillation frequencies. The portable phone device includes a frequency synthesizer for generating a local-oscillation signal having a local oscillation frequency for converting the frequency of an input receiving signal into an intermediate frequency based on an oscillation signal generated by an TCXO and a synchronization hold portion provided with an NCO for generating a signal having a predetermined frequency based on the oscillation signal generated by TCXO. The frequency synthesizer makes the local oscillation frequency variable by setting the dividing ratio variable in accordance with an arbitrary oscillation frequency so that the intermediate frequency remains within a predetermined range regardless of the oscillation frequency, and an NCO makes the frequency of the signal variable by setting the dividing ration variable in accordance with the oscillation frequency.

Abstract: In a receiving section, a first mixer and a second mixer generate an I signal and a Q signal from a modulated reception signal, a local signal, and a local signal obtained by shifting a phase by 90 degrees. These I signal and Q signal are supplied to a digital signal processing section via a low path filter, a capacitor, a variable gain amplifier, and an ADC. In addition, the generated I signal and Q signal are directly supplied to the digital signal processing section. The digital signal processing section detects a sign of the I signal and a sign of the Q signal, the signals being directly input. In addition, the detected sign of the I signal is multiplied with the I signal input from the ADC, and then, the detected sign of the Q signal is multiplied with the Q signal input from the ADC, whereby the signs are commonly established in a positive state. Then, the I signal and the Q signal are added, and decoded into two-values.

Abstract: Methods and apparatuses employing symmetrical phase-shift keying (SPSK) for data modulation and demodulation. Each symbol in a transmission signal carries n-bit information and is transmitted with one of 2n+1 directions. Half directions among the 2n+1 directions are regarded as default directions and the remaining are regarded as complementary directions. Each default direction has a corresponding complementary direction with a phase difference of ? and representing the same n-bit information as the default direction. The phase difference between any two successive symbols after modulation is less than or equal to ?/2.

Abstract: A device and method for a symbol recovery in a digital television are disclosed. The device includes a symbol clock recovery device includes a remained phase error remover operating a digital baseband real/imaginary number component signals, and removing remained phase error, a timing error detector nonlinearly operating the real/imaginary number component signals having the remained phase error removed, and detecting symbol clock phase error information therefrom, and an oscillating part generating a symbol clock frequency compensated to at least two times from the detected symbol clock phase error information and outputting the compensated frequency.

Abstract: The exemplary demodulator of the present invention can eliminate effectively a phase fluctuation which cannot be fully eliminated by a carrier recovery loop (feedback loop), with subsequent feed-forward phase compensation loop which shares a phase detector of the carrier recovery loop. A carrier recovery loop receives a digital signal after a semi-synchronous detection, detects a phase shift of the digital signal to a predefined phase position in rectangular coordinate, and compensates for the phase of the received digital signal by a first compensation value on the basis of the detected phase shift to generate an output signal. A feed-forward phase compensation loop generates an average value of the phase shift, and compensates for the phase of the output signal by a second compensation value on the basis of the averaged phase shift value.

Abstract: Systems and methods for receiving non-coherent layered modulation signals are presented. An exemplary apparatus comprises a tuner for receiving a layered signal and producing a layered in-phase signal and a layered quadrature signal therefrom, an analog-to-digital converter for digitizing the layered in-phase signal and the layered quadrature signal, a processor for decoding the layered in-phase signal and the layered quadrature signal to produce a single layer in-phase signal and a single layer quadrature signal, a digital-to-analog encoder for converting the single layer in-phase signal and the single layer quadrature signal to a single layer in-phase analog signal and a single layer quadrature analog signal and a modulator for modulating the single layer in-phase analog signal and the single layer quadrature analog signal to produce a single layer signal.

Abstract: A multi-channel RF receiver uses an image rejection mixer (e.g. double quadrature mixer) in the IF down conversion stage for image side band rejection (whereby use of an IF narrow band filter for image rejection may be omitted if desired) and comprises a simplified frequency synthesizer which generates both a “wandering” IF oscillator frequency and an RF oscillator frequency for the up/down conversion stages (being, for down conversion, from RF to IF and from IF to base band. The IF used for a particular RF carrier (channel) is selected so as to be both an integer (N) sub-harmonic of that RF carrier and within the operating frequency band of the image rejection mixer. Advantageously, the synthesizer comprises only one loop and one VCO, wherein the IF oscillator signal is produced from the RF oscillator signal by means of a frequency divider.

Abstract: A quadrature demodulator includes a reception section which receives a signal transmitted by an RFID tag and containing a specific pattern and data following the specific pattern and multiplies the reception signal by a local signal to generate an I-signal, while multiplying the reception signal by the local signal shifted in phase by 90 degrees to generate a Q-signal, a first demodulating circuit which squares the I- and Q-signals and adding the resulting I- and Q-signals together to generate data on the basis of the addition result, a second demodulating circuit which detects the specific pattern in the I- and Q-signals to decode the data following one of the detected specific patterns, and a control section which selects one of the first and second demodulating circuits in accordance with a gain determined by the result of the addition between the values of the squared I- and Q-signals.

Abstract: A multi-channel RF receiver uses an image rejection mixer (e.g. double quadrature mixer) in the IF down conversion stage for image side band rejection (whereby use of an IF narrow band filter for image rejection may be omitted if desired) and comprises a simplified frequency synthesizer which generates both a “wandering” IF oscillator frequency and an RF oscillator frequency for the up/down conversion stages (being, for down conversion, from RF to IF and from IF to base band. The IF used for a particular RF carrier (channel) is selected so as to be both an integer (N) sub-harmonic of that RF carrier and within the operating frequency band of the image rejection mixer. Advantageously, the synthesizer comprises only one loop and one VCO, wherein the IF oscillator signal is produced from the RF oscillator signal by means of a frequency divider.

Abstract: A demodulation circuit for demodulating a received signal including carriers in quadrature modulated by digital signals and/or in which the processing is performed on two carriers in quadrature. The circuit includes a demodulator, an analog-to-digital converter, a correcting circuit, and a derotator. The correcting circuit provides signals to the derotator based on the derotator output signals and on signals provided by the analog-to-digital converter.

Abstract: An apparatus for continuous phase quadrature amplitude modulation and demodulation to continuously process phases and amplitudes at symbol change points in an M-ary quadrature amplitude modulation method.

Abstract: A data-directed frequency-acquisition loop capable of generating a frequency error having a magnitude and direction from a double sideband suppressed signal comprises a first multiplier that multiplies the signal by the output of a VCO. The output of the first multiplier is convolved by a second multiplier. The I output of the second multiplier passes through a first low-pass filter. The filtered I output and the Q output are then multiplied by a third multiplier. The output of the third multiplier is filtered through a second low-pass filter, amplified, and return to the VCO to complete the feedback loop.

Abstract: A technique that enables the sine and cosine branches within a PLL module to be obtained relatively easily and efficiently is described. According to the technique, the computation operations requiring a computation load, such as calculation of sine and cosine functions, are performed mostly once per a digital sampled signal, while relatively simple operations, such as multiplication and accumulations, are performed for every frame.