Abstract: Multi-phase electronic power converter (50) for outputting multi-phase alternating current, wherein for every phase the current converter (50) comprises a power output (52) controlled via at least two semiconductor switches (51) connected in a half-bridge circuit, wherein the electronic power converter (50) has a control device (53) which is configured for processing a target value signal of the control device (53) supplied as an input signal, each in the form of a bit stream (1, 2, 3, 30, 31, 32) of one or more bits for every phase, characterized in that the control device (53) is configured by means of space-vector modulation to generate actuation signals (P1, P2, P3) of the semiconductor switches (51) in relation to the bit streams (1, 2, 3, 30, 31, 32) supplied as an input signal.
Abstract: Systems and methods are presented for transmitting additional data over preexisting differential COFDM signals by changing the amplitude of the legacy data symbols. In exemplary embodiments of the present invention, additional data capacity can be achieved for a COFDM signal which is completely backwards compatible with existing legacy satellite broadcast communications systems. In exemplary embodiments of the present invention, additional information can be overlaid on a legacy COFDM signal by applying an amplitude offset to the legacy symbols. In exemplary embodiments of the present invention, special receiver processing can be implemented to extract this additional information, which can include performing channel equalization across frequency bins to isolate the amplitude modulated overlay signal.
September 21, 2016
Date of Patent:
August 28, 2018
Sirius XM Radio Inc.
Carl Scarpa, Edward Schell, Christopher Hugh Strolle
Abstract: A receiver receives, using a plurality of antennas, a multiplexed signal that includes (i) a first OFDM modulation signal with a subcarrier carrying a symbol including multiplex information and a subcarrier carrying a pilot symbol and a subcarrier carrying a data symbol and (ii) a second OFDM modulation signal with a subcarrier carrying a symbol including multiplex information and a subcarrier carrying the pilot symbol and a subcarrier carrying the data symbol. A decoder uses the symbol including multiplex information and decodes the data symbol.
Abstract: A video data transmitter apparatus generates and transmits a multi-value amplitude modulation signal by performing a multi-value amplitude modulation of a plurality of N bits per one symbol according to video data of a video signal or a color signal constituting the video signal, or a brightness signal and a color-difference signal. A data separator portion separates the video data into first to N-th pixel data, a difference calculator portion calculates (N?1) pieces of predetermined difference information based on the separated first to N-th pixel data, and a multi-value amplitude modulator portion performs a multi-value modulation so that predetermined N-bit data corresponds to a multi-value signal level closest to an intermediate level having an intermediate value between a maximum level and a minimum level of the multi-value signal level of the multi-value amplitude modulation signal.
Abstract: A method for digital amplitude control and digital phase control of a high-frequency signal is provided. A digital command signal specifies in complex form, including a real subcomponent and an imaginary subcomponent, an amplitude and a phase of the high-frequency signal that is to be controlled. A digital activation signal is output to a high-frequency unit for the purpose of generating the high-frequency signal. A digital signal deviation value is received in complex form including a real subcomponent and an imaginary subcomponent. The signal deviation value expresses a deviation of the high-frequency signal from the command signal with respect to the amplitude and the phase. The digital activation signal is determined from the command signal while taking into consideration the signal deviation value. The determination of the real subcomponent and the imaginary subcomponent takes place separately in each case.
Abstract: An optical transport system is configured to use a modulation scheme in which a phase rotation applied to a sequence of PSK or QAM constellation symbols encoding a codeword of an FEC code produces a modified sequence of PSK or QAM constellation symbols encoding a bit-word that is not a valid codeword of that FEC code. Based on this property of the modulation scheme, an optical receiver may be configured to relatively accurately recover the absolute phase of the optical carrier wave of the received modulated optical signal by applying maximum likelihood sequence estimation processing to each portion of the signal carrying a valid codeword of the FEC code. For example, for a modulation scheme employing a 2n-PSK constellation, the optical receiver may be able to recover the absolute phase of the optical carrier wave with an accuracy that is better than 360/2n degrees.
Abstract: A data transmission apparatus and a method of modifying a symbol constellation for use in the data transmission apparatus, wherein a processor receives a starting symbol constellation suitable for use in a frequency domain parallel modulation system and defined in a complex space. The starting symbol constellation does not necessarily comprise a symbol at a zero point in the complex space. The processor is configured to locate or move one of the symbols of the starting symbol constellation at the zero point of the complex space. The newly created symbol constellation may be stored in a storage medium, such as volatile or non-volatile storage, or immediately used for data transmission by mapping bits of data to the symbol constellation and by transmitting the mapped data to a receiver of a frequency domain parallel modulation system.
Abstract: An OFDM receiver apparatus receives an OFDM signal including a plurality of DBPSK signals transmitting identical information. An extraction unit extracts the plurality of DBPSK signals from the OFDM signal. A phase difference calculation unit calculates a phase difference between symbols of each of the plurality of extracted DBPSK signals. An accumulation unit accumulates the plurality of phase differences. A decision unit decides data transmitted by the DBPSK signals on the basis of an accumulation result.
Abstract: A system for implementing the soft decision of a 3-chip differential binary phase shift keying (DBPSK) optical signal using digital components. Pair-wise comparisons of three differentially detected signals are performed and analyzed by digital logic which determines the most likely sequence of data. In a first variant, pairs of adjacent data bits are detected simultaneously, whereas in a second variant, data bits are detected individually. The digital logic can be implemented using conventional logic gates.
Abstract: In a magnetic resonance imaging method magnetic resonance signal samples are received for a predetermined field of view by a receiving antenna having a spatial sensitivity profile. The sampling in the k space corresponds to the predetermined field of view in the geometrical space. Folded-over images having folded-over pixel values are reconstructed from the sampled magnetic resonance signals. Pixel contributions for spatial positions within the predetermined field of view are calculated from the folded-over pixel values and the spatial sensitivity profile of the receiver antenna. The magnetic resonance image is formed from the pixel contributions for spatial positions within the predetermined field of view. Thus, aliasing or fold-over artefacts caused by a field of view that is too small are avoided.
November 20, 2002
Date of Patent:
May 8, 2007
Koninklijke Philips Electronics N. V.
Romhild Martijn Hoogeveen, Frederik Visser, Lolkje Frederika Zoer, Willem Marten Prins, Johan Samuel Van Den Brink
Abstract: A demodulation circuit for demodulating a received signal including carriers in quadrature modulated by digital signals and/or in which the processing is performed on two carriers in quadrature. The circuit includes a demodulator, an analog-to-digital converter, a correcting circuit, and a derotator. The correcting circuit provides signals to the derotator based on the derotator output signals and on signals provided by the analog-to-digital converter.
Abstract: An automatic gain control circuit capable of accurately executing control irrespective of the conditions of control is to be provided. This automatic gain control circuit includes a multiplier, low pass filters, a comparator, first and second absolute value circuits, and a delay circuit. The multiplier multiplies a first quadrature signal Ich by a signal supplied from the low pass filters. The first absolute value circuit figures out the amplitude of the first quadrature signal Ich supplied from the multiplier, and the second absolute value circuit figures out the amplitude of the second quadrature signal Qch. The delay circuit delays the output signal from the second absolute value circuit by at least an equivalent of one symbol. The comparator compares, after the delay circuit delays the output signals, the amplitude of first quadrature signal and the amplitude of second quadrature signal.
Abstract: This invention relates to a broad band spread spectrum communications receiver with carrier recovery and tracking based on multiple phase shift keying (MPSK) techniques. The receiver comprises three subsystems: the synchronization system, the carrier tracking system and the data demodulation system. To demodulate the received signal, the receiver requires a carrier frequency that matches that of the transmitter as well as the chip and symbol clocks that are synchronized with those of the transmitter. In the disclosed system the carrier tracking subsystem continually tracks the carrier frequency of the received signal using a tracking scheme which is based on correlation techniques. The synchronization subsystem synchronizes the symbol clock and chip clock. These three subsystems interact with each other and result in an improved bit error rate (BER) performance.
Abstract: A magnetic resonance signal is acquired from a JHH-coupled 1H within an object. After application of a wideband first radio-frequency magnetic pulse, a first frequency-selective radiation pulse is applied to a specific nucleus 1H coupled to a desired nucleus 1H through a homonuclear spin-spin coupling (JHH-coupling), thus multiple-quantum coherences between the nuclei 1H being generated. A second radio-frequency magnetic pulse is then applied. A second frequency-selective radiation pulse is then applied to the specific nucleus 1H to generate a single-quantum coherence of the desired nucleus 1H. Thus, a magnetic resonance signal can be acquired from the desired nucleus 1H. The acquisition of the signal is robust, adjustment in the phases of the radio-frequency magnetic pulses is not required, and an acquired spectrum is avoided from being visually complicated.
Abstract: A demodulator demodulates a PSK communications signal using a synchronizer, a period window detector, and a logic device. The synchronizer provides a transition signal representing reference edges of the communication signal. The period window detector, coupled to the synchronizer, establishes a time interval based on the period of the transition signal. Finally, the logic device, having logic inputs coupled to the outputs of the period-window detector, yields a logic output signal. The demodulator preferably includes a carrier boundary detector for framing messages and minimizing noise detection in a manner that permits signal strength measurements over a wide dynamic range.
October 29, 1998
Date of Patent:
January 22, 2002
Lucnet Technologies Inc.
Robert E. Johnson, George P. Vella-Coleiro
Abstract: The invention discloses a novel equalization system for reducing the deleterious effects of crosstalk on signals received at a modem, with particular regard to QAM signals transmitted over copper twisted pairs. The equalization system employs the common combination of a linear equalizer followed by a decision-feedback equalizer (DFE). However, instead of aiming for perfect equalization of channel distortion, the overall frequency response of the channel plus the linear equalizer is skewed such that higher frequencies are attenuated relative to lower ones. More generally, the spectral regions where crosstalk is strongest are attenuated, which reduces the crosstalk noise present at the input to the DFE at the expense of introducing inter-symbol interference (ISI). Fortunately, most DFEs are capable of handling the added ISI, leading to data decisions that are relatively unaffected by crosstalk noise.
Abstract: A digital demodulator which demodulates information signals that have been phase-modulated using a method such as PSK (Phase Shift Keying). The adder 46 adds a compensation value held by the phase compensator 45 to phase difference data outputted from the comparator 43. The subtractor 47 subtracts phase difference data delayed by the delaying circuit 44 by one information symbol period from the sum of the phase difference data and the compensation value from the adder 46, thus performing delay detection. With this digital demodulator, an input signal can be received and demodulated even if its frequency is not an integral division of the frequency of a master clock signal, and an oscillator can be used even if its frequency is not an integral multiple of the frequency of an input signal to be demodulated.
Abstract: A digital demodulator includes: a local oscillator for generating a predetermined frequency signal; a mixer for mixing an intermediate frequency (IF) signal with a local oscillation frequency signal output by the local oscillator; an A/D converter for converting a signal output by the mixer into a digital signal; an I and Q signal generator for producing I and Q signals from an output of the A/D converter; and a compensation unit for compensating the signals I and Q for phase errors.
Abstract: A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal.
November 12, 1997
Date of Patent:
August 1, 2000
DPS Group, Inc.
Stephen T. Janesch, Alan F. Hendrickson, Paul G. Schnizlein
Abstract: A FPLL has an I, a Q and a third multiplier, with the I multiplier supplying demodulated signals to a limiter and the Q multiplier supplying signals to a loop filter. A VCO and phase shift circuit supply quadrature signals to the I and Q multipliers. The analog input signal is applied to the I multiplier and to the third multiplier. The third multiplier, which is located in an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents, is also supplied with the digital output of the limiter. The third multiplier supplies its output to the Q multiplier.
Abstract: A circuit for measuring a carrier-to-noise ratio or a bit error rate of demodulated I and Q digital signals obtained by demodulating an input carrier wave which is modulated and transmitted under a carrier modulation transmission system including a discriminating circuit for producing a discrimination signal each time the demodulated digital signal comes within predetermined windows set on a signal space of the I and Q signals, a counter for counting the discrimination signals during a predetermined time interval, and a calculating circuit for calculating a carrier-to-noise ratio or bit error rate in accordance with a count value with reference to a previously stored relationship between count values and carrier-to-noise ratios or bit error rates.
Abstract: A frequency sweep circuit including: a pull-in verification wave generator for generating a verification signal for pull-in verification; a sweep wave generator for generating a frequency sweep signal; a first adder for adding an output from the pull-in verification wave generator and an output from the sweep wave generator; a correlation determining unit for receiving a phase difference signal representing a phase difference between a received carrier wave and a recovered carrier wave, and an output from the first adder, determining presence/absence of a correlation between the phase difference signal and the output, and outputting a control signal for controlling the sweep wave generator; a second adder for adding the output from the first adder to the phase difference signal; a digital-to-analog converter for receiving an output from the second adder; a loop filter for receiving an output from the digital-to-analog converter; and a voltage-controlled oscillator for receiving an output from the loop filter
Abstract: A demodulator of the present invention comprises a clock signal generator for generating a clock signal having a frequency that is 4 times n times (n is an integer greater than zero) the carrier frequency of a received signal, an analog-to-digital (A/D) converter for converting the received signal into a digital signal, a complex signal generator clocked by the clock signal to generate a complex signal comprised of the received signal as a real part and a .pi./2 phase-shifted signal as an imaginary part, a phase rotator for generating quasi-coherent detected signals by multiplying the complex signal by specific values of the carrier frequency, and a decimation circuit clocked by a clock signal to generate the required I channel signal and Q channel signal by decimating the quasi-coherent detected signals so as to finally obtain improved accuracy for accomplishing quadrature detection and eliminate an amplitude deviation and a direct-current offset.
Abstract: A FPLL has first second and third multipliers with the first multiplier supplying demodulated signals to a limiter and the second multiplier supplying signals to the loop filter. A VCO and phase shift circuit supply quadrature signals to the first multiplier and to the third multiplier which is relocated to an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents. The limiter output is applied to the third multiplier. The third multiplier supplies its output to the second multiplier. An integrated circuit embodiment using an exclusive OR gate as the third multiplier is also shown.
Abstract: A modulator used in an IC card reader/writer includes a phase variation detector for detecting a varying point of the phase of a modulated signal, a signal processing circuit for modifying the modulated signal for a half period at the phase varying point to have a frequency and amplitude twice those of the modulated signal, a first Miller integrator for integrating the modified signal to produce a triangular wave signal, and a second Miller integrator for integrating the triangular wave signal to produce a sinusoidal wave signal having a continuous phase. A demodulator used in the reader/writer includes a sync control circuit which controls a carrier sync signal generation circuit thereby to control the phase of a carrier sync signal in response to the discrimination as to whether the carrier sync signal is in lead-phase or lag-phase relative to the signal modulated based on binary phase shift keying (BPSK).
Abstract: A costas loop includes a comparator, and a BPSK-modulated signal which is converted into a binary signal by the comparator is latched by a D-FF according to an oscillation signal from a VCO. An output of the D-FF becomes a demodulated signal. On the other hand, a phase-difference between the BPSK-modulated signal and the oscillation signal is detected by a phase-comparator, and the phase-difference is applied to the VCO via a loop filter. An oscillation frequency of the VCO is thus controlled according to a phase-comparison result.
Abstract: A phase modulated signal demodulation system which is not affected by noise and distortion of an input signal. The system includes a carrier reproduction PLL circuit for generating a reproduction reference clock having a frequency which is N times of a carrier frequency which is synchronized with an N-phase phase modulated input signal, and a clock generation circuit for dividing the reproduction reference clock by 1/N and for generating N clocks, each of which has a different phase offset by 360.degree./N. The system further includes a phase detector which detects a phase of the N-phase phase modulated signal by using the N clocks together with the input N-phase phase modulated signal; and an operating circuit which detects a data edge of the input signal and the reproduction reference clock.
Abstract: A carrier regeneration circuit achieves quick frequency synchronization without using a sweeper. An area judging device judges whether a baseband signal, quadrature-demodulated with a regenerated carrier output from a voltage-controlled oscillator, lies inside a designated area in a phase plane. If it is inside the designated area, an output of a phase comparator is selected, and if it has exited the area, the previous value is held. The designated area is set so that the direction of control indicated by the phase comparator, just before the baseband signal rotating in the phase plane exits the area, coincides with a direction that suppresses the rotation.
Abstract: A quadrature demodulator for demodulating an input signal which includes respective data signals modulating in-phase and quadrature carriers. The demodulator includes a voltage controlled oscillator responsive to a control signal for generating an oscillatory signal. A demodulator, coupled to receive the oscillatory signal from the voltage controlled oscillator and the input signal, provides the in-phase and quadrature components of the input signal. Phase comparison circuitry, responsive to the in-phase and quadrature components of the input signal generates a phase error signal. The phase error signal represents the difference, in phase and magnitude, between a vector defined by the in-phase and quadrature components of the input signal and reference vectors. Filter circuitry, responsive to the phase error signal, generates a control signal for the voltage controlled oscillator.
Abstract: AFC circuit for QPSK demodulator including, a circuit for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator, digital converter for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal, frequency error detecter for detecting a frequency error between the quadrature related digital signals using a symbol timing sample value and a symbol intermediate timing sample value in the converted digital signals, first validity determinator for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal, second validity determinator for deetermining whether the frequency error signal is v
Abstract: In a demodulator, a delay detection means receives a .pi./4-shift QPSK signal and performs delay detection of a signal at an interval of symbols. An averaging circuit respectively averages two channel quadrature signal components of a signal. A preamble detection means detects a preamble having a specific pattern in which a phase shift of .pi./4 of the phase of a received symbol from the immediately preceding symbol and a phase shift of -3.pi./4 of a phase of a next symbol from the immediately preceding symbol are alternately repeated on a phase plane of the two channel quadrature signal components. A phase angle calculating means calculates the phase angle of an output signal from the averaging circuit. A frequency offset estimating circuit calculates a carrier frequency offset. A voltage-controlled oscillator has an output oscillation frequency variably controlled by an output signal from the frequency offset estimating circuit.
Abstract: A demodulating apparatus, which includes an up/down counter which counts up and down in accordance with a phase detection signal from a phase detector, an addition/subtraction unit which adds and subtracts the value (.DELTA.F1, .DELTA.F2) of the synchronization pull-in range to the count output, a counter stoppage unit which monitors a recovered carrier synchronization detection signal INIT and freezes the count output of the up/down counter immediately when detecting a disconnection of the input signal, and a synchronization pull-in range setting unit which expands the synchronization pull-in range at the same time as this to make it .DELTA.F2. The time required until establishment of synchronization with the input signal next to be received after the disconnection of an input signal is shortened.
Abstract: An AFC method is used in a demodulator, which employs a 2.sup.n -phase phase shift keying modulation system, where n is an integer greater than or equal to two, to correct an error between a received carrier frequency and a local frequency. The AFC method includes the steps of (a) subjecting an intermediate frequency signal of a signal received by the demodulator to a quadrature wave detection to obtain I-axis and Q-axis signals, (b) converting amplitude information of the I-axis and Q-axis signals into phase information which includes frequency information, and (c) correcting the local frequency based on the frequency information included in the phase information.
January 28, 1993
Date of Patent:
December 13, 1994
Hideto Furukawa, Koji Matsuyama, Tomonori Sato
Abstract: A BPSK demodulator having a compound phase locked loop, such as a Costas loop, is disclosed. An in-phase component, signal SI from a Costas loop demodulating section 10 is converted by a symmetrical binary-valued signal forming converting circuit 21 into binary-valued signals, while a quadrature signal component SQ from the demodulating section 10 is also converted by a non-symmetrical binary-valued signal forming converting circuit 22 into binary-valued signals. The outputs of the circuits 21, 22 are supplied to a flip-flop 23 as its data input and its clock input, respectively. An output of flip-flop 23 is integrated by an integrating circuit 25. A CPU 28 decides whether or not an integrated value from integrating circuit 25 exceeds a predetermined threshold value TH to decide whether or not the Costas loop demodulating section 10 is in the locked state. In this manner, the locked state can be detected by a simplified constitution, while a pseudo-locked state may also be detected.
Abstract: A circuit for regenerating a carrier, through coherent detection and demodulation of a quadrature modulated wave, is controlled by an improved AFC control to prevent possible false pull-in. The carrier regeneration circuit includes detector 1, a first multi-level code discriminator 2, a phase deviation detection circuit 3 and a voltage control oscillator 5.
Abstract: A phase error processor interfaces a proportionate phase detector to a digital loop filter in a high frequency phase-locked loop (PLL). The PLL receives a high frequency stream of NRZI encoded data, which contains a variable density of data signal transitions. A phase detector in the PLL generates proportionate phase error information in the form of a phase error pulse signal PD1 and a reference pulse signal PD2 for each data transition in the incoming data s The phase error processor, using a "decimation" technique, integrates the proportionate phase error information from just one pair of adjacent positive and negative data transitions during each period of N clock cycles if the number of input data transitions which occur during that time period exceeds the expected minimum, otherwise the phase error processor passes no phase error information. The selection of window width is based on the coding scheme of the incoming data stream.
Abstract: A digital audio communication system includes a digital modulation and demodulation scheme which efficiently uses the bandwidth and channel spacing of a cable television system. A 30 channel digital bit stream is demultiplexed into six groups of five channels. Each group of channels thereafter modulates a carrier by a quadrature partial response (QPR) process. The QPR signal, an amplitude modulated, double sideband, carrier suppressed (AM DSBSC) signal, is then transmitted over the cable system to a multiplicity of subscribers, each of which has a QPR demodulator. The demodulators are of the decision feedback type having a modified Costas loop carrier recovery circuit. The grouping of an odd number (five) of digital audio channels per QPR modulator minimizes error propagation due to the correlative QPR demodulation process. The decision feedback decoding is implemented in simple current nodes where a bilevel output from the decoded data is subtracted from a tertiary level output of a mixer.
Abstract: The present invention is directed to a differential phase-shift keying (PSK) signal demodulator in which an error rate provided when a signal modulated according to a .pi./4-shift DQPSK modulation system is demodulated can be improved. The differential PSK signal demodulator of the present invention includes means for phase-shifting a phase of a detection reference axis by a predetermined angle each in the counter-clockwise direction in synchronism with a timing at which a symbol to be detected is supplied, wherein the modulated signal is synchronizing-detected such that a rotation angle of the symbol and an angle of a detection reference axis are inhibited from becoming equal to each other, thereby a zero level being prevented from being output as a demodulated output.
Abstract: A data referenced demodulator is provided for recovering differentially encoded multiphase modulated digital data such as QPSK modulated audio data. An analog carrier containing the differentially encoded QPSK data is converted to a digital waveform at an intermediate frequency that is a multiple of the QPSK bit frequency. The digital waveform is delayed in a shift register that samples the waveform at a clock rate which is a multiple of the intermediate frequency. Different stages of the shift register output the digital waveform one bit time earlier plus 45.degree. and one bit time earlier minus 45.degree.. These outputs of the shift register are multipled with the digital waveform using exclusive OR gates to provide differential QPSK detection. The shift register sampling clock is phase locked to a system master clock, which in turn is locked to the received data. In an illustrated embodiment, the sampling clock is 24 times the intermediate frequency, providing 15.degree. phase resolution.
Abstract: The invention relates to a method and an arrangement for controlling the frequency of a radio-receiver which receives signal-sequences which have been subjected to interference and which include a synchronizing-sequence and a data-sequence. A signal-sequence is converted into signal-points intended for analysis. A Viterbi-analyzer is adapted to the prevailing interferences with the aid of the synchronizing-sequence. The data-sequence is Viterbi-analyzed through a large number of calculating stages to determine the bit-sequence of the data-sequence. A bit-sequence is extracted during the Viterbi-analysis, with a time-delay, subsequent to effecting a few calculating stages, and a corresponding extracted signal-point is calculated. The analysis-intended signal-point corresponding to the extracted signal-point is divided, time-delayed, and phase-compared with the extracted signal-point.
Abstract: In a demodulator circuit for receiving a direct sequence spread spectrum signal having composite PN codes, there is provided a novel detecting and tracking circuit for faster acquisition of the component PN codes. The first component code of the received composite direct sequence spread spectrum code is noncoherently detected in a noncoherent detection branch and the subsequent component codes of the composite code are automatically detected in a coherent lock detection branch to provide faster acquisition than was heretofore possible. Further, while the noncoherent detection branch is acquiring the first component PN code, a novel coherent carrier tracking loop is acquiring and locking onto the direct sequence spread spectrum signal carrier.
Abstract: A carrier lock detector for a quadrature amplitude modulation system includes Exclusive-OR gating circuits for determining when detected signal points occur within first areas centered on signal point positions in a phase plane diagram or second areas between the signal point positions, and for producing corresponding output signals. An integrated difference between these output signals is produced by an integrator and compared with a threshold level to provide a carrier lock detection signal. The arrangement is such that the integrated difference is substantially zero when the carrier is unlocked, so that the threshold level can be set to a low value to enable reliable operation of the detector at low signal-to-noise ratios.
Abstract: A digital demodulator or receiver (22) having an interface (24) for receiving an input signal modulated with digital data, a multiplier (26) for multiplying the input signal with a local oscillator signal (LOa-LOd) to generate a product signal, and an integrator (38) for periodically integrating the product signal to generate a sequence of integrated signals, each having an amplitude indicative of a respective portion of the digital data, operates in a SEARCH mode to supply acquisition reference signals (1xi, 1xq, 2xi, 2xq) to the multipliers (36). The resulting integrated values (Ia-Id) are proportional to the sine and cosine of the pahse (.phi.) of the input signal. The polarities (Sa-Sd) of these integrated values (Ia-Id) are processed to estimate this phase (.phi.) and to generate a reset signal (RESYNC) for the receiver (22) at the appropriate time.
Abstract: A universal demodulator programmable for any digitally modulated carrier signal having a known constellation format which can be characterized by a unique constellation pattern of phase-amplitude states. The demodulator also generates phase and gain-error signals for locking onto the phase and amplitude of the digitally modulated carrier. The demodulator splits the received digitally modulated carrier signal into an inphase component, D.sub.x, and a quadrature-phase component, D.sub.y. Using a preprogrammed memory device keyed to the identified modulation format, each D.sub.x signal is mapped into one of a plurality of one-dimensional zones each having R.sub.x center values. Using a second preprogrammed memory device also keyed to the identified modulation format, each D.sub.y signal is similarly mapped into a plurality of orthogonal one-dimensional zones having R.sub.y centers. Each pair of R.sub.x and R.sub.