Abstract: A single chip direct conversion transceiver that includes a substrate on which a mixer unit and a local oscillator are provided as a circuit, and a positive hole formed between the mixer unit and the local oscillator and filled with a conductive plug to block signal leakage. A shield ground surface is formed above the substrate and blocks signal leakage occurring when the signals received through the antenna are input into the mixer and signal leakage occurring when the reference signal is input into the mixer from the local oscillator. A first interconnection is formed above the shield ground surface and connects the mixer unit and the local oscillator. Dielectric layers are formed between the substrate and the shield ground surface and on the shield ground surface to cover the first interconnection.

Abstract: Systems and methods for providing baseband predistortion within a transmitter. In a simplified embodiment, the transmitter contains a main signal path that receives an input signal and generates a main signal in response thereto. A filter in the main signal path is used for removing unwanted signal components from the main signal. A power amplifier having non-linearity is also located within the transmitter. A digital predistortion module is used by the transmitter to digitally process the input signal to generate a predistortion signal that models an inverse of the non-linearity of the power amplifier. In addition, means, located between the filter and the power amplifier, for combining the predistortion signal with the main signal to generate a combined signal, and for providing the combined signal to the power amplifier, is located within the transmitter.

Abstract: Ideal nonlinear distortion compensation is realized by removing an imperfection of amplitude delay characteristic and an affection of inherent deviation that an amplifier has. A linear distortion compensation factor calculating part (18) estimates, based on quadrature demodulated signals (I?ch, Q?ch), the linear distortion characteristic occurring mainly due to imperfection of analog circuits, such as a quadrature modulator (13) and a high-power amplifier (14), and calculates and outputs a linear distortion compensation factor for compensating the linear distortion. A linear distortion compensating part (12) performs a pre-distortion (addition of a reverse characteristic of the linear distortion characteristic) by multiplying the baseband signals (Ich, Qch) by the data of the linear distortion compensation factor.

Abstract: A demodulator has a resistor and a capacitor that may be subject to tolerances. For tolerance correction, the FM demodulator is preferably supplied with a reference frequency, which corresponds to the nominal mid-frequency of the demodulator, which is a function of the resistor and the capacitor. Any discrepancy between the actual mid-frequency of the demodulator and its nominal mid-frequency leads to the production of a voltage that differs from a nominal voltage at the output. A detector detects this error and adjusts the values of the resistor or capacitor until the error between the nominal voltage and the voltage is zero or is a minimum. The described principle can be used, for example, in integrated mobile radio receivers.

Abstract: A direct conversion receiver (DCR) with a pair of quadrature conversion paths. Each of the quadrature conversion paths receives an RF input signal and converts the RF input signal to a digital baseband signal. The quadrature conversion paths each include a mixer mixes the RF input signal with a carrier phase signal. Quadrature baseband signals from the mixer pass through an analog filter which provides a filtered baseband signal. An analog to digital converter (ADC) converts the quadrature baseband component to a digital baseband signal. A 5th order elliptical filter filters the quadrature baseband component. The 5th order elliptical filter may be before or after the ADC. A digital baseband component from the ADC and filtered by the 5th order elliptical filter passes to a phase equalizer which compensates for phase distortion from the analog filter. The quadrature digital baseband outputs from the quadrature conversion paths are passed to a baseband processor.

Abstract: An FM signal receiver for use in receiving a burst signals as in a Bluetooth system includes a BPF and a frequency-demodulation circuit, each having, for example, a phase shifter, which is constructed from similar or related circuitry so as to enable adjustment of the frequency characteristics of the BPF and frequency-demodulation circuit through an identical control signal. A short-circuit switch is disposed linking the input and output terminals of an amplifier. A control circuit opens the switch in a receiving operation and closes the switch in an adjusting operation. Thus, adjustment is carried out without using the amplifier. Therefore, an amplifier offset does not affect the frequency-to-voltage conversion by the frequency-demodulation circuit in the adjusting of the frequency-demodulation circuit and similar adjusting of the BPF. Thus, the BPF is prevented from being incorrectly adjusted due to the offset. The BPF characteristics are suitably adjusted.

Abstract: An FM demodulator has a differential output demodulator for receiving an FM signal and for outputting a positive differential signal and a negative differential signal of a demodulated signal of the FM signal, a DC offset detector electrically connected to the differential output demodulator for generating a DC offset signal according to peak signals of the positive differential signal and the negative differential signal, and a correction circuit electrically connected to the differential output demodulator and the DC offset detector to compensate for the demodulated signal according to the DC offset signal.

Abstract: An FM demodulator compensates for DC offset by detecting the positive peak value of the frequency demodulated signal (D1, C2, R1) and the negative peak value of the frequency demodulated signal (D2, C3, R2). The mean of the positive and negative peak values is determined (C1, R3, R4) to produce an estimation of a DC offset value. This estimated DC offset value is then used to compensate for DC offset in the frequency demodulated signal. This circuit has the advantage of enabling the DC offset to be calculated without requiring complex digital signalling processing, and without requiring the input signal to have a zero mean. A signal strength signal RSSI may be used to disconnect the DC offset compensation circuitry during periods when the input signal strength is weak.

Abstract: A digital FM demodulator converts a digital FM input signal to a demodulated signal, detects the amplitude of the digital FM input signal, generates a corresponding amplitude signal, and adjusts the amplitude of the demodulated signal according to the amplitude signal, thereby compensating for variations in the amplitude of the digital FM input signal and removing amplitude distortion from the demodulated signal. This reduces the performance requirements of, for example, a low-pass analog filter preceding the digital FM demodulator in an FM radio broadcast receiver, permitting the analog filter to be implemented in a semiconductor integrated circuit.

Abstract: A digital FM demodulator employs a baseband phase lock loop (BBPLL), which is particularly effective for long range reception, for combining and demodulating a pair of signals represented by the mathematical expression A(t)ej&thgr;(t) to result in an approximation of d&thgr;/dt. This approximation is then subjected to an inverse of the linear approximation of the frequency response of the BBPLL that produces a very accurate &thgr;. This is conveniently achieved with a IIR filter whose transfer function happens to be the same as the inverse of the linear approximation of the frequency response of the BBPLL. The derivative is then taken of &thgr; to produce a very accurate d&thgr;/dt, the desired result for the output of an FM demodulator. To aid operation of the BBPLL, the incoming digital intermediate frequency is upsampled by a combination of sample and hold and FIR filtering prior to being processed by the BBPLL.

Abstract: A circuit (100) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector (110) and a sigma-delta analog-to-digital converter (130). The FM ratio detector (110) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter (130), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic “1's” and logic “0's” that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal (132).

Abstract: A receiver architecture includes a selectivity filter (206) for selectively passing a wanted channel and rejecting unwanted channels. The selectivity filter has a filter BT of about one-half the BT of the transmitter filter. A discriminator (208) is coupled to the selectivity filter for converting received symbols from the frequency domain to the time domain symbols. A symbol recovery processor (210) is coupled to the discriminator for recovering the symbols through a two-state maximum likelihood sequence estimation (MLSE) technique in which templates are optimized with a BT substantially less than the BT of the transmitter filter.

Abstract: Disclosed are radio frequency (RF) interference cancellation techniques that effectively estimate RF interference to the data signals being received using a frequency domain model, and then remove the estimated RF interference from the received data signals. Improved techniques for digitally filtering multicarrier modulation samples to reduce sidelobe interference due to the RF interference are also disclosed.

Abstract: The present invention is a method and apparatus to detect an instantaneous frequency of an input signal. A sampler samples the input signal to generate a sampled signal. A metric generator is coupled to the sampler to generate a metric signal based on the sampled signal. The metric signal has a magnitude proportional to the instantaneous frequency of the input signal. In another embodiment, the apparatus comprises a feedback circuit and a decimator. The feedback circuit generates a sequence signal from the input signal. The sequence signal represents a change of the instantaneous frequency of the input signal. The decimator is coupled to the feedback circuit to decimate the sequence signal to generate a frequency signal. The frequency signal providing the instantaneous frequency of the input signal.

Abstract: Estimates of both the communication channel impulse response coefficients and a received signal carrier frequency offset are generated simultaneously without either estimation interfering with or hampering of the other estimation. This is realized in an embodiment of the invention by utilizing both received symbols known to the receiver during a training sequence and a received signal to generate simultaneously an estimate of the impulse response coefficients of the communication channel and an estimate of the received signal carrier frequency offset. In one embodiment of the invention a first estimator and a second estimator are employed to generate the communication channel impulse response coefficients and the received signal carrier frequency offset, respectively.

Abstract: An FM demodulator circuit with reduced sensitivity to noise and performance nearly identical to theoretical predictions. The FM demodulator is a time sampled detector for binary shift key (BFSK) modulated signals. Its inputs are an in-phase and a quadrature outputs of a receiver, which have been oversampled by a predetermined factor with respect to the data rate. The demodulator circuit differentiates the in-phase and the quadrature input signal by computing the difference between the current signal value and the signal value delayed by one clock period. The differentiated values of the in-phase and the quadrature signals may be changed based on the sign of the quadrature and the in-phase signals respectively to produce modified values of the differentiated in-phase and quadrature signals.

Abstract: A reference generator includes a memory that stores reference data which, when clocked out of the memory, produces an ATSC compliant VSB reference signal substantially free of sub-harmonics of the clock signal. A digital-to-analog converter converts the clocked out reference data to an analog signal. The analog signal may be at low IF. An up converter is arranged to upconvert the output of the digital-to-analog converter to an RF reference signal. The RF reference signal can be used, for example, to calibrate a VSB demodulator.

Abstract: A demodulator circuit for demodulating a frequency modulated input, which includes a detector (14) that is operable to produce a demodulated signal from an incoming frequency modulated signal. A tuning circuit (19) is connected to the detector and operable to vary the frequency response characteristics of the detector. An auxiliary detector (25, 26) is connected to receive a reference frequency signal and to provide an auxiliary tuning signal to the detector on the basis of detection of the reference frequency signal.

Abstract: A frequency demodulator of the present invention includes: an amplification section for receiving a frequency-modulated signal and amplifying the frequency-modulated signal based on a gain so as to produce a digital signal having a predetermined level and an inverted signal of the digital signal; a digital demodulation section for receiving the digital signal and frequency-demodulating the digital signal; an amplitude detection section for receiving the digital signal and the inverted signal of the digital signal, and detecting maximum amplitude values of the digital signal and the inverted signal for a predetermined period of time so as to produce an amplitude signal in proportion to the maximum values; and a gain controlling section for varying the gain based on the amplitude signal.

Abstract: There are a receiving unit for receiving a TDMA signal which is FSK (FM) modulated by a signal containing known information, and a demodulating unit 103 for demodulating received data. The demodulating unit 103 outputs a demodulated signal in a direct connection to a C-coupling. A C-coupling demodulation signal is inputted to a synchronization detecting unit 105, and a directly connected demodulation signal is inputted to an AFCBU 106. After a power supply is turned on, the C-coupling demodulation signal is inputted to the synchronization detecting unit 105. The demodulation signal whose synchronization state is being detected is inputted to the AFC unit 106 in a parallel condition and in a direct connection condition. After the synchronization signal is detected, a frequency offset correction is applied to thereby change a frequency offset of the frequency-converted signal by a carrier wave frequency converting section 10.

Abstract: A method and device for digitally demodulating a frequency modulated signal includes: calculating a phase of a digital complex baseband signal of a received frequency modulated signal, calculating an unwrapped phase of the calculated phase, detecting and eliminating 2.pi. phase jumps in the unwrapped phase to generate a corrected phase, and differentiating the corrected phase.

Abstract: A method for demodulating a radio frequency signal having a frequency, by oscillating a demodulator at a frequency different from the signal frequency, and measuring a DC offset value at this different frequency, the DC offset value being associated with interference. Then the demodulator is oscillated at the signal, thereby providing a demodulated signal. The DC offset value is subtracted from the demodulated signal in order to provide a demodulated signal with a substantially reduced DC component. The demodulated signal is then monitored for further DC offset components, and these further DC offset components are subtracted from the demodulated signal.

Abstract: An FM demodulation circuit includes a phase conversion circuit which converts a frequency variation of an input signal into a phase variation and has a variable conversion characteristic, and a control current source circuit which outputs, when the level of the input signal drops lower than a predetermined level, control current to vary the conversion characteristic of the phase conversion circuit so that the demodulation sensitivity may be raised.

Abstract: Disclosed are radio frequency (RF) interference cancellation techniques that effectively estimate RF interference to the data signals being received using a frequency domain model, and then remove the estimated RF interference from the received data signals. Improved techniques for digitally filtering multicarrier modulation samples to reduce sidelobe interference due to the RF interference are also disclosed.

Abstract: Known is a zero intermediate frequency receiver or zero-IF receiver in which DC-offset correction is done in the I- and Q-paths, after mixing down of the received RF-signal or of an IF-signal. Such a DC-offset correction is not sufficient for high gain I- and Q-paths, particularly not in pagers for receiving long messages. Furthermore, no optimal power saving is achieved if such a receiver alternately operates in receive mode and sleep mode. A zero intermediate frequency receiver is proposed in which DC-offset correction is distributed over the high gain I- and Q-path. Preferably, blocking means are provided between DC-offset correction circuits and low pass filters in the I- and Q-path to prevent that an output signal of an upstream DC-offset correction circuit in the path excites a downstream low pass filter in the path during DC-offset correction. Herewith, considerable power savings are achieved.

Abstract: This invention relates to telecommunications systems. The present invention provides a system and method operable to the cancel interference from digital subscriber line systems. A data signal demodulator having first and second inputs arranged to receive differential data signals and local field RFI signals respectively, wherein a digital adaptive notch filter is formed by DSP means which locates an interferer in the differential signal by adapting its bandwidth and center frequency by adaptation means and wherein the center frequency and bandwidth of the notch filter are used to generate a bandpass filter centered on the interferer and of approximate bandwidth to the interferer; whose output, after processing forms a feedback signal which is sampled, processed, weighted and then combined with the local field RFI input signal of the demodulator, which combined signal is summed with the differential input signal to thereby cancel interference coupled onto the first input.

Abstract: Carriers (51) in a cable telephony system (10) are prioritized (70) according to their usability. A local access manager (LAM) (27) creates a frequency list that ranks the carriers (51) based upon their frequency. When a cable fixed access unit (CFAU) (44) requests a traffic channel, the LAM (27) selects a traffic channel based on the channel's carrier usability. The LAM (27) also selects an alternative channel based on both the channel's carrier usability and the based on the number of carriers between the traffic channel and the alternate channel in the frequency list. When either the LAM (27) or the CFAU (44) determines the traffic channel is unacceptable during a call they transmit a "Switching to Alternate Channel" message. The CFAU (44) retunes to the alternate channel and transmits a "Re-Connect" request. The LAM (27) then transmits a new alternate channel and the call continues.

Abstract: A frequency synthesizer (100) is utilized for producing an output signal (124) which is phase locked to a reference signal (110) operating at a reference frequency. The frequency synthesizer (100) comprises a main phase lock loop (PLL) (102), and a tracker PLL (128). The main PLL (102) includes a phase detector (112), two frequency dividers (108, 126), a loop filter (116), a notch filter (118), and a controlled oscillator (122). The tracker PLL (128) phase locks to the reference signal (110), and biases the notch filter (118) in order to maintain an accurate lock on the notch frequency which is proportional to the reference frequency. All circuits are integrated in the same monolithic device in order to track parametric tolerances such as transconductances of the operational transconductance devices included in the tracker PLL (128) and the notch filter (118).

Abstract: Co-channel interference of a frequency modulated signal represented by complex signal samples is reduced by amplitude limiting each sample and non-linearly filtering the limited samples. The non-linear filter low pass filters the limited samples, multiplies the filtered samples by their complex conjugates, and high pass filters the products to produce resultant signal samples. It also squares the filtered samples, low pass filters the squared samples, multiplies the filtered squared signals by the complex conjugates of the filtered samples, combines the result with said resultant signal samples and the filtered samples, and low pass filters the combined signal to produce samples having reduced co-channel interference. The limiter and non-linear filter can be constituted by a digital signal processor.

Abstract: The invention provides a quadrature demodulator which removes unnecessary higher harmonic signals included in a demodulation output without giving rise to increase in number of externally connected parts and increase in current consumption. The quadrature demodulator includes a first double differential circuit to which a modulated signal and a first local signal are inputted, a first emitter follower circuit for effecting impedance conversion, a second double differential circuit to which the modulated signal and a second local signal having a phase shifted by 90-degrees from the first local signal are inputted, and a second emitter follower circuit connected to a pair of outputs of the second double differential circuit for effecting impedance conversion.

Abstract: A method in which correctable I/Q imbalance errors in a complex receiver can be detected and compensated for digitally without the use of special calibration signals. Differential D.C. offset errors are compensated by averaging the incoming I.sub.d and Q.sub.d digital signals and subtracting from them an expected value of differential D.C. offset, for example, computed from the long term average of the I and Q signals to create I' and Q' signals. Differential gain imbalance errors are corrected by calculating a root means square average of the I' and Q' digital signals and applies to them compensation coefficients K.sub.x and K.sub.y determined from either the RMS average or from a Stochastic Gradient Algorithm. The DSP compensates for the quadrature phase errors by calculating a compensation matrix which is independent of the frequency of the carrier and applies the compensation matrix to the I' and Q' digital signals.

Abstract: A radio transceiver including a counter for outputting a DC compensation signal, an amplifier for receiving a input signal having a DC component and for receiving the DC compensation signal and forming a signal difference between the input signal and the DC compensation signal and a comparator for comparing the signal difference and a reference signal. The counter increases and decreases the DC compensation signal based on the output of the comparator such that the incrementation or decrementation of the counter is based on the DC component of the signal difference.

Abstract: An FM demodulator formed on a semiconductor chip generates a demodulated audio-frequency signal from an audio intermediate frequency signal through a phase locked loop constituted by a multiplier, a low-pass filter and a voltage-controlled oscillator. A variation of amplitude of the demodulated audio-frequency signal due to a temperature variation is compensated by a temperature compensating amplifier and a de-emphasis filter through first and second reference currents flowing out therefrom through an internal resistor fabricated on the same semiconductor chip and an external resistor.

Abstract: An inversion prevention device to prevent inversion and provide the best S/N ratio detects a point where the zero crossing is missing from a quantized FM signal. An output is provided by switching between the digital FM signal and the output signal of at least one sideband suppression filter based on a result of the inversion detection. Alternatively, an output is provided by switching between the digital FM signal and a specified value based on a result of the inversion detection. As a further alternative, an output is provided by switching between the digital FM signal, the output signal of a low-sideband emphasis filter and the output signal of a sideband suppression filter based on a result of the inversion detection.

Abstract: An FM detecting circuit using phase locked loop (PLL) is disclosed. A reference voltage unit generates a reference voltage. A phase detector detects a phase difference between an FM signal and another frequency signal. A low-pass filter receives the output signal from the phase detector, and outputs a detected signal by passing only low frequency signals. A DC component detector receives the output signal from the low-pass filter, and detects a DC component. A voltage controlled amplifier receives the reference voltage and the voltage output from the DC component detector, and outputs a constant level voltage by controlling a gain based upon the difference between the two received voltages.

Abstract: A receiver having, arranged in this order, an input section, an FM demodulator, to which a frequency-modulated input signal is applied, and an LF section, which FM demodulator includes a pulse shaper and a low-pass filter, the pulse shaper comprising a series arrangement of at least a load and a capacitance, the base-emitter junction of a transistor being arranged across the capacitance, and further including a switching device for charging and discharging the capacitance. The pulse shaper generates a low-noise pulse in that charging of a capacitance is started upon an edge of the input signal. The capacitance voltage is measured by a single transistor and when the transistor is turned on, the charging current of the capacitance is diverted via the transistor, so that the capacitance voltage is limited. The capacitance is discharged upon a second edge, after which the cycle is repeated. The output signal of the pulse shaper is a signal which varies with the current through the capacitance.

Abstract: An AFC system and method of detecting and compensating frequency drift in the carrier frequency of a Gaussian filtered Minimum Shift Keying (GMSK) signal by demodulated frequency compensated samples of the received signal and calculating a frequency compensation angle based upon the demodulated frequency compensation samples. The compensation angle is fed back to the frequency compensator and error detector and used to calculate the error signal.

Abstract: Method and apparatus for improving an estimate of a message being carried by a frequency modulated dominant carrier in the presence of co-channel interference from a subdominant carrier. An envelope detector provides an envelope signal E(t). A frequency demodulator provides a demodulated frequency signal F(t). In one embodiment, a comparator compares the envelope signal to a threshold voltage V.sub.T. A switch is operated when the envelope signal is less than V.sub.T. The signal F applied to the switch is held by a holding circuit while the switch is open. Interpolation and lowpass filtering improve the quality of the output signal. In another embodiment of the invention, the frequency demodulated signal F is summed with an unfiltered signal to provide a first summed signal. The first summed signal is summed with an unfiltered signal to provide a second summed signal which is an estimate of the message on a co-channel subdominant carrier.

Abstract: A .pi./4 delay spread detection and compensation arrangement effectively detects distortion due to multipath delay spread in a digital channel and compensates for this distortion with minimum circuit complexity. An improvement in the bit error rate performance for a differential detector in the receiver is achieved through use of a detected direct current (DC) component, which is proportional to the amount of multipath delay spread on the digital channel. This DC component is used in the differential detector for compensating for this delay spread. In addition, the differential detector also provides a channel quality measure of the level of delay spread on the digital channel for use by the receiver in selecting either the differential detector or an equalizer for decoding of the data on the digital channel.

Abstract: A method and apparatus utilizing the techniques of frequency shifting and filtering for converting an input signal having a desired signal at intermediate frequency and an undesired DC offset to a baseband frequency signal in which the undesired DC offset is eliminated. The apparatus includes a first multiplier for multiplying the input signal by a signal having substantially the same intermediate frequency plus an offset frequency (.DELTA.f) to produce a first output signal wherein the desired signal is shifted in frequency to the offset frequency (.DELTA.f) and the undesired DC offset is unaffected. The apparatus also includes a second multiplier coupled to the first multiplier for multiplying the first output signal by a signal having substantially the same offset frequency (.DELTA.f) to produce a second output signal having the desired signal shifted to baseband frequency and the undesired DC offset shifted in frequency to the offset frequency .DELTA.f.

Abstract: Method and apparatus for cancelling in-band interference in real time. A cancellation circuit is provided where one demodulator circuit provides a demodulated output having interference voltage owing to interference between carrier signals, between a carrier signal and noise, or a combination of both. Cancellation of interference is particularly directed to narrowband applications. Because the interference is within the band of the desired signal, it cannot be filtered without materially harming the quality of the message. A separation circuit is provided for removing the interference voltage component from the message signal. Outputs are provided to a second demodulator for creating a phase-shifted near replica signal of the dominant carrier signal without an interference voltage component. The separation circuit includes an isolation circuit.

Abstract: In detection of a frequency error of a local frequency for quadrature demodulation of a received signal by sampling (S2) each burst of the received signal by a sampling signal at a sampling period into a predetermined number 2m of sampled vectors, zeroth to (2m-2)-th phase errors are calculated (S3), each phase error accompanying a phase difference which is between two adjacent ones of the sampled vectors and is constant during each burst. Zeroth to (m-1)-th averages are calculated (S4(1)) as regards m consecutive ones of the phase errors with each average calculated starting at a q-th phase error of the phase errors and with q varied between zero and (m-1), both inclusive. A mean value of these m averages is calculated (S4(2)) and is divided (S5) by a divisor comprising the sampling period. The frequency error is given by a quotient of this division. The received signal is derived by reception of a transmitted signal subjected to digital angle modulation, such as GMSK or MSK modulation.

Abstract: A frequency modulation signal demodulator receives an intermediate frequency signal to demodulate a FM signal. The frequency modulation signal demodulator includes a voltage-controlled oscillator having variable capacitance diodes. The voltage-controlled oscillator varies the oscillating frequency of a signal by controlling a voltage across the variable capacitance diodes using a DC voltage. Also included is a phase comparator which produces a phase difference by comparing the phase of the intermediate frequency signal to the phase of the signal from the voltage-controlled oscillator and provides a direct current voltage signal corresponding to the phase difference. Also included is a differential amplifier which has an adjustable reference voltage source. The differential amplifier amplifies the direct current voltage signal to produce a demodulated signal. The demodulated signal is negatively fed back to the voltage-controlled oscillator as the direct current signal.

Abstract: Digital FM demodulator and method in which zero-crossings of a frequency modulated input signal are detected, a binary pulse is provided for each of the zero-crossings, and the binary pulse stream is filtered digitally to provide enhanced resolution of the incremental phase (frequency) of the input signal over a period which is asynchronous with the input signal. In the disclosed embodiments, the digital filtering is done with comb decimation filters, with a higher order filter being employed where greater resolution is desired.

Abstract: An information reproduction apparatus for reproducing a frequency modulated signal, the information reproduction apparatus having a demodulation portion for demodulating the frequency modulated signal and a deemphasis portion for deemphasis the demodulated frequency modulated signal, comprises: a detection portion for detecting an inversion of levels of the demodulated frequency demodulated signal to produce an inversion detection signal, the inversion being such that the frequency demodulated signal is uncorresponding to the frequency modulated signal when the frequency modulated signal having an image of an edge portion; a compensation portion responsive to the inversion detection signal for compensate the demodulated frequency modulated signal, the compensated demodulated frequency modulated signal being supplied to the deemphasis portion.

Abstract: A TC controlled RF signal detecting circuitry (211) used in the output power control circuit of a TDMA RF signal power amplifier includes positive coefficient current source (303) producing current I+ having a positive TC, negative coefficient current source (305) producing current I- having a negative TC, and current mirror (301) for summing currents I+ and I- to produce substantially identical compensated mirror currents Im1 and Im2. Anti-clamping current mirror (309) mirrors current Im2 to produce compensated currents Ia1 and Ia2, which are applied to and bias a Schottky diode coupled in series to a resistor network in each leg of diode detector (311). Each leg of diode detector (311) has a positive TC, which is substantially offset by the negative TC of compensated currents Ia1 and Ia2.

Abstract: A system is described which achieves an increased rate of transmission by transmitting multiple symbols in one symbol time. The information in the overlapping symbols can be recovered if the symbol used for transmission is chosen so that a subset of the samples representing the symbol has an inverse. The construction of suitable symbols is illustrated. Effective operation of the system depends on equalizaton which will recover the the baseband signal shape. Methods of equalization are depicted which are suitable for use with this sytem including equalization realized by predistorting the signal at the transmitter so that it arrives at the receiver undistorted. The invention is applied to to baseband and passband systems and the application of predistortion equalization to the fading passband channel is described.

Abstract: A decoder circuit (21) and method for providing an amplitude compensated signal by removing the undesired effect of amplitude modulation on a phase modulated signal. The decoder method is provided by demodulating a received inphase receive signal component (10) and quadrature receive signal component (12) of the phase modulated signal and outputting an amplitude varying signal (15) to a feedforward automatic gain control circuit that outputs an amplitude compensated signal (38). The feedforward automatic gain control circuit comprises a detector circuit (16), an offset bias circuit (32), a differencer circuit (30) and a gain control circuit (28).The detector circuit (16) outputs a DC signal (17) representing an amplitude of the inphase receive signal (10) and the quadrature receive signal (12). The offset bias circuit (32) provides a constant current bias (29) to the DC signal (17) thus creating a control signal 31.

Abstract: In a digital frequency demodulator, data representing the input signal to be demodulated is prestored in a look-up table and signal processing is digitally performed to generate a read address required for reading out the data stored in the look-up table using a phase shift method of operation. Phase-shifting is performed by determining the slope of a frequency-modulated signal containing a signal which does not cross the zero axis. Thus, the precision of the frequency demodulation is enhanced, and the frequency demodulation data stored in the look-up table is minimized to reduce the size of a ROM used for the look-up table.

Abstract: A device for removing a frequency offset in modem reception signals includes a sampling part for sampling signals, a carrier phase control (CAPC) part to compute and correct a frequency offset value .theta..sub.1, an automatic equalizer, a determining circuit, and a frequency offset computing part disposed between the automatic equalizer and the determining circuit to separately compute the frequency offset value .theta..sub.2 from a vector signal sampled in the sampling part. The frequency offset value .theta..sub.2 is compared with the frequency offset value .theta..sub.1 computed by the carrier phase control part, and when the net error .DELTA..theta. exceeds a predetermined value, a renewing part forcibly substitutes the first frequency offset value .theta..sub.1 in the carrier phase control part with the second frequency offset value .theta..sub.2.