Abstract: A transformer includes a magnetic core, a first coil unit and a second coil unit. The first coil unit is disposed within the magnetic core and includes a laminated board having layers laminated therein and conductive patterns. Respective ones of the conductive patterns are disposed on the laminated layers. The second coil unit includes a conductive wire spaced apart from the conductive patterns of the laminated board by an insulating distance. The conductive wire includes a triple-insulated wire surrounded by three sheets of insulating paper to maintain the insulating distance from the conductive patterns.

Abstract: A communication device of the disclosure includes a phase synchronizer, a first modulator, and a detector. The phase synchronizer generates a second signal on a basis of a first signal received from a communication partner. The first modulator is able to modulate the first signal on a basis of the second signal. The detector detects that synchronization between the first signal and the second signal is lost.

Abstract: An ultra-low power back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8 GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the third harmonic of the local oscillator for power efficiency. The LP-65 nm CMOS receiver consumes 335 ?W with a sensitivity of ?72 dBm at a BER of 10?3 and data-rate of 31.25 kb/s. The radio uses a balun and a 250 kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the local oscillator and the frequency-locked loop circuits.

Abstract: A transmitter with compensating mechanism of pulling effect includes an output unit and a correction unit. The output unit mixes a first correction signal and a second correction signal according to an oscillating signal to generate a modulated signal, and to amplify the modulated signal to generate a first output signal. The correction unit analyzes the power of the first output signal to generate a first coefficient and a second coefficient, and generate the first correction signal and the second correction signal according to the first coefficient, the second coefficient, an in-phase data signal, and a quadrature data signal.

Abstract: Examples of passive diode-based transmitter detuning circuits and low-voltage active diode-based and receiver detuning circuits are provided.

Abstract: The present disclosure provides systems and related methods for reducing noise and interference in communications between an external device and implantable medical devices. The external device comprises an isolated switching power supply that includes a transformer separating a non-isolated side from an isolated side of the power supply. The transformer includes a primary winding on the non-isolated side, the primary winding extending between a primary winding upper end and a primary winding lower end, and a secondary winding on the isolated side, the secondary winding extending between a secondary winding upper end and a secondary winding lower end. The power supply further includes a high-frequency switch configured to selectively connect and disconnect the primary winding lower end to a ground, wherein the primary winding is electrically coupled to a supply voltage at an intermediate point between the primary winding upper end and the primary winding lower end.

Abstract: A BPSK demodulator circuit comprises: a sideband-separating and lower sideband signal-delaying unit which separates a modulated signal into a lower sideband and an upper sideband by a primary low pass filter and a primary high pass filter having a cut-off frequency as a carrier frequency, and which outputs an upper sideband analog signal and an analog signal delayed by ¼ of a cycle of the carrier frequency from a lower sideband analog signal; a data demodulating unit which demodulates digital data by means of latching, through a hysteresis circuit, an analog pulse signal appearing in accordance with the phase change part of a signal generated by the sum of the analog signals; and a data clock restoring unit which generates a data clock by using a data signal and a signal having the delayed lower sideband analog signal digitized through a comparator.

Abstract: A method for processing an audio signal (i(t)), comprises: receiving a first set (x(t)) of time-varying signals representing a first sound comprised in the audio signal (i(t)), the first set (x(t)) of time-varying signals comprising an amplitude modulation signal (a(t)), a carrier frequency signal (fc(t)), a pitch signal (f0(t)) and an FM index signal (h(t)); and modifying the first set (x(t)) of time-varying signals by modifying the amplitude of the FM index signal (h(t)), thereby providing a first modified set (x?(t)) of time-varying signals. The resulting first modified set (x?(t)) of time-varying signals may subsequently be modulated to provide an audio output signal.

Abstract: Methods, systems, and devices are described for an adaptive demodulator that supports multiple modes. An FM signal may be received at a demodulator and parameters corresponding to the FM signal may be identified. Connections between multiple modules within the demodulator may be configured, based at least in part on the parameters, to select one of multiple demodulation modes supported by the demodulator to demodulate the FM signal. The modes may include a phase differencing mode, a phase-locked loop (PLL) mode, a frequency-compressive feedback (FCF) mode, and/or a quadrature detector mode. The parameters may include one or both of a signal strength of the FM signal and a maximum frequency deviation of the FM signal. Based on the parameters, one or more signals may be generated to configure the connections within the demodulator. A switch from one mode to another may occur when one of the parameters breaches a threshold value.

Abstract: Circuit for processing an input signal based on at least one reference signal, comprising a phase locked loop demodulator configured to receive a speed control signal and said input signal and further configured to follow a frequency and/or a phase of said input signal at a speed, wherein said speed depends on said speed control signal; and a reference signal detector configured to determine said at least one reference signal and to set said speed by outputting said speed control signal to said phase locked loop demodulator, wherein, if said reference signal detector detects said at least one reference signal, said reference signal detector decreases said speed.

Abstract: A periodically resetting integration angle demodulation device and a method using the same is disclosed, which uses a waveform multiplier and a periodically resetting integrator to modulate a continuous-time angle modulation signal into a discrete-time signal. The waveform multiplier multiplies the continuous-time angle modulation signal by a square wave signal whose frequency is integer times a carrier frequency, and then transmits the continuous-time angle modulation signal to a periodically resetting integrated circuit. The periodically resetting integrated circuit performs integration during a carrier period to generate a discrete-time angle modulation output signal. The present invention can greatly reduce the difficulty for designing an optical sensing system in the front end without limiting a modulation depth. Besides, the present invention achieves a small volume, high speed, high sensitivity, high reliability, high performance and high condition-adapting properties.

Abstract: A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal.

Abstract: A modulator, a demodulator and a modulator-demodulator are provided. A modulator includes a first intermediate signal processing path adapted to route a first intermediate signal; a second intermediate signal processing path adapted to route a second intermediate signal; a first amplifier coupled into the first intermediate signal processing path; a second amplifier coupled into the second intermediate signal processing path; and a chopper circuit coupled into the first intermediate signal processing path; wherein the chopper circuit is adapted to process the first intermediate signal in dependence on first baseband data; wherein the first amplifier is adapted to amplify the first intermediate signal processed by the chopper circuit in dependence on second baseband data; and wherein the second amplifier is adapted to amplify the second intermediate signal in dependence on the second baseband data.

Abstract: In conventional radio frequency (RF) systems, transmitters will usually convert baseband signals to RF so as to be transmitted. As part of the conversion process, the transmitters will perform digital predistortion (DPD), which uses feedback from a power amplifier. However, there are usually mismatches between the in-phase (I) and quadrature (Q) paths within with feedback loop. Traditional IQ correction filters were ineffective at providing adequate compensation for these mismatches, but here a filter is provided that provides adequate out-of-band compensation by use of frequency selectivity.

Abstract: The radio transmitting apparatus includes a first initial phase value setting circuit that sets, in the first modulator, an initial value of the phase of the first modulated signal, which is a value at the start of the modulation according to the first modulation scheme. The radio transmitting apparatus includes a second initial phase value setting circuit that sets, in the second modulator, the phase stored in the phase storing circuit as an initial value of the phase of the second modulated signal, which is a value at the start of the modulation according to the second modulation scheme. The radio transmitting apparatus includes a signal gathering circuit that selects and outputs the first modulated signal output from the first modulator and then selects and outputs the second modulated signal output from the second modulator.

Abstract: A receiving system and a method of processing broadcast signals in the receiving system are disclosed. The receiving system includes a tuner, a known sequence detector, a carrier recovery unit, a baseband processor, and a channel equalizer. The tuner receives a broadcast signal of a passband including a data group. Herein, the data group comprises mobile service data, a plurality of known data sequences, and signaling data. The known sequence detector estimates an initial frequency offset and detects a position of each known data sequence based on the known data sequence having the first data pattern. The carrier recovery unit acquires an initial frequency synchronization using the initial frequency offset estimated by the known sequence detector and estimates a residual frequency offset based upon the known data sequences having the second data pattern so as to perform carrier recovery.

Abstract: In one embodiment, three substantially simultaneous phase waveforms may be converted into a first quadrature signal and a zero sequence signal. For each phase waveform, a power system digital frequency may be determined through analysis of the first quadrature signal (e.g., and at least one additional prior quadrature signal) while eliminating waveform phase angles from the analysis. Subsequently, demodulation of the first quadrature signal and zero sequence signal based on the power system digital frequency results in a positive sequence phasor, a negative sequence phasor, and a zero sequence phasor.

Abstract: Systems and methods for mitigating multipath signals in a receiver are provided. In this regard, a representative system, among others, includes a radio frequency (RF) front-end and at least one analog-to-digital converter (ADC). The RF front-end receives FM signals and down-converts the received frequency signals to intermediate frequency (IF) signals. The analog-to-digital converter (ADC) receives the intermediate frequency signals and digitizes multiple FM channels around a desired FM channel associated with the down-converted signals. The system further includes multiple sets of digital processing components that are configured to simultaneously receive and process the digitized multiple channels. The multiple sets of digital processing components include at least two parallel channel selection and demodulation paths in which the respective digitized multiple channels are processed therethrough.

Abstract: An apparatus for providing a data encoding scheme may include an encoder. The encoder may be configured to determine, for a digital input value comprising a particular number of bits, whether more than half of the bits of the digital input value have a high value. The encoder may be further configured to encode the digital input value by inverting each of the bits of the digital input value in response to a determination that more than half of the bits of the digital input value have the high value. Corresponding method and computer program product, and a decoder and decoding method are also provided.

Abstract: Phase of an output signal is based on comparison of an oscillating signal with an adjustable threshold. Here, adjustment of the threshold results in a corresponding adjustment of the phase of the output signal. For example, the adjustable threshold may comprise an adjustable bias signal for a transistor circuit whereby the oscillating signal is provided as an input to the transistor circuit and the output of the transistor circuit provides the output signal. In some aspects these phase adjustment techniques may be employed to provide one or more tunable multiphase clocks.

Abstract: A communication device includes: demodulating means for demodulating a transmission signal from another communication device that performs noncontact communication; calculating means for performing at least one of addition and subtraction of a predetermined voltage according to a logical value of a demodulated signal obtained by demodulation by the demodulating means; determining means for determining a communication system of the transmission signal transmitted by the other communication device by comparing a calculation result of the calculating means at predetermined timing after a lapse of a predetermined time from the start of communication with a threshold voltage; and transmitting means for transmitting predetermined data to the other communication device in the communication system determined by the determining means among plural communication systems that the device itself can support.

Abstract: In an apparatus and method, time-varying signals are processed and encoded via a frequency domain linear prediction (FDLP) scheme to arrive at an all-pole model. Residual signals resulted from the scheme are estimated and transformed into a time domain signal. Through the process of heterodyning, the time domain signal is frequency shifted toward the baseband level as a downshifted carrier signal. Quantized values of the all-pole model and the frequency transform of the downshifted carrier signal are packetized as encoded signals suitable for transmission or storage. To reconstruct the time-varying signals, the encoded signals are decoded. The decoding process is basically the reverse of the encoding process.

Abstract: Disclosed herein is a demodulator, including: a frequency synchronization section adapted to synchronize a frequency of a local oscillation signal to be produced on the demodulator side with a local oscillation frequency of a modulation signal transmitting from a modulator side; a demodulation signal production section adapted to produce a demodulation signal based on the local oscillation signal synchronized by the frequency synchronization section and the modulation signal transmitted from the modulator; and a direct current correction section adapted to detect a direct current voltage of the demodulation signal from the demodulation signal produced by the demodulation signal production section and correct the direct current voltage of the demodulation signal so that the direct current voltage becomes equal to a reference voltage set in advance.

Abstract: A method and apparatus for enabling the operative association of electronic devices that each employ spread spectrum EMI noise reduction. The method includes the detection of frequency modulation and the generation of a modulation detection signal that conveys the modulation extent and type. The modulation detection signal is then used to accommodate the modulation technique and make it compatible with the receiving electronic device. The apparatus of the invention includes an FM modulator that creates an FM signal from an input signal, an FM detector that detects the FM content of the incoming signal and represent this information by means of either voltage or current signals, and a circuit to process this FM information and perform functions such as modification of the FM content and generating a new signal with this new content, complete removal of the content, and “no-action,” whereby the signal is passed on with no alteration to the content.

Abstract: An alternating current motor control system constituted of: a control unit; a cycloconverter functionality; a phase control functionality; and a semiconductor switching unit comprising a plurality of electronically controlled semiconductor switches each associated with a particular winding of a target alternating current motor and each independently responsive to the control unit. In one embodiment the semiconductor switching unit is arranged to connect the windings of the target alternating current motor to a three phase power input in one of a star and a delta configuration responsive to the control unit.

Abstract: The present invention relates to a digital receiver for FM signals, in particular to a new demodulator structure and demodulating method, by which according to a first aspect of the invention the usual complex de-rotation process is reduced to a simple addition/subtraction. According to a second aspect of the invention, the requirements for the sampling frequency necessary for processing the demodulator signals are reduced substantially.

Abstract: A receiver includes a band-pass filter that limits a passband of an IF (Intermediate Frequency) signal, an FSK detector that detects the IF signal passing through the band-pass filter to generate a detection signal, and a control block that controls a modulation sensitivity of the FSK detector and a pass bandwidth of the band-pass filter, in which the control block controls the modulation sensitivity of the FSK detector according to the pass bandwidth of the band-pass filter.

Abstract: Embodiments of the invention are concerned with correction of quadrature errors associated with digital communications systems, and in particular in a wireless transmit chain in which an up-converter and a down-converter both have a direct conversion architecture. One embodiment comprises a correction network for correcting a difference between a transmission characteristic of an in-phase signal path and a transmission characteristic of a quadrature signal path, said quadrature signal path being for the transmission of in-phase and quadrature parts of a signal and the signal comprising frequency components within a base band, wherein the correction network comprises an in-phase input port, a quadrature input port, an in-phase output port and a quadrature output port, wherein each input port is connected to each output port by a digital filter network, the digital filter network comprising a set of filter tap coefficients and configuration means for configuring values of said set of filter tap coefficients.

Abstract: A differential input envelope detector receives an unamplified Near Field Communication (NFC) input signal from an NFC antenna and downconverts an NFC intelligence signal to baseband. In one example, the NFC input signal includes the NFC intelligence signal modulated onto a carrier. The differential input envelope detector downconverts and outputs the downconverted NFC intelligence signal onto an output node in such a way that the fundamental and odd harmonics of the carrier are canceled on the output node. There is substantially no signal of the frequency of the carrier present on the output node and this facilitates filtering of the downconverted NFC intelligence signal from interference and data recovery. An NFC data recovery circuit receives the downconverted NFC intelligence signal from the envelope detector output node. The NFC data recovery circuit can be a low power digital circuit involving an ultra-low power ADC and subsequent low power digital processing circuitry.

Abstract: Quadrature signal demodulator circuitry for demodulating multiple related input signals into respective pairs of quadrature signals for selective combining to provide a composite pair of quadrature signals with a maximized signal-to-noise ratio (SNR).

Abstract: A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a positive integer greater than one. The wireless communication device includes an RF front end, a baseband processor, and an equalizer module. The RF front end is operable to receive the plurality of received RF bursts and to convert the RF bursts to corresponding baseband signals. The baseband processor is operable to receive the baseband signals, to pre-equalization process the baseband signals to produce processed baseband signals, and to post-equalization process soft decisions. The equalizer is operable to equalize the processed baseband signals to produce the soft decisions. These RF bursts may be contained in adjacent slots or, in non-adjacent slots, or in a combination of adjacent slots and non-adjacent slots.

Abstract: Frequency and phase of an output signal is adjusted to track an input signal. A control signal is adjusted to control a frequency of an oscillating signal from which the output signal is derived. In some aspects the frequency of the oscillating signal is adjusted by reconfiguration of reactive circuits coupled to an oscillator circuit. Phase of the output signal may be adjusted based on comparison of the oscillating signal with an adjustable threshold. For example, the adjustable threshold may comprise an adjustable bias signal for a transistor circuit whereby the oscillating signal is provided as an input to the transistor circuit and the output of the transistor circuit provides the output signal.

Abstract: Provided are modulation and demodulation methods and apparatuses using a frequency selective baseband. The frequency modulation method includes: generating a plurality of subgroups by dividing 2N (N is a real number) spread codes used for frequency spreading into 2M (M<N, M is a real number) spread codes; selecting P(P is a real number) subgroups among the generated subgroups; acquiring P spread codes by inputting M data bits to each of the p subgroups so as for 1 spread code to be selected among the 2M spread codes of each subgroup; and selecting dominant value among the acquired P spread codes to generate transmitting data including the dominant value. Accordingly, it is possible to increase a processing gain of the entire system, to increase a transmission data rate, and to reduce power consumption of the system.

Abstract: In general, this disclosure describes techniques for demodulating wireless signals. In particular, the techniques of this disclosure dynamically select between two or more demodulators based on channel quality information measured over a plurality of measurement periods. For example, a wireless communication device (WCD) may switch from a first demodulator to a second demodulator when the channel quality information associated with the demodulators indicates a better channel quality for the second demodulator than the first demodulator for a consecutive number of measurement periods. As another example, the WCD may compute, for each measurement period, the difference between the channel quality information associated with each of the demodulators, sum the differences, and switch demodulators when the total accumulation of the differences exceeds a threshold.

Abstract: A method for demapping dual carrier modulated COFDM signals comprises normalizing an estimated channel state information signal to obtain a normalized channel state information signal, determining a Y-domain weighting factor from the normalized channel state information signal, determining an X-domain weighting factor from the normalized channel state information signal, performing equalization on a received data OFDM signal to obtain an equalized data signal, weighting an equalized data signal using the Y-domain weighting factor and the X-domain weighting factor to generate a weighted input signal of a demapper and performing linear demapping of the weighted input signal in the demapper. There is also disclosed an apparatus for demapping dual carrier modulated COFDM signals and a receiver comprising such an apparatus.

Abstract: Provided are a frequency modulation/demodulation apparatus using a frequency selective baseband and a transmitting/receiving apparatus using the same. In a frequency selective baseband transmission technique or an FS-CDMA technique, a transmission rate is controlled according to communication channel environment, spread code groups are repeatedly selected in a receiving side so as to obtain a frequency diversity gain. Accordingly, it is possible to reduce interference between users. In addition, even in a case where strong interference induced from electronic exists, it is possible to implement low-power, stable human-body communication and to ensure a communication quality.

Abstract: Disclosed herein is a demodulator, including: a frequency synchronization section adapted to synchronize a frequency of a local oscillation signal to be produced on the demodulator side with a local oscillation frequency of a modulation signal transmitting from a modulator side; a demodulation signal production section adapted to produce a demodulation signal based on the local oscillation signal synchronized by the frequency synchronization section and the modulation signal transmitted from the modulator; and a direct current correction section adapted to detect a direct current voltage of the demodulation signal from the demodulation signal produced by the demodulation signal production section and correct the direct current voltage of the demodulation signal so that the direct current voltage becomes equal to a reference voltage set in advance.

Abstract: The present invention relates to an FM demodulator incorporating a delay-line quadrature detector without the use of a limiter amplifier. An Amplitude Locked Loop circuit provides a carrier signal with no amplitude variation prior to performing a conversion from frequency modulation to phase modulation. A delay-line performs this conversion using a standard IF ceramic filter with a precise delay of 90 degrees to the un-modulated carrier frequency. The original non-delayed carrier is multiplied with the delayed carrier using a four quadrant linear multiplier to generate a demodulated audio output.

Abstract: Provided are modulation and demodulation methods and apparatuses using a frequency selective baseband. The frequency modulation method includes: generating a plurality of subgroups by dividing 2N (N is a real number) spread codes used for frequency spreading into 2M (M<N, M is a real number) spread codes; selecting P(P is a real number) subgroups among the generated subgroups; acquiring P spread codes by inputting M data bits to each of the p subgroups so as for 1 spread code to be selected among the 2M spread codes of each subgroup; and selecting dominant value among the acquired P spread codes to generate transmitting data including the dominant value. Accordingly, it is possible to increase a processing gain of the entire system, to increase a transmission data rate, and to reduce power consumption of the system.

Abstract: Disclosed is a demodulation circuit for demodulating an IF signal which is input via an antennal and then over-sampled at a sampling rate four times a frequency of a baseband signal, the demodulation circuit including a mixer for converting the IF signal down to a baseband signal using a coefficient corresponding to either sine values or cosine values, a DEMUX for dividing the down-converted baseband signal into a plurality of signals, and a PPF having a plurality of sub-filters for filtering the divided signals input from the DEMUX and a plurality of adders for operating the output signals of the sub-filters. As a result, the demodulation circuit can be realized in a small hardware size and is capable of reducing power consumption.

Abstract: A radio frequency (RF) receiver for receiving transmissions of different modulations includes cycling between a first mode for receiving transmissions of a first modulation that occurs frequently and a second mode for receiving transmission of a second modulation that occurs infrequently. The example RF receiver is cycled between a first modulation for receiving a frequency shift keyed (FSK) transmission from a tire pressure monitoring (TPM) system and a second modulation for receiving an amplitude shift keyed (ASK) transmission from a remote keyless entry (RKE) system. The RF receiver cycles between different modulations to detect the most frequent FSK modulated transmissions while also detecting and receiving the relatively infrequent ASK modulated RKE transmissions without an undesirable delay.

Abstract: Apparatus and methods for data demodulation in FM-FSK communication systems may include comparing the power spectral density (PSD) of the received frequency spectrum with that of the previously received samples using digital signal processing on a multi-sample message. A narrow band FM-FSK receiver may include a filter configured to pass FM signal components of a predetermined signal band, a memory configured to store the filtered signal component, and a DSP operably connected to the filter and the memory. The DSP may be configured to output a digital signal based upon a comparison of successive DSP calculated frequencies associated with a peak power of a power spectrum density (PSD) of successive samples of the filtered multi-sample message.

Abstract: Certain embodiments of the present invention provides a system and method for SAP FM demodulation. The system includes a bandpass filter for isolating the SAP signal, a Hilbert filter to produce a copy of the SAP signal phase shifted by 90 degrees, an FM demodulator for demodulating the SAP signal using the phase shifted SAP signal and a delayed SAP signal, and a lowpass filter to eliminate noise from the FM demodulated SAP signal. The system may also include an automatic gain control for normalizing amplitude of FM demodulator input signals. The digital FM demodulator uses a simplified approximation using non-unity delay for simplified demodulation of frequency modulated signals.

Abstract: A high frequency signal detection circuit includes an input terminal for a high frequency signal to be detected, a switch transferring the high frequency signal as intermittent ringing signal to a first node in response to a pulse signal whose frequency is lower than that of the high frequency signal, a transistor amplifying the signal at the first node, and outputting to a second node, a bias generator generating a bias voltage by which the transistor is operated in its weak inversion region, a resonant circuit outputting the bias voltage to the first node, and resonating the high frequency signal, a capacitor removing a high frequency component of the signal at the second node; and a judgment circuit judging whether or not the high frequency signal is inputted by detecting the signal at the second node, which has the same frequency as the pulse signal.

Abstract: A demodulator circuit for demodulating a signal modulated by frequency shift keying discriminates the frequency of the signal to produce demodulated data. When the demodulated data match a known synchronization pattern, or are complementary to the known synchronization pattern, the demodulator circuit latches a value indicating whether the demodulated data match or are complementary to the synchronization pattern. If the latched signal indicates matching data, subsequent demodulated data are output as is. If the latched signal indicates complementary data, subsequent demodulated data are inverted and the inverted data are output. The output data are therefore correct even if the demodulated data are inverted.

Abstract: An efficient configurable signal filter. The filter includes a first mechanism for receiving a first signal of a first type and a second signal of a second type. A second mechanism selectively filters the first signal during a first mode of operation, and filters the second signal during a second mode of operation. A third mechanism generates control signals. A fourth mechanism automatically configures the second mechanism to operate in the first mode of operation or the second mode of operation based on the control signals. In a specific embodiment, the first type of signal is characterized by a first rate, and the second type of signal is characterized by a second rate. The first signal and the second signal are digital ADC outputs. The second mechanism includes plural filter blocks, each having one or more Multiply-Accumulate (MAC) pipes. Each of the one or more MAC pipes include one or more MAC blocks that are each associated with a coefficient memory data structure of a coefficient memory.

Abstract: The present invention relates to a digital receiver for FM signals, in particular to a new demodulator structure and demodulating method, by which according to a first aspect of the invention the usual complex de-rotation process is reduced to a simple addition/subtraction. According to a second aspect of the invention, the requirements for the sampling frequency necessary for processing the demodulator signals are reduced substantially.

Abstract: An FM detector circuit includes an unbalanced/balanced conversion circuit, a signal synthesis circuit, a parallel circuit including a first diode connected between a first balanced output terminal of the unbalanced/balanced conversion circuit and one signal input terminal of the signal synthesis circuit and a resonator, a parallel circuit including a second diode connected between a second balanced output terminal of the unbalanced/balanced conversion circuit and the other signal input terminal of the signal synthesis circuit and a capacitor element, and a low-pass filter connected to an output terminal of the signal synthesis circuit.

Abstract: Apparatus having corresponding methods and computer-readable media comprises a receiver to receive a wireless stereo frequency-modulation (FM) signal comprising a plurality of spectral signal components including a first tone and one or more frequency bands; one or more tone generators each to generate a respective second tone based on a respective one of the frequency bands; a plurality of phase circuits each to measure a phase of a respective one of the first and second tones; and a difference element to determine a phase difference between two of the phases.

Abstract: Provided are a method and system for demodulating a signal. The method includes receiving the signal along first and second signal paths within a demodulator having a common starting point. Impedance values along each of the paths are changed alternately in synchronism.