Abstract: The disclosed embodiments relate to the design of a system that implements a reflectarray antenna. The system includes a time-modulated metasurface, which is configured to act as a planar reflector for an electromagnetic wave that is radiated by a feeder into free space at an operation frequency f0. The time-modulated metasurface includes time-modulated unit-cells that provide a nonlinear conversion between f0 and another desired frequency fd. The system also includes a phase-delay mechanism, which adjusts a phase delay by acting on a phase applied to a modulation frequency fm that modulates each unit-cell. The nonlinear conversion and the phase-delay mechanism operate collectively to facilitate angle-independent nonreciprocity by imposing different phase gradients during up-conversion and down-conversion processes, and by preventing generation of certain propagative harmonics due to total internal reflection.

Abstract: A signal input from a microphone is A-D converted by an A-D converter, is frequency differentiated by a pre-emphasis circuit, and is input to a shift control circuit. The shift control circuit includes a limiter circuit, a phase shifter, and a harmonic suppressor. The limiter circuit performs amplitude limitation so as to limit the amplitude of the input control target signal to be equal to or less than a first threshold. The phase shifter shifts, for the control target signal having the amplitude limited, a phase of a frequency component within the predetermined frequency range. The harmonic suppressor suppresses, for the control target signal phase-shifted by the phase shifter, a frequency component equal to or greater than a second threshold, and outputs an information signal that is the control target signal having the frequency component of equal to or greater than the second threshold suppressed. The modulator performs frequency modulation on a carrier wave in accordance with the information signal.

Abstract: A demodulator including a delay line adapted for receiving an input signal at an input frequency, phase or frequency modulated by symbols with a duration equal to a period of the input signal or very close to that period. The delay line has Nd outputs producing Nd signals at the input frequency but with Nd different delays offset by ?T relative to one another, Nd being an integer number greater than or equal to 1. The demodulator also includes a register of Nd latches each receiving a respective output of the delay line and a clock signal which is the input signal, in order to store the state of the outputs of the delay lines at the end of a period of the clock signal in the register. The content of the register represents a value of an input signal modulation symbol.

Abstract: Enhanced granularity operational parameters adjustment of components and modules in a multi-band, multi-standard communication device. For supporting two-way communications, a communication device includes receiver and transmitter modules. Each module includes various components that are configurable and/or programmable based on a protocol and band pair by which the communication device is operating. The communication device is a multi-protocol and multi-band capable communication device capable to operate in accordance with any one protocol and band at a first time and another protocol and band at a second time. The various components within each of the receiver and transmitter modules can be adjusted using one or more operational parameters. In some instances, a given component can be controlled by more than one operational parameter. Alternatively, certain components are controlled only one operational parameter.

Abstract: A demodulator including a delay line adapted for receiving an input signal at an input frequency, phase or frequency modulated by symbols with a duration equal to a period of the input signal or very close to that period. The delay line has Nd outputs producing Nd signals at the input frequency but with Nd different delays offset by ?T relative to one another, Nd being an integer number greater than or equal to 1. The demodulator also includes a register of Nd latches each receiving a respective output of the delay line and a clock signal which is the input signal, in order to store the state of the outputs of the delay lines at the end of a period of the clock signal in the register . The content of the register represents a value of an input signal modulation symbol.

Abstract: A frequency change detector splits a frequency standard signal into two undelayed frequency signals, one of which is delayed by a predetermined amount. The delayed signal is then mixed with the undelayed frequency signal into a mixed signal that is further filtered and amplified for providing an output signal indicating frequency changes of the frequency standard signal. The mixed frequency signal indicates frequency changes of the original frequency standard signal without reference to another frequency standard. This frequency change detector is well suited for use on satellites as an early warning detection of changes in on-board atomic frequency standards.

Abstract: Compensating for wideband quadrature imbalance error by introducing inverse complex inputs to phase quadrature estimator filters to generate estimated quadrature distortion; summing estimator quadrature distortion with a delayed version of the actual complex input to obtain estimated quadrature output; comparing the output with the true output to obtain residual quadrature imbalance error; applying a least mean square to the inverse input and imbalance residual error to obtain an updated estimate of filter coefficients; updating the filter coefficients of the phase quadrature estimator; and updating the filter coefficients of a phase quadrature compensator with the filter coefficients of the phase quadrature estimator to obtain a quadrature output pre-compensated for quadrature imbalance error.

Abstract: Certain embodiments of the present invention provides a system and method for SAP FM demodulation. The system includes a bandpass filter for isolating the SAP signal, a Hilbert filter to produce a copy of the SAP signal phase shifted by 90 degrees, an FM demodulator for demodulating the SAP signal using the phase shifted SAP signal and a delayed SAP signal, and a lowpass filter to eliminate noise from the FM demodulated SAP signal. The system may also include an automatic gain control for normalizing amplitude of FM demodulator input signals. The digital FM demodulator uses a simplified approximation using non-unity delay for simplified demodulation of frequency modulated signals.

Abstract: A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2nd or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

Abstract: Certain embodiments of the present invention provides a system and method for SAP FM demodulation. The system includes a bandpass filter for isolating the SAP signal, a Hilbert filter to produce a copy of the SAP signal phase shifted by 90 degrees, an FM demodulator for demodulating the SAP signal using the phase shifted SAP signal and a delayed SAP signal, and a lowpass filter to eliminate noise from the FM demodulated SAP signal. The system may also include an automatic gain control for normalizing amplitude of FM demodulator input signals. The digital FM demodulator uses a simplified approximation using non-unity delay for simplified demodulation of frequency modulated signals.

Abstract: An FM detector circuit includes a bridge circuit having four sections with a discriminator connected as one of the four sections. An FM intermediate frequency is applied across one pair of diagonally opposed nodes of the bridge circuit and an output is picked up across the other pair of diagonally opposed nodes of the bridge circuit. The discriminator includes a piezoelectric material that is selected to produce stable overall temperature characteristics.

Abstract: A digitally implemented demodulator. A frequency-modulated signal is applied to a limiting amplifier such that the signal amplitude is fixed at a constant level. The signal is undersampled and quadrature demodulated. The demodulator generates the cross-product of the baseband complex envelope to recover the original modulating signal. A digital Frequency Shift Keyed signal can be further recovered by applying the recovered signal to a data slicer to square-up the signal, and a matched filter for improved error resistance.

Abstract: A transmitter for transmitting a high frequency transmit signal generates a low intermediate frequency quadrature signal, and up-converts the low intermediate frequency quadrature signal to the high frequency transmit signal. The frequency spectrum of the high frequency transmit signal has a transmit band and a sideband corresponding to the transmit band. The transmit band is confined to a total transmit band outside of which severe sideband filtering requirements.apply. Before up-converting, the transmitter provides that the sideband falls at a side of the transmit band such that the sideband falls within the total transmit band.

Abstract: A digital radio device having a quadrature demodulator that does not suffer from substantial amplitude roll-off at the relevant operating range. Such a device is obtained by a phase shifting network in a quadrature branch of the demodulator having a series arrangement of a resistor and an capacitor coupled to an inductor coupled to ground. A junction between the series arrangement and the inductor forms the output of the quadrature branch. Alternative embodiments are provided. The demodulator avoids asymmetric digital signal distortion which can have deteriorating effects, in particular to GFSK-signals or &pgr;/4-DQPSK signals, or the like, and further noise shift of data which is of particular importance in low [S/N]-systems such as paging systems.

Abstract: Transistors (12a, 12b) turn on and off with mutually opposite phase input signals. Capacitors (16a, 16b) discharge when the transistors (12a, 12b) turn on, and capacitors (16a, 16b) are charged by constant current from constant current sources (18a, 18b) when the transistors (12a, 12b) turn off. As a result, a gradually rising voltage is obtained at the positive input ends of comparators (14a, 14b) while the input signals are L. By comparing this with fixed voltages of reference sources (20a, 20b), signals having rise timing shifted from input signals by 90° are obtained. The outputs of the comparators (14a, 14b) are mutually shifted by 180°, and at the rise of these outputs, an RS flip-flop (22) is set and reset so that signals delayed in phase by 90° with respect to the input signals are obtained at its outputs.

Abstract: A circuit (100) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector (110) and a sigma-delta analog-to-digital converter (130). The FM ratio detector (110) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter (130), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic “1's” and logic “0's” that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal (132).

Abstract: A method for detecting and correcting non-linearities in radio-frequency, voltage controlled oscillators provides for digitization of the frequency signal by feeding the undelayed frequency signal and a delayed frequency signal generated therefrom into EXOR gates. The digital pulses produced thereform are converted using a low pass filter into a proportional DC voltage value which is proportional to the oscillator frequency and is used as a basis for producing a correction value for the frequency control of the oscillator.

Abstract: A circuit (100) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector (110) and a sigma-delta analog-to-digital converter (130). The FM ratio detector (110) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter (130), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic “1's” and logic “0's” that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal (132).

Abstract: A variable delay line detector (34, 48, 66)includes a power splitter (36, 50, 68), a mixer (44, 62, 72) and a variable delay line (42,52, 70). Various devices are suitable for the variable delay line (42, 52, 70), such as a non-linear transmission line (NLTL). By providing a variable delay line, the variable delay line detector (34, 48, 66) is adapted to be programmed in real time thus making it suitable in applications where the phase and or frequency of the input signal varies. As such, the variable delay line detector (34, 48, 66) may be used in applications heretofore unknown, such &a an inexpensive demodulator in a frequency hopped spread spectrum system.

Abstract: A frequency modulated signal demodulator circuit includes a phase shift element and a time delay element which operate on an input signal (V_IF). The phase shift element and the time delay element are provided by a gyrator component (14, 16, 20).

Abstract: A digital FM demodulation circuit which samples an input analog FM signal and digitally detects the sampled input signal has an arctangent circuit into which a second signal that is delayed from the sampled input signal by a constant time, and a third signal that is different in phase by 90 degrees from the second signal are input, and which outputs a corresponding arctangent value based on a result of a division of the two input signals. The arctangent circuit has: roundoff means for sequentially rounding the division result to one of plural typical values; and a ROM address unit for performing a control in which an arctangent value corresponding to the rounded typical value is selected from a ROM table containing arctangent values of the typical values, and the selected arctangent value is output.

Abstract: An approach for demodulating a frequency-modulated signal involves processing a frequency-modulated signal with a phase shifter network to provide a demodulated signal that has a relatively constant amplitude around the center frequency of the frequency-modulated signal and that exhibits a relatively linear phase change over an operational frequency range. Embodiments of the invention include a phase shifter network, using N number of cascaded all-pass filters, that receives as an input a limited amplitude signal and outputs a phase-shifted limited amplitude signal that is mixed with the limited amplitude signal. The phase shifter network may also comprise a low-pass bessel filter.

Abstract: The present invention is directed to a system, apparatus and method for averaging digitized phase values. In particular, the polar coordinates represented by the digitized phase values are converted to rectangular coordinates via trigonometric identities. Several coordinate values are averaged, and the quadrant information derived from the signs (+ or -) of the averaged values is used to efficiently convert the final averaged rectangular coordinates back to polar representation.

Abstract: A circuit is designed with a delay circuit (102) coupled to receive a frequency-modulated data signal (100) at a delay input terminal. The delay circuit produces the data signal (103) after a predetermined delay at a delay output terminal. An exclusive OR circuit (104) has a first input terminal coupled to the delay input terminal and has a second input terminal coupled to the delay output terminal.

Abstract: In a digital demodulation apparatus of a QPSK receiver which demodulates an input signal being modulated in the QPSK method by separating into an I (In Phase) channel signal and a Q (Quadrature) channel signal by a local carrier which is synchronized with the transmitter, A .pi.

Abstract: An FM demodulation circuit includes a phase conversion circuit which converts a frequency variation of an input signal into a phase variation and has a variable conversion characteristic, and a control current source circuit which outputs, when the level of the input signal drops lower than a predetermined level, control current to vary the conversion characteristic of the phase conversion circuit so that the demodulation sensitivity may be raised.

Abstract: An integrated circuit includes a demodulator having delay circuitry and demodulation control circuitry that may be fully formed within a common integrated circuit. The delay circuitry receives an input signal and generates a delayed input signal. The demodulation control circuitry generates a demodulated output based upon the input signal and the delayed input signal that has a level that is proportional to, or a finction of, a period of a respective cycle of the input signal. The demodulation control circuitry includes pulse generation circuitry, pulse delay circuitry, pulse conversion circuitry and sampling circuitry. The pulse generation circuitry generates a signal pulse based upon the input signal and the delayed input signal with a duration that is proportional to at least one period of the input signal. The pulse delay circuitry generates a delayed signal pulse based upon the signal pulse.

Abstract: A signal detection circuit employs a delay line with edge detection logic for capturing and buffering timing information about an input signal. A plurality of comparators for comparing the input signal to different reference potentials capture amplitude information in the input signal launching bits into respective delay lines. Preferably, each delay line includes a counter for counting detected bit edges.

Abstract: A frequency modulation (FM) signal demodulating circuit having a simple structure using general digital devices is provided. The FM signal demodulating circuit according to the present invention includes a first pulse generator for generating a pulse signal having a predetermined pulse width at every rising edge of the input FM signal, a second pulse generator for generating a pulse signal having a predetermined pulse width at every falling edge of the input FM signal, a combining portion for combining the pulse signals generated in the first pulse generator and the second pulse generator, and a low-pass filter for performing a low-pass filtering operation by receiving a combined pulse signal generated in the combining portion and outputting a signal having a magnitude corresponding to the frequency of the input FM signal.The FM signal demodulating circuit according to the present invention has a simple structure.

Abstract: A frequency selective noise reduction circuit and finds application in receiver demodulator arrangements in mobile telecommunication base stations. A receive signal is divided into two paths. One path includes a Phase Lock Loop circuit (PLL) which is employed to identify noise. The noise signal is inverted and then combined with the other signal.

Abstract: Radio receivers for frequency-modulated signals and more particularly, in such receivers, to a device for the demodulation of a signal modulated at intermediate frequency f.sub.i. The signal F.sub.M that is frequency modulated around a frequency f.sub.i is applied, after conversion into a square-wave signal F.sub.MR, to a delay line with shift registers that is controlled by the signals provided by an oscillator. Each of the three cascade-connected sections of the delay line introduces a delay 1/4f.sub.i and the output signals of each section are applied to EXCLUSIVE OR circuits that respectively give a demodulated signal F.sub.R1, a signal F.sub.R2 for the suppression of a demodulated signal and a signal F.sub.R3 to control the frequency of the oscillator.

Abstract: In order to process an input signal exhibiting a frequency modulation about an intermediate frequency, the demodulator includes a first mixer for producing a first signal exhibiting the frequency modulation about a transposition frequency lower than the intermediate frequency; a switched-capacitor phase-shifter receiving the first signal so as to produce a second signal exhibiting, with respect to the first signal, a phase-shift varying substantially linearly with frequency about the transposition frequency; two substantially identical low-pass filters receiving the second signal and the first signal respectively; and a second mixer for mixing the signals produced by the first and second low-pass filters, in order to deliver a baseband output signal.

Abstract: A frequency modulated signal demodulator circuit wherein an in-phase component (I) and an orthogonal component (Q) of a frequency modulated signal output from an orthogonal detector circuit are respectively delayed by one sampling time. The result (I.multidot.Qs) of multiplying the in-phase component (I) by a delayed orthogonal component (Qs) is subtracted from the result (Q.multidot.Is) of multiplying the orthogonal component (Q) by the delayed in-phase component (Is), and the subtraction result (d.theta.) is multiplied by an inverse (1/Ts) of the sampling time to derive an instantaneous angular frequency (d.theta./Ts), whereby the frequency modulated signal can be demodulated without any feedback loop which is required by conventional FM demodulator circuits, thus making it possible to avoid a deterioration demodulation characteristics due to the influence of phasing.

Abstract: A combination of two phase-lock loops, and a cancellation circuit are used to remove a dominant FM signal from within a signal environment. The two phase-lock loops together produce a replica of the highest power (i.e. dominant) FM signal. The cancellation circuit uses this replica in a demodulation, notch-filtering, and remodulation process to excise the dominant FM signal, leaving the other signal(s) undisturbed. Potential applications include co-channel FM signal/interference cancellation and optimizing utilization of RF spectrum.

Abstract: A delay-type FM demodulation circuit of this invention has an object to satisfactorily remove a harmonic wave in an arithmetic calculation output signal even if an LPF having relatively moderate stopping characteristics is used. The delay-type FM demodulation circuit includes first to third delay circuits for obtaining first to third signals obtained by times (e.g., 1/8, 1/4, and 3/8) which sequentially increase within a time shorter than 1/2 which is a signal period obtained when an FM-modulated input signal is positively deviated by a maximum frequency, a first multiplication circuit for multiplying the input signal and the first signal, a second multiplication circuit for multiplying the second signal and the third signal, and an addition circuit for adding an output signal from the first multiplication circuit and an output signal from the second multiplication circuit.

Abstract: Digital frequency demodulation is accomplished by monitoring similar transitions in an FM radio signal to determine frequency. Time intervals between similar transitions in the FM signal are established by selecting anticipated transition times and accumulating error values relative to actual transition times. Accumulated error values provide a basis for further selecting anticipated transition times in such manner that a reported sequence of anticipated transition times provides a basis for inferring signal frequency. In one illustrated embodiment, the chosen transition times are positive transitions in the FM signal and the anticipated times of transition are taken from a set of two time periods, an early transition and a late transition relative to a valid transition window. In one embodiment of the invention, accumulated error is stored in an integrator device while in another embodiment accumulated error is stored in the phase of a bi-frequency oscillator.

Abstract: In a digital frequency demodulator, data representing the input signal to be demodulated is prestored in a look-up table and signal processing is digitally performed to generate a read address required for reading out the data stored in the look-up table using a phase shift method of operation. Phase-shifting is performed by determining the slope of a frequency-modulated signal containing a signal which does not cross the zero axis. Thus, the precision of the frequency demodulation is enhanced, and the frequency demodulation data stored in the look-up table is minimized to reduce the size of a ROM used for the look-up table.

Abstract: An apparatus and method is provided of recovering a frequency modulated signal having a first component of the frequency modulated signal at a zero-RF spectral location and a second component of the frequency modulated signal at a zero-RF spectral location in quadrature relationship to the first component. The method includes the steps of: upconverting and summing the first and second components to produce a reference signal (100), time delaying the first and second components, upconverting and summing the delayed, upconverted first and second components to produce a delayed reference signal (101) in quadrature relationship to the reference signal; limiting the reference and delayed signal (102); and exclusive or-ing (103) the limited reference and limited delayed signal.

Abstract: The transmitter uses a synthesized oscillator (1A) whose reference (24) is provided by the clock (H) of the data (P, Q). The demodulation oscillator (13A) of the receiver is a synthesizer which is functionally identical to that (1A) of the transmitter, and its reference (23) is provided by the clock (H, 36) recovered from the received data.

Abstract: Digital frequency demodulation is accomplished by monitoring similar transitions in an FM radio signal to determine frequency. Time intervals between similar transitions in the FM signal are established by selecting anticipated transition times and accumulating error values relative to actual transition times. Accumulated error values provide a basis for further selecting anticipated transition times in such manner that a reported sequence of anticipated transition times provides a basis for inferring signal frequency. In one illustrated embodiment, the chosen transition times are positive transitions in the FM signal and the anticipated times of transition are taken from a set of two time periods, an early transition and a late transition relative to a valid transition window.

Abstract: FM quadrature demodulator having in-phase and quadrature terminals for applying a pair of FM-modulated signals in a mutual phase quadrature thereto, having a modulation signal which is frequency-modulated on a carrier, one of the two terminals being coupled to a first input of a first phase comparison circuit and the other terminal being coupled to a second input of the first phase comparison circuit via a first phase-shifting circuit which realizes a phase shift varying with said modulation signal, the first phase comparison circuit being connected to an output of the FM quadrature demodulator via a low-pass filter.

Abstract: In an FM detector circuit, a phase-shifting circuit is constituted by integrating circuits each consisting of a transconductance amplifier and capacitor. The phase-shifting circuit being arranged to cause limiter signal to be phase-shifted by 90 degrees at center frequency. A multiplying circuit is provided which is arranged to be provided with said limiter signal and output of said phase-shifting circuit, thereby effecting phase-detection of said limiter signal. Further, an error amplifier is provided which is supplied with a smoothed version of detection output derived from said multiplying circuit. The arrangement is made such that output of the error amplifier is applied to the transconductance amplifiers constituting said phase-shifting circuit.

Abstract: Apparatus for demodulating information signals frequency-modulated on an RF carrier signal carrying spectral components within the audio frequency range, a pilot carrier signal having an imparted phase shift from the phase of the transmitted pilot carrier signal, and amplitude-modulated spectral components having another imparted phase shift in a subcarrier channel frequency range above the audio frequency range. The apparatus includes a demodulator for demodulating the frequency-modulated information signals to provide a detected composite signal which includes a detected pilot carrier characterized by an imparted phase shift due to the effects of multipath reception, and detected amplitude modulated spectral components exhibiting another multipath induced phase shift.

Abstract: An FM demodulator which generates a modulated object signal directly in digital form, wherein an input FM signal is phase detected, then converted to digital form, then quantized into a pulse density modulated binary signal using a clock reference signal having a frequency which is not correlated to the frequency of the input FM signal, and then the signal is filtered at the clock reference signal and outputted as the digital word output. Advantageously, by using the non-correlated clock reference signal, the signal to noise ratio is improved by a substantial factor.

Abstract: A circuit array for frequency translation by means of quadrature heterodyne signals has very low quadrature errors even at very high frequencies and is monolithically integratable with little external circuitry. The circuit array includes a first mixer which receives a first portion of an input signal, a second mixer which receives a second portion of the input signal, and a heterodyne signal generator which receives a local oscillator signal and supplies quadrature heterodyne signals to the mixers. The heterodyne signal generator includes a control loop to ensure a 90.degree. phase shift between the quadrature heterodyne signals. The circuit array can be used in a modulator for a transmitter or in a demodulator for a receiver.

Abstract: An analog angle modulated signal is converted into a digital signal within an A/D converter using a sampling clock having a frequency an integer times higher than the carrier of the angle modulated signal. The digital signal is delayed by one sampling slot within each of four delay circuits connected in series to the A/D converter. The output of the A/D converter and that of the fourth delay circuit are multiplied by -1/2 within respective digital weighting circuits, and the multiplied outputs as well as the output of the second delay circuit are added together to generate an I component level signal. The output of the first delay circuit is multiplied by -1 within another weighting circuit and this multiplied output as well as the output of the third delay circuit are added together to generate a Q component level signal.

Abstract: An imput for receiving FM modulated video signals is connected to a first demodulator circuit, the output of which is connected to the first input of an adder. The input is also connected to a transversal filter, the output of which feeds a Hilbert transform circuit that has its output connected to a second demodulator circuit. The output of the second demodulator is connected to a second input of the adder, the adder providing an FM demodulated video signal with reduced moire and improved signal-to-noise ratio. In a second embodiment, the Hilbert transform circuit is formed by delay circuits and a subtraction circuit connected to subtract the output of the delay circuits from the input thereto. An adder is connected to add the output of the delay circuits to the input thereto. First and second demodulation circuits receive the outputs from the subtractor and adder, respectively, and the outputs of the first and second demodulation circuits are mixed to produce the FM demodulated video signal.

Abstract: A direct conversion receiver having a tri-phase architecture including three separate baseband signal channels. RF communications signals which are being tuned by the receiver are split into three equal and in-phase components which are mixed with three equal but substantially out-of-phase injection signals on frequency with the communications signal. The resulting baseband component signals are independently filtered and amplified on the three signal channels. The baseband components are then directed to a signal processing unit which corrects the baseband components for gain or phase mismatch errors between the signal channels based on the information carried by the three components and thereafter demodulates the signals in order to acquire the information carried by the RF communications signal. An automatic gain control system and a signal filtering system adapted for use with direct conversion receivers are also disclosed.

Abstract: A circuit arrangement which includes an FM demodulator having a delay circuit which subjects the received FM signal to a preset time delay and a signal combining circuit which combines the delayed and undelayed FM signal to derive a combined signal the mean value of which is proportional to the frequency of the FM signal. A low pass filter derives the demodulated signal from such combined signal. The proportionality factor is determined by the preset time delay, which is controllable by a control signal supplied to the delay circuit by a datum level detector which detects a selected datum level of the demodulated signal; for example, the lowest level of such signal. By controlling the time delay in accordance with such datum level, the datum level detector thereby stabilizes the maximum amplitude of the demodulated signal relative to the datum level thereof despite variations in the maximum frequency swing of the received FM signal.

Abstract: An improved multilevel FSK demodulator, according to the invention, is provided that down-converts the IF frequency back to baseband quadrature via dual mixers. The improved multilevel FSK demodulator uses controllable time-delay in the demodulation process. This method requires a 90.degree. phase difference between 2 modulated signals to produce a maximum demodulated output amplitude at the maximum frequency deviation. Since the IF frequencies have been down-converted back to baseband quadrature, these 2 signals are only "out of phase" by an amount .DELTA.t that is equal to 90.degree./d.omega.. A further aspect of this invention addresses minimizing the DC offset from the demodulator by providing a feedback signal which controls the amount of delay provided to one of the quadrature signals.