Including Plural Detector Diodes (e.g., Ratio Detector Type) Patents (Class 329/340)
  • Patent number: 8198936
    Abstract: A semiconductor device is provided, which comprises a first demodulation circuit, a second demodulation circuit, a first bias circuit, a second bias circuit, a comparator, an analog buffer circuit, and a pulse detection circuit. An input portion of the pulse detection circuit is electrically connected to an output portion of the analog buffer circuit, a first output portion of the pulse detection circuit is electrically connected to an input portion of the first bias circuit, and a second output portion of the pulse detection circuit is electrically connected to an input portion of the second bias circuit.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: June 12, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takanori Matsuzaki
  • Patent number: 7405613
    Abstract: A circuit and method for differential slope demodulator circuit are shown that utilize amplitude stabilizing of a frequency modulated signal to obtain an amplitude stabilized signal. Also shown is bandpass filtering of the amplitude stabilized signal for a first frequency that is offset by a shift frequency below an intermediate frequency, to obtain a first filtered signal and bandpass filtering the amplitude stabilized signal for a second frequency that is offset by the shift frequency above the intermediate frequency, to obtain a second filtered signal. The circuit and method further operate by detecting an envelope of the first filtered signal to obtain a first envelope signal, detecting an envelope of the second filtered signal to obtain a second envelope signal, and differencing the first and second envelope signals to obtain a demodulated output signal.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: July 29, 2008
    Assignee: Integration Associates Inc.
    Inventor: Hendricus C. De Ruijter
  • Patent number: 6951149
    Abstract: An output shaft locking device for a multi-clutch transmission in which a plurality of rotational mechanisms, each of which is formed by arranging a clutch and a shifting mechanism is series, is provided in parallel between a rotational power input shaft and a rotational power output shaft, and an output shaft locking method. The output shaft locking device includes a locking control device which locks the rotational power output shaft by engaging a shifting gear in each of the shifting mechanisms of at least two of the rotational mechanisms, and engaging each of the clutches of the rotational mechanisms. Thus, it is possible to lock the output shaft so as to fix wheels by engaging the shifting gear without providing a lock mechanism.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: October 4, 2005
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kazuhiro Yamamoto, Koji Naito, Takaya Amano
  • Patent number: 6573782
    Abstract: A circuit (100) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector (110) and a sigma-delta analog-to-digital converter (130). The FM ratio detector (110) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter (130), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic “1's” and logic “0's” that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal (132).
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: June 3, 2003
    Assignee: Motorola, Inc.
    Inventors: Raymond Louis Barrett, Jr., Barry Herold, Scott Humphreys