Abstract: A BTE prosthetic device for use in a medical system or prosthesis comprises a connector configured to mechanically attach an auxiliary device of the system to the BTE prosthetic device. The connector is electrically connected to a transceiver of the BTE prosthetic device. The connector operates as an electromagnetic antenna for transmitting and/or receiving signals between the BTE prosthetic and other components of the medical system.

Abstract: Disclosed herein are a Bluetooth signal receiving device and method. The Bluetooth signal receiving device includes a frequency shift demodulator circuit, a sampler circuit, a training bit pattern discriminator circuit, and a frequency offset compensation circuit. The frequency shift demodulator circuit generates a baseband signal by performing frequency shift demodulation on a received signal, and generates a frequency proportion signal having a value proportional to the frequency of the baseband signal. The sampler circuit generates a plurality of series of bit streams from the frequency proportion signal. The training bit pattern discriminator circuit determines whether the plurality of series of bit streams generated by the sampler circuit satisfies a training bit pattern condition.

Abstract: In an apparatus and method, time-varying signals are processed and encoded via a frequency domain linear prediction (FDLP) scheme to arrive at an all-pole model. Residual signals resulted from the scheme are estimated and transformed into a time domain signal. Through the process of heterodyning, the time domain signal is frequency shifted toward the baseband level as a downshifted carrier signal. Quantized values of the all-pole model and the frequency transform of the downshifted carrier signal are packetized as encoded signals suitable for transmission or storage. To reconstruct the time-varying signals, the encoded signals are decoded. The decoding process is basically the reverse of the encoding process.

Abstract: A demodulator for demodulating a modulated signal has a peak detector (206) with an input (100) coupled to receive the modulated signal and an output (207) to supply a peak detector output signal. The peak detector has a charge storer (314) coupled to the peak detector output so that the peak detector output signal is provided by a voltage across the charge storer (314) and a comparator (313) having a first comparator input coupled to the peak detector input to receive the modulated signal and a second comparator input coupled to the peak detector output to receive the peak detector output signal. The comparator (313) provides a comparison signal representing a comparison between the voltage of the modulated signal and the peak detector output signal.

Abstract: A time-based, digital FM demodulator circuit receives a stream of digital samples corresponding to an analog FM waveform. The samples are provided to a zero crossing detector, which allows a counter to determine a number of clock cycles between zero crossings. The resolution of this coarse period determination is further refined by an intercept calculation, which further localizes the zero crossing of the FM waveform based on interpolation between samples on either side of the zero crossing. Accuracy of the period determination may be further enhanced by use of a sinusoidal correction filter, which minimizes error caused by the linear interpolation performed on the sinusoidal waveform. Although the FM demodulator circuit is particularly suitable for demodulation of the chroma component of a SECAM video signal, it may advantageously be applied in a wide variety of FM demodulation applications.

Abstract: A quadrant deciding section decides the quadrant to which a received signal belongs based on a baseband signal. A rotation projector rotates the received signal and projects the rotated signal to a straight line that intersects orthogonally at the origin with a straight line that bisects the decided quadrant. An integrator integrates the signal after the projection. A one-bit quantizer quantizes the integration result by deciding the sign of the integration result. A delay circuit delays the quantized signal by a predetermined time. An adder adds the decision result and the quantized signal modulo the phase 2?. A low-pass filter sequentially latches phase values after the addition with internal shift registers, converts the phase value to a prescribed specific value when the phase values that cross over 2? exist in the whole data within the registers, and averages the phase values.

Abstract: A digital FM demodulator employs a baseband phase lock loop (BBPLL), which is particularly effective for long range reception, for combining and demodulating a pair of signals represented by the mathematical expression A(t)ej&thgr;(t) to result in an approximation of d&thgr;/dt. This approximation is then subjected to an inverse of the linear approximation of the frequency response of the BBPLL that produces a very accurate &thgr;. This is conveniently achieved with a IIR filter whose transfer function happens to be the same as the inverse of the linear approximation of the frequency response of the BBPLL. The derivative is then taken of &thgr; to produce a very accurate d&thgr;/dt, the desired result for the output of an FM demodulator. To aid operation of the BBPLL, the incoming digital intermediate frequency is upsampled by a combination of sample and hold and FIR filtering prior to being processed by the BBPLL.

Abstract: Provided is a time counting circuit which can measure the time taken from the rising edge to the falling edge of a pulse signal and the time from the falling edge to the rising edge thereof. The time counting circuit according to the present invention comprises a measuring circuit for measuring the time between either of the rising and falling edges of the pulse signal, and a pulse converting circuit for converting a pulse signal to be measured to a pulse signal having either of the edges in accordance with the rising edge of the pulse signal to be measured and having either of the edges in accordance with the falling edge of the pulse signal to be measured. The time between either of the edges of the pulse signal converted by the pulse converting circuit is measured by the measuring circuit. The time obtained by measurement is the time taken from the rising edge to the falling edge of the pulse signal to be measured or the time taken from the falling edge to the rising edge thereof.

Abstract: A frequency demodulator of the present invention includes: an amplification section for receiving a frequency-modulated signal and amplifying the frequency-modulated signal based on a gain so as to produce a digital signal having a predetermined level and an inverted signal of the digital signal; a digital demodulation section for receiving the digital signal and frequency-demodulating the digital signal; an amplitude detection section for receiving the digital signal and the inverted signal of the digital signal, and detecting maximum amplitude values of the digital signal and the inverted signal for a predetermined period of time so as to produce an amplitude signal in proportion to the maximum values; and a gain controlling section for varying the gain based on the amplitude signal.

Abstract: A circuit is designed with a delay circuit (102) coupled to receive a frequency-modulated data signal (100) at a delay input terminal. The delay circuit produces the data signal (103) after a predetermined delay at a delay output terminal. An exclusive OR circuit (104) has a first input terminal coupled to the delay input terminal and has a second input terminal coupled to the delay output terminal.

Abstract: A digital super-regenerative receiver is provided having an analog RF detector and a regenerative oscillator. The output of the RF detector is used to generate a digital signal from which the oscillator bias is adjusted, in order to maintain the oscillator start-up time at a fixed level. The circuit senses if the start-up time is earlier or later than the predetermined start-up time and produces an output when the majority of the start times are ahead of the expected start time.

Abstract: Apparatus and method for digital frequency discrimination are provided that only require one sample per data symbol (e.g. one bit for BPSK or 2 bits for QPSK). This is accomplished by determining the difference between the carrier phase error on successive data symbols. The difference in phase error is then used as an approximation to the derivative of the phase error, which is the frequency error between the carrier and the local oscillator of the receiver. An important advantage of this apparatus and method is that they allow the maximum symbol rate to be processed by the receiver for a given digital technology. In other words, maximum symbol rate can now be equal to the maximum clock rate of the digital technology, if so desired by the user. In contrast, conventional digital frequency discriminators limit the maximum symbol rate to one-half or one-fourth of the maximum clock rate for a given digital technology.

Abstract: A signal detection circuit employs a delay line with edge detection logic for capturing and buffering timing information about an input signal. A plurality of comparators for comparing the input signal to different reference potentials capture amplitude information in the input signal launching bits into respective delay lines. Preferably, each delay line includes a counter for counting detected bit edges.

Abstract: An receiver receives, amplifies, filters, and downconverts an RF signal to obtain an FM signal. The FM signal is then limited by a limiter and sampled by an ADC. The FM samples from the ADC are provided to an edge detector which detects transitions in the FM samples. The transitions correspond to zero crossings in the FM signal. The time period between the zero crossings, or the cycle width, is measured with a counter to determine the instantaneous frequency f.sub.c of the FM signal. The demodulated output is proportional to the instantaneous frequency which can be determined from the measured cycle periods as f.sub.c =1/2T.sub.c, f.sub.c .apprxeq.-.alpha.T.sub.c, or f.sub.c .varies.T.sub.c, where T.sub.c is the measured cycle period, and .alpha. is a constant based on the slope of 1/2T.sub.c,avg, where T.sub.c,avg is the average cycle period. The sample rate of the demodulated output can be reduced, through resampling, to minimize power consumption in the subsequent signal processing blocks.

Abstract: Frequency modulated signals are demodulated through a limiter circuit that chops the signal to give pulses whose occurrence frequency is proportional to the instant frequency of the received signal. The invention is devoted to a new processing of those pulses. The leading edges of the pulses are time integrated. The obtained signal is then as usual, low pass filtered to give the demodulated signal. The main advantage of this new processing is that the circuit that makes this processing does not implement delay lines and can then be made as a single chips.

Abstract: A frequency modulation (FM) signal demodulating circuit having a simple structure using general digital devices is provided. The FM signal demodulating circuit according to the present invention includes a first pulse generator for generating a pulse signal having a predetermined pulse width at every rising edge of the input FM signal, a second pulse generator for generating a pulse signal having a predetermined pulse width at every falling edge of the input FM signal, a combining portion for combining the pulse signals generated in the first pulse generator and the second pulse generator, and a low-pass filter for performing a low-pass filtering operation by receiving a combined pulse signal generated in the combining portion and outputting a signal having a magnitude corresponding to the frequency of the input FM signal.The FM signal demodulating circuit according to the present invention has a simple structure.

Abstract: A digital frequency demodulator includes a first counter and a second counter measuring the instantaneous and mean values of the period of a frequency modulated signal. A comparator compares the values measured and creates a binary signal of the same frequency as the modulation signal. The measurement of the instantaneous value of the frequency modulated signal is effected by counting the number of reference clock pulses during a period of the modulated signal, and the measurement of the mean value is effected by counting the number of pulses of a clock signal of frequency N times lower than the reference clock during N periods of the modulated signal.

Abstract: Radio receivers for frequency-modulated signals and more particularly, in such receivers, to a device for the demodulation of a signal modulated at intermediate frequency f.sub.i. The signal F.sub.M that is frequency modulated around a frequency f.sub.i is applied, after conversion into a square-wave signal F.sub.MR, to a delay line with shift registers that is controlled by the signals provided by an oscillator. Each of the three cascade-connected sections of the delay line introduces a delay 1/4f.sub.i and the output signals of each section are applied to EXCLUSIVE OR circuits that respectively give a demodulated signal F.sub.R1, a signal F.sub.R2 for the suppression of a demodulated signal and a signal F.sub.R3 to control the frequency of the oscillator.

Abstract: A frequency modulated signal demodulator circuit wherein an in-phase component (I) and an orthogonal component (Q) of a frequency modulated signal output from an orthogonal detector circuit are respectively delayed by one sampling time. The result (I.multidot.Qs) of multiplying the in-phase component (I) by a delayed orthogonal component (Qs) is subtracted from the result (Q.multidot.Is) of multiplying the orthogonal component (Q) by the delayed in-phase component (Is), and the subtraction result (d.theta.) is multiplied by an inverse (1/Ts) of the sampling time to derive an instantaneous angular frequency (d.theta./Ts), whereby the frequency modulated signal can be demodulated without any feedback loop which is required by conventional FM demodulator circuits, thus making it possible to avoid a deterioration demodulation characteristics due to the influence of phasing.

Abstract: A DMUX 11 outputs data in a digital FM signal in a circulation to produce signals S1 to S4. An MUX 14 alternately outputs inverted signals of the signals S1 and S3, obtaining a signal Si.sub.(k). An MUX 15 alternately outputs inverted signals of the signals S2 and S4, obtaining a signal Sq.sub.(k). An interpolation circuit 17 inserts data having a value of zero between individual data in the output signal of the MUX 14, and cuts off the high-frequency component of the resultant signal, obtaining a signal Si.sub.(i). A second interpolation circuit 19 inserts data having a value of zero between individual data in the output signal of the MUX 15, and cuts off the high-frequency component of the resultant signal, obtaining a signal Sq.sub.(i). An arithmetic operation circuit 2 computes SI.sub.(i-1) .multidot.SQ.sub.(i) -SI.sub.(i) .multidot.Sq.sub.(i-1), and integrates it to obtain a digital demodulated signal.

Abstract: A phase detection system in which an original modulation signal is detected from a first complex baseband signal obtained through orthogonal demodulation of an FM signal and output, a second complex baseband signal having cosine and sine components of a phase change .DELTA..phi. of the first complex baseband signal in a predetermined time interval .tau. is rotated until a rotation angle .theta. becomes .DELTA..phi., and rotation angle data indicative of the rotation angle .iota. is detected and output.

Abstract: An up/down counter within a phase locked loop is gated to count high frequency clock pulses during the first cycle of the input signal. Upon detection of a transition in the input signal indicating the end of the first cycle, the direction of the count is reversed until the count is reduced to zero, thereby assuring equal widths for the first and second half cycles of each output cycle. The system may be implemented with or without a voltage controlled oscillator. In the latter implementation, the count in the up/down counter at the time of a reversal in the count direction is compared with the count in a preset counter. A difference counter compares the differences in a count in the two counters and adjusts the count in the preset counter to match that in the up/down counter at the time of transition. The widths of the successive cycles, rather than half cycles, may be made by doubling the output frequency relative to the input frequency.

Abstract: To demodulate an analog signal having information modulated by a carrier, the analog signal is chopped by a chopper, the chopped signal is digitized by a sigma-delta analog-to-digital converter to produce a series of digital samples at a sampling frequency, the digital samples are filtered in a digital decimating filter to produce data words, and the data words are modulated by an intermediate frequency signal to produce a detected information signal. The various frequency signals are generated by a phase-lock loop so that the intermediate frequency is the difference between the carrier frequency and the chopping frequency, and both the chopping frequency and the intermediate frequency are sub-multiples of the sampling frequency.

Abstract: Digital frequency demodulation is accomplished by monitoring similar transitions in an FM radio signal to determine frequency. Time intervals between similar transitions in the FM signal are established by selecting anticipated transition times and accumulating error values relative to actual transition times. Accumulated error values provide a basis for further selecting anticipated transition times in such manner that a reported sequence of anticipated transition times provides a basis for inferring signal frequency. In one illustrated embodiment, the chosen transition times are positive transitions in the FM signal and the anticipated times of transition are taken from a set of two time periods, an early transition and a late transition relative to a valid transition window. In one embodiment of the invention, accumulated error is stored in an integrator device while in another embodiment accumulated error is stored in the phase of a bi-frequency oscillator.

Abstract: The digital FM demodulation apparatus includes a sampling unit, a frequency specifying unit, and a demodulated value specifying unit. The sampling unit samples an FM modulated wave at predetermined intervals. The frequency specifying unit specifies a frequency of the FM modulated wave at the time of sampling based on a plurality of sampled values. The demodulated value specifying unit specifies a demodulated value corresponding to the frequency to provide the demodulated value.

Abstract: Digital frequency demodulation is accomplished by monitoring similar transitions in an FM radio signal to determine frequency. Time intervals between similar transitions in the FM signal are established by selecting anticipated transition times and accumulating error values relative to actual transition times. Accumulated error values provide a basis for further selecting anticipated transition times in such manner that a reported sequence of anticipated transition times provides a basis for inferring signal frequency. In one illustrated embodiment, the chosen transition times are positive transitions in the FM signal and the anticipated times of transition are taken from a set of two time periods, an early transition and a late transition relative to a valid transition window.

Abstract: An FM receiver includes an FM discriminator having a comparator for converting the FM signal to a series of discrete square-wave pulses all of the same amplitude and of a repetition rate varying with the frequency of the FM signals; and an integrator circuit which integrates the series of monopolar square-wave pulses to produce an output signal having an amplitude varying with the repetition rate of the square-wave pulses. Also described are FM stero systems including the above FM discriminator in its audio channels.

Abstract: An FM or PM signal is demodulated so that the cycle time of the modulated input signal is measured using a time-to-digital converter comprising a counter that uses a moderate clock frequency as a reference clock, a digital delay line interpolator and a control circuitry. The counter is used for rough digitization and the delay line for interpolating the moment of zero-crossing inside a clock cycle. Total delay of the delay line, i.e., the range of time intervals the interpolator is able to measure, is actively kept equal to the cycle time of the reference clock. When the number of delay elements in the delay line is a power of two, the result of the delay line interpolator may be used directly as the least significant bits of the measurement.

Abstract: For an integratable FM demodulator which has an optimal noise behavior and does not require any balancing, the demodulator includes a marker pulse generator (2) having an integrator (22) which is succeeded by a comparator (23), while at the start of each positive and/or negative edge of the limited FM signal, a marker pulse is started and one of a first and second reference signals is applied to the integrator input until a predetermined edge of the reference clock signal appears, and the first and a second reference signals are subsequently applied alternately to the integrator input in dependence upon a reference clock signal applied to the marker pulse generator, the two reference signals being applied to the integrator input during the desired period of time of the marker pulse, each time during equal overall time intervals, and a comparison voltage occurring at the integrator output at the end of the desired period of time, which comparison voltage is detected by the comparator (23), whereupon the starte

Abstract: An FM discriminator (34) which independently recovers modulating information from each half-cycle of a modulated waveform (16) is disclosed. The discriminator (34) includes a comparison circuit (36-42, 80-82) which produces bipolar signals describing positive and negative half-cycles of the modulated waveform (16). These bipolar signals are de-glitched (80, 82, 52, 54) for respective positive and negative counter circuits (44p, 44n). Each of the counter circuits (44) includes a counter (58) which counts a high speed clock signal supplied by a clock generator (46) during one of the half-cycles to produce a period count that describes the duration of the half-cycle. During a subsequent half-cycle, a translation circuit (60) converts the period count into an amplitude value that describes the information modulated onto the modulated waveform (16), and a resetting circuit (64-68) presets the counter (58) to an initial value.

Abstract: A frequency demodulation circuit disclosed superposes pulses on an input frequency-modulated (FM) signal at substantially peaks of the FM signal before demodulating the FM signal so that zero cross points of the FM signal can be correctly restored. A peak detection circuit detects peaks of the FM signal or peaks of the fundamental wave of the FM signal, which substantially correspond to the peaks of the FM signal. A pulse generating circuit generates, from the peak detection result, a train of pulses respectively occurring at the same timings as those of the detected peak occurrance timings. The generated train of pulses and the FM signal are respectively fed to differential inputs of a differential input type limiter. An output signal of the limiter is fed to a pulse count circuit to obtain a frequency demodulated signal.

Abstract: The invention utilizes a commercially available so-called "quad-pack" of logic gates; i.e. four exclusive OR or exclusive NOR gates mounted in a package. With minimal use of additional components and minimal circuit coupling, a quad-pack of this type is used to produce a detector circuit with FM limiting and an approximate 90.degree. phase shift. The circuit can be used for detecting an FM modulated video signal.

Abstract: An FM signal demodulator for converting the frequency of an input signal to a corresponding voltage. The demodulator includes a delay circuit responsive to the input signal for delaying the phase of the input signal by a fixed time, an exclusive-OR gate responsive to the input signal and the delayed phase signal from the delay circuit for outputting a pulse signal having a duration corresponding to the fixed time and an LPF responsive to the pulse signal for generating an output signal having a level which changes in response to changes in the frequency of the input signal.

Abstract: A homodyne down-converter, for use in an IF signal demodulator and the like, includes an analog-to-digital converter (ADC) which receives the IF analog signal for conversion to a digital data stream by sampling at a sampling rate frequency substantially equal to four times the IF signal frequency. A digital mixer controllably inverts the sampled data to convert the data to baseband, before a circuit removes the effects of DC offset in the analog IF signal applied to the ADC. A discrete Hilbert Transform filter is used for generating streams of sequential in-phase I' and quadrature-phase Q' data words, which are resampled to temporally align the two data word streams at a new data rate, thus effectively removing sample offset without the need for separate misalignment correction circuitry.

Abstract: A FM demodulation circuit contains an analog-to-digital converter which converts an inputted frequency-modulated (FM) signal into a digital signal of one bit at a timing based on the predetermined clock signal and a differentiation circuit which differentiates the digital signal to thereby output a pulse train whose pulse density is in proportion to a frequency of the inputted FM signal. When the pulse train is supplied to a low-pass filter, the pulse train is converted into an analog signal, which is outputted as a demodulated signal. When the pulse train is supplied to a decimation circuit which includes a weight function generating portion and an accumulator, weighted function values are sequentially accumulated based on the level of the pulse train in the predetermined period so that the demodulated signal can be obtained in the form of a linear pulse code modulated (linear PCM) signal.

Abstract: In a digital FM demodulating apparatus of this invention, an input video signal is converted into a predetermined digital FM signal, e.g., Asin.theta. by a recording signal processor and supplied from an input terminal to a phase shift circuit. The phase shift circuit divides digital FM signal Asin.theta. into digital FM signals Asin.theta..sub.2 and Acos.theta..sub.2 phase-shifted from each other through 90.degree. and outputs the signals directly to an operational circuit. The digital FM signal Asin.theta. is converted into digital FM signals A'sin.theta..sub.1 and A'cos.theta..sub.1 delayed from signals Asin.theta..sub.2 and Acos.theta..sub.2 by predetermined periods by registers and supplied to the operational circuit. The operational circuit calculates signals Asin.theta..sub.2, Acos.theta..sub.2, A'sin.theta..sub.1 and A'cos.theta..sub.1. A result of tan.sup.-1 conversion of an output from the calculator performed by a ROM having a tan.sup.