Abstract: In a transmission method according to one aspect of the present disclosure, a encoder performs error correction coding on an information bit string to generate a code word. A mapper modulates a first bit string in which the number of bits is the predetermined integral multiple of (X+Y) in the code word using a first scheme, the first scheme being a set of a modulation scheme in which an X-bit bit string is mapped to generate a first complex signal and a modulation scheme in which a Y-bit bit string is mapped to generate a second complex signal, and modulates a second bit string in which the first bit string is removed from the code word using a second scheme different from the first scheme.

Abstract: Data modulation for use in a multi-carrier system, a demodulation method, a frame generation method, and a node. A transmitter node performs an inverse fast Fourier transform (IFFT) on successive L symbols of frequency domain data, wherein an inverse of an adjacent subcarrier interval of the frequency domain data is T0, and L?2. The transmitter node modulates, using a designated wave function, the successive L symbols of time domain data generated after the IFFT process, wherein an adjacent symbol interval of the L symbols after the modulation is T1, and T1>T0. A variable interval length of the designated wave function is N×T1, where N is a real number exceeding or equal to 2 or 3. The application also provides the corresponding demodulation method, frame generation method, and node. The application can better inhibit out-of-band power leakage, and maintain compatibility to LTE. Furthermore, an increased demodulation performance is provided at a receiver end.

Abstract: There is provided a digital data compression device including a domain converter configured to perform frequency domain conversion on input digital I/Q data and output coefficient data corresponding to the digital I/Q data; a data converter configured to receive the coefficient data output from the domain converter and convert the input coefficient data of Cartesian coordinates into coefficient data of polar coordinates; and a quantizer configured to quantize the coefficient data of the polar coordinates output from the data converter.

Abstract: In one embodiment, a method for encoding or decoding video content is provided. The method determines a plurality of sets of interpolation filters for use in interpolating sub-pel pixel values for a temporal prediction process of video content. Different sets of interpolation filters include different phase offset characteristics. A unit of video content is received. The method then selects one of the set of interpolation filters to interpolate a set of sub-pel pixel values for use in the temporal prediction process for the unit of video content based on characteristics associated with the encoding or decoding of the video content. The one of the set of interpolation filters is selected based on the phase offset characteristic of the one of the set of interpolation filters and the characteristics associated with the encoding or decoding.

Abstract: The invention provides a receiver associated with a body, e.g., located inside or within close proximity to a body, configured to receive and decode a signal from an in vivo transmitter which located inside the body. Signal receivers of the invention provide for accurate signal decoding of a low-level signal, even in the presence of significant noise, using a small-scale chip, e.g., where the chip consumes very low power. Also provided are systems that include the receivers, as well as methods of using the same.

Abstract: A method for dynamically clocking one component located into a Wireless telecommunication apparatus comprising a RF transceiver subject to desensizitation by said component EMI, characterized in that it involves the steps of performing an adaptive control on the clock rate of said component so as to locate a wideband noise PSD null just to the left or to the right, in the frequency domain, of the RF transceiver wanted carrier frequency (fw) Particularly, the control is performed by means of the control of programmable frequency dividers, and under the control of a general control unit (UCM) for the purpose of performing a contextual analysis of the current mode of operation of said wireless telecommunications and, in response to said contextual analysis, for determining the fine tuning of the clock rate to be applied to said component.

Abstract: A new coded continuous phase modulation (CPM) scheme is proposed to enhance physical layer performance of the current DVB-RCS standard for a satellite communication system. The proposed CPM scheme uses a phase pulse design and combination of modulation parameters to shape the power spectrum of CPM signal in order to improve resilience to adjacent channel interference (ACI). Additionally, it uses a low complexity binary convolutional codes and S-random bit interleaving. Phase response using the proposed CPM scheme is a weighted average of the conventional rectangular and raised-cosine responses and provides optimum response to minimize frame error rate for a given data rate.

Abstract: An I/Q demodulation apparatus and method with phase scanning are provided. The demodulation apparatus includes a ring oscillator, a first latch unit, a decoding unit, a counter unit, a second latch unit, a first arithmetical unit and a second arithmetical unit. The first latch unit samples phase signals outputted from the ring oscillator. The decoding unit decodes the output of the first latch unit to correspondingly generate fine code of a first, a second, a third and a fourth codes. The counter unit counts the phase signals. The second latch unit samples the output of the counter unit to correspondingly generate coarse code of the first, the second, the third and the fourth codes. The first arithmetical unit performs an addition/subtraction operation by using the first code and the second code. The second arithmetical unit performs the addition/subtraction operation by using the third code and the fourth code.

Abstract: A receiving system and a method of processing broadcast signals in the receiving system are disclosed. The receiving system includes a tuner, a known sequence detector, a carrier recovery unit, a baseband processor, and a channel equalizer. The tuner receives a broadcast signal of a passband including a data group. Herein, the data group comprises mobile service data, a plurality of known data sequences, and signaling data. The known sequence detector estimates an initial frequency offset and detects a position of each known data sequence based on the known data sequence having the first data pattern. The carrier recovery unit acquires an initial frequency synchronization using the initial frequency offset estimated by the known sequence detector and estimates a residual frequency offset based upon the known data sequences having the second data pattern so as to perform carrier recovery.

Abstract: A method (500) of demodulation, the method comprising the steps of receiving (510) a radio frequency signal, converting (520) the received radio frequency signal to a baseband signal, performing (530) symbol timing recovery on the baseband signal, and demodulating (540) the baseband signal. The baseband signal comprises alternating symbols spaced therebetween at an alternating first interval length and a second interval length, where the first interval length and second interval length are dissimilar. Communication units and a method of modulation are also described.

Abstract: Methods, systems and software are provided for high order signal modulation based on improved signal constellation and bit labeling designs for enhanced performance characteristics, including decreased power consumption. According to the improved signal constellation and bit labeling designs for enhanced performance characteristics, designs for 8-ary, 16-ary, 32-ary and 64-ary signal constellations are provided. According to an 8-ary constellation, improved bit labeling and bit coordinates are provided for a 1+7APSK signal constellation. According to a 16-ary constellation, improved bit labeling and bit coordinates are provided for a 6+10APSK signal constellation. According to three 32-ary constellations, improved bit labeling and bit coordinates are provided for a 16+16APSK signal constellation and two 4+12+16APSK signal constellations.

Abstract: In a receiver circuit, an analog signal processor frequency-converts an input high frequency signal into a baseband signal, and performs low pass filtering at a cutoff frequency below a desired-wave band. An ADC converts an output of the analog signal processor into a digital signal. A digital signal processor compensates an output of the ADC for a signal component in the desired-wave band which has been attenuated by the filtering operation of the analog signal processor.

Abstract: In one embodiment, an analog-to-digital converter (ADC) receives a radio frequency (RF) signal and converts the RF signal into a digital signal at an intermediate frequency. The ADC uses a sampling frequency that is a multiple of the intermediate frequency to perform the conversion. A selector receives the digital signal and outputs a combined in phase and quadrature signal at a plurality of sampling points based on the sampling frequency. A filter receives the combined in phase and quadrature signal and outputs a baseband in phase baseband signal and a baseband quadrature baseband signal.

Abstract: A basic symmetric ?/2 phase-detector receives four control signals that control a differential current at the detector's output. Each respective control signal is a linear combination of a respective pair of signals chosen from a first input signal, its logic complement, a second input signal and the logic complement of the latter. Operation is based on time-averaging the differential current, the result being zero at a phase difference of ?/2. By means of adding one or more additional current sources to the output, controlled by one or more of the control signals, the basic operation is skewed. The time-averaged output current is now made zero only at a value of the phase difference different from ?/2. In an embodiment with uniform current sources and resistors, the modified detector is configured for a phase difference of ?/2N .

Abstract: An alternating current motor control system constituted of: a control unit; a cycloconverter functionality; a phase control functionality; and a semiconductor switching unit comprising a plurality of electronically controlled semiconductor switches each associated with a particular winding of a target alternating current motor and each independently responsive to the control unit. In one embodiment the semiconductor switching unit is arranged to connect the windings of the target alternating current motor to a three phase power input in one of a star and a delta configuration responsive to the control unit.

Abstract: Provided is a test apparatus for testing a device under test that outputs, as an output signal, an amplitude-phase modulated signal having a level and a transition point phase selected from among a plurality of levels and a plurality of phases according to transmission data, the test apparatus comprising a comparing section that compares the output signal to a first comparison level, which is less than the expected level, before the expected phase, and compares the output signal to a second comparison level, which is greater than the expected level, and to a third comparison level, which is less than the expected level, after the expected phase; and a judging section that judges that the output signal matches the expected values on a condition that (i) the output signal is less than or equal to the first comparison level before the expected phase and (ii) the output signal is less than or equal to the second comparison level and greater than or equal to the third comparison level after the expected phase.

Abstract: The communications terminal and acquisition method is for use with Continuous Phase Modulation (CPM) and Phase Shift Keying (PSK) modulation-type signals, each modulation-type signal having a respective preamble phasing sequence. The communications terminal may include a wireless communications device to receive a modulated signal having one of the CPM and PSK modulation types, and having a symbol rate. A controller may be included to cooperate with the wireless communications device to perform a transform process, such as a Fourier Transform (FT) process, on the received modulated signal to detect the modulation type and the symbol rate of the received modulated signal based upon the preamble phasing sequence. Carrier phase and frequency of the received modulated signal may be estimated based upon bin amplitudes. Also, symbol timing may be estimated based upon a phase difference between tones associated with the preamble phasing sequence.

Abstract: A wireless communication device processes N Radio Frequency (RF) bursts contained within N slots of a digital communications time divided frame, wherein N is a positive integer greater than one. The wireless communication device includes an RF front end, a baseband processor, and an equalizer module. The RF front end is operable to receive the plurality of received RF bursts and to convert the RF bursts to corresponding baseband signals. The baseband processor is operable to receive the baseband signals, to pre-equalization process the baseband signals to produce processed baseband signals, and to post-equalization process soft decisions. The equalizer is operable to equalize the processed baseband signals to produce the soft decisions. These RF bursts may be contained in adjacent slots or, in non-adjacent slots, or in a combination of adjacent slots and non-adjacent slots.

Abstract: A device (100) for processing an input signal (102), the device (100) comprising a delay unit (104) adapted for delaying the input signal (102) by a predefined delay time, at least one phase shifting unit (106) each adapted for phase shifting the delayed input signal (108) by an assigned phase value, a plurality of mixer units (110) each adapted for mixing the input signal (102) with the delayed input signal (108) or with one of the at least one phase shifted signal (112), and an extraction unit (114) adapted for extracting information from each of the mixed signals (116).

Abstract: A demodulation apparatus that demodulates an amplitude-phase-modulated signal having a level and a transition phase selected from among a plurality of levels and a plurality of phases according to transmission data, comprising a clock recovering section that receives the amplitude-phase-modulated signal and recovers a clock signal synchronized with the amplitude-phase-modulated signal; an amplitude and phase detecting section that detects, with the clock signal as a reference, the level and the transition phase of the amplitude-phase-modulated signal; a data output section that outputs data corresponding to the level and the transition phase detected by the amplitude and phase detecting section; and a phase difference correcting section that outputs a correction signal for correcting an oscillation frequency of the clock signal output by the clock recovering section, according to the transition phase detected by the amplitude and phase detecting section.

Abstract: A modulation scheme detecting apparatus includes a first power estimating module, a second power estimating module and a decision module. The first power estimating module is utilized for evaluating a first nominal power of the received signal rotated by a first predetermined phase according to a first modulation scheme. The second power estimating module is utilized for evaluating a second nominal power of the received signal rotated by a second predetermined phase according to a second modulation scheme. The decision module is coupled to the first power estimating module and the second power estimating module, and is utilized for selecting a target modulation from the first and second modulation schemes according to the first nominal power and the second nominal power.

Abstract: Some embodiments discussed relate to an apparatus and method for processing signals, comprising receiving an input signal and forming a stream of digital samples of the input signal by sampling at a sampling frequency and mixing the stream of digital samples using a mixer sequence having a sine sequence and a cosine sequence based on the sampling frequency to generate an input sequence, each of the sine sequence and the cosine sequence including a plurality of components in an arrangement such that at least one of the components has a zero value and the remaining components has a non-zero value, and filtering the input sequence using a plurality of polyphase filter parts, each corresponding to the non-zero components of the sine sequence and the cosine sequence, and selectively combining the outputs of the polyphase filter parts to generate an in-phase sequence and a quadrature sequence.

Abstract: A receiver including first circuitry configured to combine corresponding soft decision values from at least two groups of RDS/RBDS data transmitted as part of a broadcast channel to generate a set of combined values and second circuitry configured to identify a subset of the combined values that indicate a relatively constant subset of the received values from the at least two groups of the RDS/RBDS data is provided.

Abstract: A demodulator is provided for demodulating a phase-modulated data signal. The demodulator includes a phase frequency detector to output a voltage representing a phase difference between a received phase-modulated data signal and a reference clock signal. The voltage is input to first and second phase change detectors, which are provided to measure the phase difference of the phase-modulated data signal during first and second time periods, respectively.

Abstract: A recursive demodulation apparatus is provided. Therecursive demodulation apparatus, including: a segment generation unit dividing data symbols with a residual frequency or phase error into a predetermined number of data symbols, and generating a plurality of segments, each of the plurality of segments including the predetermined number of data symbols; and a phase error correction unit sequentially correcting a phase error of each of the data symbols, included in the each of the plurality of segments, for each segment.

Abstract: An envelope (100) detector for detecting a modulation envelope of a modulated signal. The envelope detector includes a sensor (102). The sensor has a sensor input (1021), for sensing a signal forming a measure for the amount of electrical power presented at the sensor input (1021). The sensor input (1021) is electrically conducting connectable to an electrical path (14), along which electrical path (14) the modulated signal is transmitted. The detector (100) includes a filter (103) for removing from the sensed signal a part contributed to non-envelope signal components in the modulated signal; and a detector output (104) connected to the filter (103) for outputting an envelope signal.

Abstract: A digital demodulator includes a resonator having a resonance frequency same as a carrier frequency to store a charge corresponding to a digital signal modulated by phase shift keying, a capacitor to store the charge of the resonator, an amplifier including an input node and an output node between which the capacitor is connected to convert a stored charge of the capacitor into a voltage signal, and a controller configured to accumulate in the resonator the charge induced by the frequency signal modulated by phase shift keying in a first control mode and configured to transfer the charge of the resonator to the capacitor in a second control mode, to output the voltage signal corresponding to the stored charge of the capacitor from the output node of the amplifier.

Abstract: Disclosed is a demodulation circuit for demodulating an IF signal which is input via an antennal and then over-sampled at a sampling rate four times a frequency of a baseband signal, the demodulation circuit including a mixer for converting the IF signal down to a baseband signal using a coefficient corresponding to either sine values or cosine values, a DEMUX for dividing the down-converted baseband signal into a plurality of signals, and a PPF having a plurality of sub-filters for filtering the divided signals input from the DEMUX and a plurality of adders for operating the output signals of the sub-filters. As a result, the demodulation circuit can be realized in a small hardware size and is capable of reducing power consumption.

Abstract: Compensating for wideband quadrature imbalance error by introducing inverse complex inputs to phase quadrature estimator filters to generate estimated quadrature distortion; summing estimator quadrature distortion with a delayed version of the actual complex input to obtain estimated quadrature output; comparing the output with the true output to obtain residual quadrature imbalance error; applying a least mean square to the inverse input and imbalance residual error to obtain an updated estimate of filter coefficients; updating the filter coefficients of the phase quadrature estimator; and updating the filter coefficients of a phase quadrature compensator with the filter coefficients of the phase quadrature estimator to obtain a quadrature output pre-compensated for quadrature imbalance error.

Abstract: A demodulation device (1) in semiconductor technology is disclosed. The device (1) is capable of demodulating an injected modulated current. The device (1) comprises an input node (IN1), a sampling stage (DG1, IG1, GS1, IG2, DG2) and at least two output nodes (D1, D2). The sampling stage DG1, IG1, GS1, IG2, DG2) comprises transfer means (GL, GM, GR) for transferring a modulated charge-current signal from the input node (IN1) to one of the output nodes (D1, D2) allocated to the respective time interval within the modulation period. The small size and the ability to reproduce the device (1) in standard semiconductor technologies make possible a cost-efficient integration of the device (1).

Abstract: The present invention relates to a digital receiver for FM signals, in particular to a new demodulator structure and demodulating method, by which according to a first aspect of the invention the usual complex de-rotation process is reduced to a simple addition/subtraction. According to a second aspect of the invention, the requirements for the sampling frequency necessary for processing the demodulator signals are reduced substantially.

Abstract: The invention relates to a device for demodulating an input signal containing information being conveyed by phase modulation of a carrier wave. A transmitter generates a signal controlling a phase variation in the carrier wave, for each symbol having N cycles, N being an integer strictly greater than 1. The phase variation stretches on the receiver side over n cycles, n being an integer greater than 1 and less than N. The device generates a single pulse for each symbol received suited to generate the leading edge of the pulse corresponding to the symbol considered after a constant duration from the moment the symbol considered starts; and generates the trailing edge of the pulse considered at a moment the phase shift corresponding to the symbol considered has to be measured. Conversion means generate an output signal with a voltage varying as a function of the duration of the pulse produced.

Abstract: A phase demodulator has a high frequency amplifier which amplifies a received signal modulated by phase, a voltage control oscillator which conducts oscillation operation in tune with the received signal amplified by the high frequency amplifier, a phase comparator which detects a phase difference between an output signal of the voltage control oscillator and a reference oscillation signal, and a demodulator which conducts demodulation process based on the phase difference.

Abstract: A digital baseband (DBB) radio frequency (RF) receiver used for receiving and processing a wireless communication signal. The DBB receiver includes a demodulator, first and second analog low pass filters (LPFs), first and second digital gain control circuits, and a digital time domain compensation module which removes group delay variation distortion, introduced by the first and second analog LPFs, from real and imaginary signal components of the communication signal.

Abstract: A system for, and method of recovering primary channel operation in a facsimile (fax) receiver and a fax machine that incorporates the system, the method or both. In one embodiment, the system includes: (1) a signal receiver that receives a signal containing first and second points located at first and second angles and (2) angle determination circuitry that determines an offset angle by which the signal has been rotated based on the first and second angles.

Abstract: The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the utmost speed of operation, all circuits including the phase locked loop, operate as differential circuits which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.

Abstract: In a sampling block 40a-1, an intermediate frequency signal RIFs is sampled at a frequency of the intermediate frequency signal RIFs multiplied by “1/(m+0.25)” or “1/(m+0.75)” (m: 0 or natural number), to generate signals having phase differences “0”, “?/2”, “?”, and “3?/2”. A polarity adjustment block 40a-2 matches a polarity of the signal having phase difference “?” with that of the signal having phase difference “0”. Further, it matches a polarity of the signal having phase difference “3?/2” with that of the signal having phase difference “?/2”. In a signal synthesis block 40a-3, the signal with phase difference “0” and the signal with phase difference “?” having phase difference “?” from each other are synthesized and held to be output as a demodulated signal PI. Further, the signal with phase difference “?/2” and the signal with phase difference “3?/2” having phase difference “?” from each other are synthesized and held to be output as a demodulated signal PQ.

Abstract: The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.

Abstract: A dual phase pulse modulation (DPPM) decoder circuit processes a DPPM signal, which is in the form of a series of high and low pulses whose pulse widths represent successive groups of M data bits, so as to recover data carried by the signal. Each of the 2M possible data values of an M-bit group corresponds to one of 2M distinct pulse widths. Circuit blocks determine the width of each pulse by piping the DPPM signal through a short delay chain and inputting the delayed outputs and the non-delayed signal into AND logic gates, whose outputs are used to clock flip-flop registers. The registers are reset to a known state at the start of each signal pulse and toggled to an opposite state if clocked. The registered outputs are interpreted by logic to obtain the corresponding M-bit groups.

Abstract: Disclosed is a phase-demodulation method for minimizing the phase error of a communication signal. The phase-demodulation method for demodulating a phase-demodulated communication signal using a digital phase-demodulation algorithm includes the steps of: adding one sampling to the digital phase-demodulation algorithm represented by an equation F k ? ( x ) = ? k = 0 k - 1 ? C k ? x k , where k is the number of sampling times and Ck is a complex constant; and, demodulating the phase-demodulated communication signal. Accordingly, the phase-demodulation method minimizes the phase error generated when a noise is propagated in phase space during a demodulation time of the phase-modulated communication signal, using a minimum number of sampling times and a minimum number of calculation times.

Abstract: Methods for predicting the power spectral density of modulated waveforms are based on symmetric and Hermitian forms of a matrix equation. These forms facilitate the use of a Fourier transform method of prediction. In one embodiment, these methods are applied to a particular class of constant-envelope waveforms known commonly as multi-h continuous phase modulation. Various expressions for the power spectral density are then provided as well as an expression for an upper bound. These expressions facilitate the design of waveforms for practical use.

Abstract: In embodiment, the present invention is directed to a PLL phase demodulator that utilizes feed-forward error correction. The feed-forward error correction may occur by calibrating an equalizer to possess transfer function that emulates the modulation response curve of the VCO of the PLL phase demodulator. In operation, the equalizer may receive the filtered and integrated version of the error signal produced by the phase detector of the PLL. The equalizer filters the received signal according to the calibrated transfer function. The output of the equalized is provided to a adder to combine the equalized signal with the error signal produced by the phase detector. A similar arrangement including a suitably calibrated equalizer may be utilized to address phase tracking error in a PLL frequency demodulator.

Abstract: A demodulator arrangement, suitable to demodulate data symbols modulated in accordance with a predefined constellation diagram and sent as part of information bursts (A1, B1, C1, D1, A2, B2, C2, D2) over a transmission medium with substantially stable attenuation characteristics, detects the amplitude of the data symbols in a coherent way and detects the phase of the data symbols in a differential way.

Abstract: A system for signal acquisition in a distance meter includes at least one photoelectric receiver that detects electromagnetic radiation that is high-frequency modulated via a modulation frequency and converts the same to high-frequency electrical signals (HF). A device is provided for transforming the high-frequency electrical signals (HF) supplied by the photoelectric receiver into low-frequency measuring signals (NF) that can be passed on to a signal-processing unit mounted downstream of the device. The device for transforming the high-frequency electrical signals (HF) supplied by the photoelectric receiver into low-frequency measuring signals (NF) can include at least one switch whose switching frequency is controlled by a control frequency (F) whose frequency is higher or lower than the modulation frequency by the amount of the low-frequency measuring signal.

Abstract: A feed-forward symbol synchronizer (200, FIG. 2) samples symbols transmitted within one or more packets that form a burst of radio frequency (RF) energy. The symbol samples (209) are delayed in a data delay buffer (214) while a phase estimate (212) is generated for each packet. A resampler (218) resamples the delayed symbol samples based on the phase estimate, resulting in resampled data (228) that includes one sample per symbol. The resampled data is clocked into a dual-port RAM (230) using a resampling clock that is also based on the phase estimate. The resampled data is then clocked out of the dual-port RAM and into a demodulator (238) using the receiver's symbol clock (232). Also described are methods of operating the feed-forward symbol synchronizer.

Abstract: Disclosed is a phase-demodulation method for minimizing the phase error of a communication signal.

Abstract: A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit (4), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180°, which are included in a carrier reproduction phase difference detecting circuit (8), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit (10) so that the phase obtained from the signal point position coincides with the phase convergence point.

Abstract: A method and a circuit for demodulating a signal transmitted by an electromagnetic transponder, comprising a sensor of a variable which is a function of the load formed by the transponder on an oscillating circuit, a phase demodulator and an amplitude demodulator at least functionally in parallel and receiving a signal coming from said sensor, a summer of the results provided by said demodulators, and a delay element in series with a first one of said demodulators, to compensate for a possible propagation time difference therebetween.

Abstract: An angle demodulator in which an FM modulated wave is converted into an IF signal (SI) in the form of digital so as the signal is supplied to a Hilbert transformer (81) and to an outer product calculation section (82). The Hilbert transformer (81) allows the phase of the IF signal (SI) to shift ninety degrees and supplied it to the outer product calculation section (82). An integrator (84) calculates a phase of a cosine wave of an angular frequency that a frequency control unit (83) designates. A phase converter (85) calculates the cosine wave and an instantaneous value of a signal in which the cosine wave shifts ninety degrees out of phase so as to supply the value to the outer product calculation section (82). The outer product calculation section (82) supplies to the frequency control unit (83) an outer product of a vector including a value of the IF signal and of a signal from the Hilbert transformer (81) and a vector including a value supplied from the phase converter (85).

Abstract: The invention discloses a phase detection method including a quadrant determining procedure, a first comparison procedure, a second comparison procedure, a coordinate transforming procedure, and a phase computing procedure. A first and a second phase approximate values are obtained in the quadrant determining procedure and the first comparison procedure. A third phase approximate value is obtained in the second comparison procedure and the coordinate transforming procedure. A total phase is computed in the phase computing procedure. Using this method, we does not need to consult look-up tables to determine the phase, thus saving a lot of memory space. The invention also provides a phase detection device.