Abstract: Techniques are described whereby noise estimates from individual finger processors are compared using a noise estimator, and a finger merge condition declared on the basis of such comparison. In one embodiment, when noise estimates from two or more finger processors is identical or nearly identical, finger merge is presumed such that noise estimates from merged fingers are blocked from forming a combined noise estimate. Furthermore, in another scheme a correcting factor is introduced to account for the correlation between noise samples from merged fingers. In a further embodiment, a computationally effective procedure to perform comparisons between the noise estimates from individual fingers is implemented by sorting noise estimates according to respective magnitudes to create a sort list. In one implementation, only samples that are neighbors in the sorted list are then compared.

Abstract: In accordance with an embodiment of the invention there is provided a sample and hold demodulator circuit (200) for use in an automotive immobilizer to recover modulation information from a received modulated carrier signal (VRD). Sample and hold circuitry samples signals to recover the modulation information therein, and control circuitry (214) is coupled to the sample and hold circuitry for controlling operation thereof. The control circuitry includes shift register circuitry (252) for receiving a second received signal having a same frequency as a carrier frequency of the received modulated carrier signal and for producing at its outputs signals (SAMPLE, SAMPLE2, LATCH) for controlling operation of the sample and hold circuitry. The sample and hold demodulator circuit provides a single IC solution, allowing amplitude and phase demodulation to be performed with a single sample and hold circuit.

Abstract: A phase demodulator is used for measuring a phase difference between a phase-modulated test signal and a phase-modulated reference signal having fixed carrier frequencies. The phase demodulator includes an amplitude control device for adjusting amplitudes of the test and reference signals. A differential amplifier receives amplitude-adjusted test and reference signals from the amplitude control device, obtains an intensity difference between the amplitude-adjusted test and reference signals, and amplifies the intensity difference to generate an amplitude-modulated output. An amplitude demodulator demodulates the amplitude-modulated output to obtain an output that is related to the phase difference.

Abstract: A communication system and method for continuous phase modulation providing for transmission of a phase-modulated carrier having a phaseform representative of concurrently transmitted symbols. The phaseform of the phase-modulated signal is a sum of shift bi-orthogonal functions, each term in that sum being weighted by one of the overlapping symbols. The communication system and method provide full-response demodulation for the recovery of a particular symbol from among the concurrently transmitted symbols by selecting a receiving filter function shift bi-orthogonal to the transmitter filter function corresponding to the particular symbol. The communication system and method then provide for nulling, by integration over a time interval during which the particular symbol is transmitted, those transmitter filter functions that do not correspond to the particular symbol. This results in the separation of the particular symbol from the other concurrently transmitted symbols.

Abstract: A reference generator includes a memory that stores reference data which, when clocked out of the memory, produces an ATSC compliant VSB reference signal substantially free of sub-harmonics of the clock signal. A digital-to-analog converter converts the clocked out reference data to an analog signal. The analog signal may be at low IF. An up converter is arranged to upconvert the output of the digital-to-analog converter to an RF reference signal. The RF reference signal can be used, for example, to calibrate a VSB demodulator.

Abstract: Received signals are digitized by a comparator, and sampled by regenerated clock signals synchronized to a carrier. Biphase symbol data are demodulated based on the sampling data. A biphase decoder circuit performs subtraction of the biphase symbol data to be paired. The subtraction result is compared with threshold values by data judgment circuitry which then judges inversion of the biphase signals to be paired. An RDS-ID detector circuit detects inversion of RDS signals by detection of either continuity or a ratio of signals received for a certain length period. Alternatively, RDS signals are detected by stability of output from the pair judgment circuit to detect a combination of biphase symbols.

Abstract: A method and apparatus for decoding a phase encoded data signal utilizes windowed data which is transformed into real and imaginary frequency components thereof. The real and imaginary frequency components are converted into phase and magnitude information. The magnitude information is used to calculate a threshold based upon a signal-to-noise ratio, and the phase of the data signal is corrected by identifying and sorting magnitude peaks. The data signal is differentially demodulated and the demodulated data is then multiplied by a correlation sequence so as to facilitate its being converted into a binary number.

Abstract: A reference signal source produces a substantially distortion free reference signal which is supplied to a demodulator that is arranged to demodulate the substantially distortion free reference signal. A calibration filter and an equalizer are included downstream of the demodulator. A controller sets the calibration filter to initially pass the reference signal to the equalizer without substantial change to the reference signal. The controller subsequently calibrates the calibration filter in accordance with the demodulator caused distortion reduced by the equalizer.

Abstract: A decoder circuit for decoding phase-encoded digital data signals includes a timing circuit and a signal viewer circuit coupled to logic circuitry. The timing circuit uses an edge of a received phase-encoded digital data signal to indicate when to sample data from the received phase-encoded digital data signal in the signal viewer circuit. The logic circuitry determines the value encoded in the phase-encoded digital data signal based on the sampled data.

Abstract: The present invention, generally speaking, provides a quadrature-free RF receiver for directly receiving RF signals such as angle modulated signals. Various embodiments of the receiver use a digital phase detector together with well-known RF components: a limiter, an envelope detector, a slow Automatic Gain Control (AGC) circuit, a fast AGC circuit, etc. Demodulation may be non-coherent or coherent. The approach followed is to handle the underlying non-linearities of the demodulation process within the circuitry itself, rather than relegating the non-linearities to a separate signal processing step as in the prior art. No I and Q signals are obtained, and no coordinate conversions are performed, offering the potential for space savings, increased accuracy, and especially power savings. Depending on the nature of the modulation employed, either circuitry relating to amplitude recovery or circuitry relating to phase recovery may be dispensed with.

Abstract: A method, and related apparatus, for coherently demodulating phase-modulated data which is coherently transmitted (i.e., without the use of differential encoding of the data) on Rician fading channels. The method uses phase unwrapping and phase interpolation, in conjunction with block phase estimation, to achieve a performance comparable with coherent detection of coherently transmitted data while reducing processing requirements.

Abstract: A four-stage phase demodulation low frequency wireless mouse device is disclosed, improving a shortcoming of a conventional low frequency wireless mouse device which can not effectively overcome the signal interference and prevent the misoperations by only using I and Q axes or a quadrature demodulation method and the present invention installs a phase demodulation circuit on a receiving end for generating four sets of phase signals each having a phase of 0.degree., 90.degree., 180.degree. and 270.degree. respectively. Then, each of the quadrature signals is sent into a microprocessor for processing to become a computer interfacing signal after passing through a low pass filter, a detecting circuit and a voltage comparator respectively so that the signal interference is effectively eliminated, the misoperation is obviated and the reaction speed of the signal is enhanced due to a low error rate.

Abstract: Apparatus and method for estimating the angle-modulation imposed on a transmitted Radio Frequency (RF) or Intermediate Frequency (IF) carrier. The method estimates angle-modulation when communications channels add distortions such as noise to transmitted signals. The system provides reconstituted frequency modulation from a feedforward demodulator. The goal is to reduce the modulation index of a desired signal and to employ a narrower band-pass filter that passes this signal while rejecting the distortion that accompanies it. A plurality of stages, 1 through M, exist within the system. Stages 2 through M contain the same components, although filter coefficients and alignment delays may differ from stage to stage. Stage 1 of the demodulator differs slightly from the remaining stages, since the only input required by Stage 1 is a complex envelope signal that contains both the desired signal and the distortion added by the channel.

Abstract: An arrangement to realize the functions of a radio card system in which power is transmitted to perform data communication. According to such arrangement, a delay line and a clock regenerating circuit such as PLL circuit which are previously necessary for demodulation by PSK are not necessary, and thus functions of data communication are realized by minimum hardware construction, size, cost and power consumption. Further, in a data communication system in which electric power transmission using a signal of a frequency fp and digital data communication using a carrier wave of a frequency fs are performed by radio, fs and fp are in the relationship of fs=fp/N (where N is an integer) and a phase shift P when the phase of the carrier wave is modulated by PSK is (M.times.360.degree.)/N (where M, N are integers and P is preferably not equal to 180.degree.).

Abstract: A digital implementation for a carrier detector. The detector determines if the carrier frequency at any instant is within a predetermined frequency band. The detector further determines if the detected frequency remains within the predetermined frequency band for a predetermined period of time. The detector also provides an indication that there has not been any loss of carrier for another predetermined period of time.

Abstract: A QPSK demodulator that is smaller in size and lower in cost by restricting a storage capacity needed for a TAN.sup.-1 ROM to a minimum. Values of I and Q channel base band signals obtained by converting and quantizing a received signal are approximated to a nearest one of values on (2.sup.N-3 +1) segment lines represented by Q=(n/2.sup.N-3)I, where n=0, 1, . . . , 2.sup.N-3, with a phase accuracy of positive N bits. Data corresponding to the approximated segment line is previously stored in a TAN.sup.-1 ROM as phase arithmetic data. An address decoder converts each base band signal into an address. An arithmetic circuit obtains phase data, for obtaining a QPSK demodulated signal, by performing a predetermined arithmetic operation, which is commensurate with the size of I and Q channel base band signals, on phase arithmetic data stored in the TAN.sup.-1 ROM in association with the converted address.

Abstract: A device and a method correct deviation when transferring an information-carrying signal between a transmitter and a receiver. The transmitter can transmit with a plurality of frequencies generated by a voltage-controlled oscillator used for phase demodulation. The receiver demodulates the modulated information-carrying signal. A detector measures the deviation of the modulated information-carrying signal via the information-carrying signal demodulated in the receiver. The frequencies of the demodulated information-carrying signal can be adjusted so that the correct deviation is obtained, and a correct phase demodulation can be carried out.

Abstract: In a Viterbi decoder and a Viterbi decoding method, a modulating method and a phase of a carrier wave, employed in a transmitter apparatus can be automatically followed up in a receiver apparatus.

Abstract: A method and apparatus for improved mobile radio telecommunications employs the transmission of a pilot reference signal within the coherence band of the modulated carrier wave. The receiver in this system uses instantaneous phase estimation techniques of the pilot and carrier received waveforms to provide immunity from phase distortion introduced by the channel.

Abstract: A cancellation circuit is provided where one demodulator circuit provides a demodulated output having interference voltage owing to interference between carrier signals, between a carrier signal and noise, or a combination of both. Cancellation of interference is particularly directed to narrowband applications. Because the interference is within the band of the desired signal, it cannot be filtered without materially harming the quality of the message. A separation circuit is provided for removing the interference voltage component from the message signal. Outputs are provided to a second demodulator for creating a phase-shifted near replica signal of the dominant carrier signal without an interference voltage component. The separation circuit includes an isolation circuit. Further described are applications of the cancellation circuit, including demultiplexing a power-multiplexed signal, demodulation of two or more carrier signals, and removal of interference from modulated and unmodulated carrier signals.

Abstract: Method and apparatus for improving an estimate of a message being carried by a frequency modulated dominant carrier in the presence of co-channel interference from a subdominant carrier. An envelope detector provides an envelope signal E(t). A frequency demodulator provides a demodulated frequency signal F(t). In one embodiment, a comparator compares the envelope signal to a threshold voltage V.sub.T. A switch is operated when the envelope signal is less than V.sub.T. The signal F applied to the switch is held by a holding circuit while the switch is open. Interpolation and lowpass filtering improve the quality of the output signal. In another embodiment of the invention, the frequency demodulated signal F is summed with an unfiltered signal to provide a first summed signal. The first summed signal is summed with an unfiltered signal to provide a second summed signal which is an estimate of the message on a co-channel subdominant carrier.

Abstract: Information often modulates an underlying carrier signal, thereby producing a modulated information signal 70. This same carrier signal is required, with a few modifications, to demodulate the modulated information signal. This required signal is called the demodulator reference signal. It must be complex, that is, it must contain separate in-phase and quadrature outputs. A degraded version 10 of this signal is often available with the correct frequency, but with the wrong phase and amplitude, and with a direct current (dc) offset. The present invention 68 produces a digital demodulator reference signal 38, 46 from the degraded signal 10. It eliminates dc offset with a dc blocker 18, adjusts amplitude with a scaler 14, adjusts phase with a first Hilbert transformer 20, multipliers 26 and 28 and summer 34, and produces in-phase and quadrature outputs with a second Hilbert transformer 36 cascaded with the first.

Abstract: A phase lock loop (PLL) circuit and method in which a PLL circuit locks on a variable input phase by providing an instantaneous phase value of a signal from an oscillator at periodic intervals, and by providing phase corrective signals to the oscillator at the same periodic intervals by comparing an instantaneous value of the variable phase to the corresponding instantaneous value of the oscillator signal phase, the phase corrective signals adjusting the phase of the oscillator signal to the predetermined phase. The PLL circuit may also lock on a predetermined frequency by providing frequency corrective signals until a difference between the predetermined frequency and the frequency of oscillator signal is smaller than a predetermined threshold.

Abstract: In a synchronous detector a first local signal from a first local signal generator is frequency divided by a frequency divider to obtain a second local signal. The polarity of the first local signal is inverted by a polarity inverter in synchronization with the second local signal, and the output of the polarity inverter is used to synchronously detect the output of an AC amplifier by a first synchronous detector. The synchronous detected output is synchronously detected by the second local signal in a second synchronous detector, the detected output of which is averaged by a filter.

Abstract: An FM or PM signal is demodulated so that the cycle time of the modulated input signal is measured using a time-to-digital converter comprising a counter that uses a moderate clock frequency as a reference clock, a digital delay line interpolator and a control circuitry. The counter is used for rough digitization and the delay line for interpolating the moment of zero-crossing inside a clock cycle. Total delay of the delay line, i.e., the range of time intervals the interpolator is able to measure, is actively kept equal to the cycle time of the reference clock. When the number of delay elements in the delay line is a power of two, the result of the delay line interpolator may be used directly as the least significant bits of the measurement.

Abstract: The order statistic signal processor obtains continuing estimates of amplitude, phase, or frequency of an input signal based on order statistics. By way of definition, the P'th order statistic for a set of samples from a continuously distributed process is the P'th largest of the samples. Where a signal parameter fluctuates with time as a result of contamination by noise and interference and where the noise fluctuation rate is much greater than the rate at which changes in a signal parameter occur, an order statistic associated with a set of signal parameter samples can serve as an estimate of the signal parameter. The order statistic signal processor is based on an iterative process whereby the prior estimate of a signal parameter, i.e. amplitude or phase, is subtracted from each of a plurality of signal parameter samples obtained over a period of time. The differences are converted to quantities of fixed magnitude with signs corresponding to the differences.

Abstract: An angle modulation detector which prevents a demodulated output from being influenced by fluctuations in the amplitudes of signals generated from angle-modulated signal sources such as a phase-modulated signal and a frequency-modulated signal, even if the amplitude of a driving voltage applied to a connection between the bases of a pair of transistors constituting a phase detecting device is made larger in order to enhance the demodulation sensitivity and reduce noise produced during demodulation.

Abstract: A digital demodulator for demodulating baseband signals in a radio receiver. The demodulator includes a digital signal processing module for forming a mathematical series adapted for generating demodulation functions. The selection of coefficients for this series is controlled to provide specific demodulation functions as required for the demodulation of different kinds of signals such as amplitude modulated or angle modulated signals using one computational block or element. When demodulating amplitude modulated signals, the coefficients used in the mathematical series provide an approximation to the square root function. When demodulating phase or frequency modulated signals, the coefficients used provide an approximation to the arctangent function.

Abstract: Parallel low-level and high-level quadrature demodulators (60,62) are provided, each including high speed analog-to-digital converters (82,84) with a nominal number of bits. A signal limiter (56) upstream of the low-level demodulator (60) limits the amplitude of an input analog signal (IF IN) to a value corresponding to a predetermined signal level. An attenuator (58) upstream of the high-level demodulator (62) attenuates the input signal (IF IN) by a predetermined factor, so that the signal level into the high-level demodulator (62) is correspondingly lower than the signal level into the low-level demodulator (60). When the amplitude of the input signal (IF IN) is below a predetermined value, a digital switching and scaling unit (72) selects the output signals from the low-level demodulator (60) and extends the digital output to a larger number of bits.

Abstract: In a demodulator for demodulating into a demodulated signal a quadrature phase modulated signal having a large varying amplitude caused by various radio transmission link conditions, a preprocessing circuit (21) logarithmically processes the envelope to produce a first preprocessed signal having a logarithmically compressed and digitized amplitude and limits the amplitude to multiple values to produce a second preprocessed signal. A phase detecting circuit (22) detects a phase difference between a reference signal having a reference frequency and the second preprocessed signal and produces a phase difference signal representative of the phase difference. A processing circuit (23) processes the first preprocessed signal and the phase difference signal to produce first and second processed signals collectively as the demodulated signal.

Abstract: The continuous phase angular demodulation method disclosed digitally processes the signal in baseband after having over-sampled it with reference to the bit period. The processing consists in routinely demodulating sub-sets of differential phases at the bit period T.sub.b shifted with respect to one another by fractions T.sub.b /q of this period, in correcting them, a priori, by the phase deviations associated with a set of pre-defined d frequency drifts and in computing, for the d.q sets thus obtained, a noise criterion. The set of demodulated bits chosen is the one that reduces this noise criterion to the minimum. The set of bits then enables computation of the phase variation emitted and, using this variation and the measured variation, the real frequency drift. Another demodulation taking this drift into account is done for the q sets of initial differential stages and the set minimizing the noise criterion is then chosen and fixes the synchronization bit by the sampling instants associated with it.

Abstract: A sampled data FM demodulator samples the FM signal at intervals of (2n.pi.+.pi./2) radians relative to the FM carrier. Pairs of samples S.sub.n and S.sub.n+1 are square and multiplied together to generate sample values S.sub.n.sup.2, S.sub.n+1.sup.2 and S.sub.n S.sub.n+1. These sample values are lowpass filtered in a filter having a cutoff frequency which substantially attentuates at least the second harmonic of the FM carrier. The low pass filtered samples are then combined according to the relation S.sub.n S.sub.n+1 /.sqroot.S.sub.n.sup.2 S.sub.n+1.sup.2 to generate demodulated output samples.

Abstract: A low noise floor phase detector is designed with a transmission line coupler to take advantage of the low noise characteristics of such couplers and their improved operational characteristics relative to a transformer. The preferred detector circuitry also utilizes amplitude detectors that include signal terminating means to operate the diodes at a conduction angle for maximum signal to noise ratio and effective impedance matching between the circuit components.

Abstract: A digital implementation of an analog phase detector is illustrated, wherein the novel aspect is the use of a low speed clock, which is passed through a delay line to provide ten different phases of clock signal. The circuitry is used to generate digital numbers on a basis similar to the pulses in an analog equivalent, which numbers are summed to provide a phase detected output.

Abstract: A demodulator mechanism which uses estimates of the in-phase and quadrature-phase components of differential phase modulated carrier signals for performing a coherent demodulation of these signals is described. The instantaneous estimates, obtained from an estimator circuit, are fed into a differential carrier recovery circuit, which provides for a feedback of ideal sine and cosine components, and combined with the instantaneous estimates for incrementally decreasing a phase error signal generated in a computational circuit. By thus incrementally decreasing the phase error signal, an ideal phase angle is eventually obtained, thereby providing for coherent demodulated output components of the input carrier signals.

Abstract: A multichannel processor for signals modulated onto a common IF frequency includes first and second analog-to-digital converters (ADC) for first and second channels, respectively. Each ADC receives a 4XIF frequency clock for producing digital samples, which are applied to a pair of gates for alternately coupling the digital signal to two signal paths. Each signal path alternately negates and does not negate the signals passing therethrough, thereby generating baseband I and Q signals for that channel. Since each channel has a separate ADC, there may be amplitude and temporal error between the channels. One of the channels is selected as a reference, and uses a pair of interpolators to produce samples representing the I and Q signal values at a common time between clock pulses. The other channels include controllable interpolators which are adjusted so that their I, Q common times correspond to that of the reference channel.