Abstract: Embodiments of communications devices and methods for operating a communications device are described. In an embodiment, a communications device includes a complex multiplier configured to multiply a first input complex signal with a second input complex signal to generate an output complex signal, an amplifier configured to amplify an imaginary part of the output complex signal to generate an amplification result, a delay element configured to delay a rotation angle signal that is related to the second input complex signal, and a subtractor configured to subtract the amplification result from the delayed rotation angle signal to generate the rotation angle signal. Other embodiments are also described.

Abstract: An output driver with programmable single-ended and differential outputs includes a first switch, a first output attenuator, and a programmable attenuator. The first switch is coupled in a shunt configuration to a first path of a differential output of a first amplifier. The first output attenuator is included in the first path and is coupled to the first switch in accordance with the shunt configuration. The programmable attenuator is included in a second path of the differential output of the first amplifier.

Abstract: A method is provided, performed by a wearable computing device comprising at least one bio-signal measuring sensor, the at least one bio-signal measuring sensor including at least one brainwave sensor, comprising: acquiring at least one bio-signal measurement from a user using the at least one bio-signal measuring sensor, the at least one bio-signal measurement comprising at least one brainwave state measurement; processing the at least one bio-signal measurement, including at least the at least one brainwave state measurement, in accordance with a profile associated with the user; determining a correspondence between the processed at least one bio-signal measurement and at least one predefined device control action; and in accordance with the correspondence determination, controlling operation of at least one component of the wearable computing device, such as modifying content displayed on a display of the wearable computing device.

Abstract: An A/D conversion device includes: a level shifter circuit configured to level-shift an analog voltage of an input voltage signal to generate a conversion signal; an A/D converter configured to A/D-convert a voltage of the conversion signal supplied from the level shifter circuit. The level shifter circuit subtracts an instantaneous voltage value of the input voltage signal from a reference voltage so as to output a signal value as the conversion signal.

Abstract: A method of detecting a communication mode is provided to rapidly detect which one of near field communication (NFC) protocols includes a communication frame pattern of data provided to a receiving device. The method includes receiving a communication frame pattern of data transmitted from an NFC initiator after synchronizing the communication frame pattern with a predetermined sampling clock. The detection of the communication mode may be done by analyzing a start pattern out of the communication frame pattern. Since a communication mode is rapidly detected and data is automatically received without performing an additional operation to set the communication mode, operation performance of a receiving device is improved.

Abstract: A transmitter includes an encoding module, an adaptive hierarchical signal mapping module and a transceiver module. The encoding module receives an input signal and encodes the input signal. The input signal includes data to be transmitted. The adaptive hierarchical signal mapping module modulates the encoded signal according to one or more hierarchical level distance ratios to obtain modulated symbols. The hierarchical level distance ratio defines distances between the modulated symbols. The transceiver module generates a radio frequency signal according to the modulated symbols and transmits the radio frequency signal to an air interface.

Abstract: In a receiver circuit, an analog signal processor frequency-converts an input high frequency signal into a baseband signal, and performs low pass filtering at a cutoff frequency below a desired-wave band. An ADC converts an output of the analog signal processor into a digital signal. A digital signal processor compensates an output of the ADC for a signal component in the desired-wave band which has been attenuated by the filtering operation of the analog signal processor.

Abstract: The envelope detector for detecting an envelope of a digital modulation signal in accordance with an embodiment of the present invention, includes: a mixer configured to receive the digital modulation signal and output a square signal squaring the digital modulation signal when being applied with bias voltage; a bias voltage applying unit configured to apply the bias voltage to the mixer; and a DC blocking capacitor configured to be connected to the mixer to block DC component included in the square signal. In accordance with the embodiment of the present invention, it is possible to provide the envelope detector having the simple structure while having the good receiving sensitivity and the wide dynamic range characteristics and detect the envelope of the modulated signal without transmitting the carrier signal in the transmitter and generating the separate signal in the receiver, thereby saving the costs consumed to implement the transceiver.

Abstract: The present invention relates to a demodulator for simultaneous multi-node receiving and a method therof; and, more particularly, a demodulator in a wireless communication system for receiving signals from multi nodes simultaneously and a method thereof. In accordance with the aspect of the present invention, there is provided a demodulator for simultaneous multi-node receiving which comprises: a clock generator for generating a pair of CW signals and a pair of demodulating modules, wherein the demodulating modules comprise a mixer for multiplying received signals and one of the CW signals, an integrator for integrating multiplied signal and data operating unit for calculating variation result of integrated signal at every certain symbol duration and deciding output data in accordance with the variation result.

Abstract: A quadrature demodulation circuit includes: first to fourth mixers to receive a modulation signal; a phase shifter to supply to the first and third mixers a first local frequency signal, to supply to the second mixer a second local frequency signal having a designated phase difference relative to the first local frequency signal, and to supply to the fourth mixer a third local frequency signal that is an inverse in phase to the second local frequency signal; a first adder to add a signal output from the first mixer and a signal output from the second mixer and to output a first demodulation signal; and a second adder to add a signal output from the third mixer and a signal output from the fourth mixer and to output a second demodulation signal.

Abstract: A radio receiver including a reception processing system that uses discrete-time frequency conversion to acquire a signal having a sampling rate corresponding to a local frequency, wherein the reception characteristic is improved when the reception processing system is applied to a system having a wide reception channel band. The radio receiver comprises an A/D converting part that quantizes a discrete-time analog signal to a digital value to output a received digital signal; a channel selection filtering part that uses a tap coefficient value to perform a digital filtering process of the received digital signal; and a frequency response characteristic correcting part that generates the tap coefficient in accordance with the sampling rate.

Abstract: A quadrature modulator and a method of calibrating same by applying a first test tone signal to an in-phase modulation branch input of the modulator and a ninety degree phase-shifted version of the first test tone signal to a quadrature modulation branch input of the modulator. The carrier leakage level in an output signal of the modulator is measured and in response base band dc offset voltages are adjusted to minimize the carrier leakage. A second test tone signal is applied to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input. The level of an undesired upper sideband frequency component in the output signal is measured and in response base band gains the in-phase and quadrature modulation branches and a local oscillator phase error are adjusted to minimize the undesired side band.

Abstract: The invention relates to a digital acquisition device for an amplitude modulation signal of a carrier. The acquisition device digitally acquires a useful signal. The useful signal modulates the amplitude of a carrier HF1 which has a frequency and a phase that are known. A modulation of the amplitude of the carrier by the useful signals forms a signal to be processed. According to the invention, the device has a summing device for creating an aggregate signal from a sum of the signal to be processed and a neutralizing signal. The neutralizing signal is a product of the carrier HF1 and of a neutralizing coefficient that can evolve over time, produced by a controlled-gain amplifier device. A load amplifier device amplifies the aggregate signal and produces an amplified aggregate signal. A quadrant comparison device QC is provided for the signal of the amplified aggregate signal and the sign of the carrier which delivers a comparison signal. A sampling device produces a bitstream from the comparison signal.

Abstract: A software defined radio detects an amplitude modulated (AM) signal contained within a received signal. This detection involves first receiving a radio frequency (RF) signal that contains the AM signal modulated about a carrier frequency (fc). The RF signal is downconverted using a first local oscillator having a frequency flo. An in-phase (I) channel signal and a quadrature (Q) channel signal are produced. From the I-channel signal, a relationship between the carrier frequency and the frequency of the local oscillator is determined with a frequency detector. The downconverted carrier signal of the I-channel signal is used to create a second set of signals with proper phases and frequencies that can be used to rotate the I-channel and Q-channel signals to account for differences between the downconverted fc and DC.

Abstract: Because of the natural ability to reject clock jitter, the SRC circuits include an internal oscillator to provide an operating clock signal. The internal oscillator can be operated independently of any external frequency control signal, including input and output frame clocks. The internal oscillator can be implemented as a relatively low-cost fixed frequency oscillator. The use of a relatively low precision, inexpensive internal oscillator in an SRC circuit reduces the overall cost of SRC circuits while providing acceptable performance. Accordingly, reducing costs of SRC circuits also has a positive cost/benefit affect on the digital signal processing systems that use SRC circuits.

Abstract: Devices (1) for exchanging ultra wide band signals comprise frequency translating stages (20,30) for frequency translating signals and oscillating stages (40) for supplying main inphase/quadrature oscillation signals to the frequency translating stages (20,30). By providing the oscillating stages (40) with polyphase filters (43,44) for reducing harmonics in oscillation signals, the main oscillation signals will be sufficiently clean. The oscillating stages (40) comprise mixers (46) for converting first inphase/quadrature oscillation signals and second inphase/quadrature oscillation signals into the main oscillation signals. The polyphase filters (43,44) may be located before and after the mixers (46). Frequency selectors (45) replace prior art multiplexers located after the mixers (46).

Abstract: To improve the quality of the demodulated signal without altering the form in which an AM radio wave is transmitted, the received amplitude-modulated signal is converted to a single-sideband signal, and the information signal demodulated from the phase term of this converted single-sideband signal.

Abstract: A method and a circuit for demodulating a signal transmitted by an electromagnetic transponder, including a sensor of a variable which is a function of the load formed by the transponder on an oscillating circuit, a phase demodulator and an amplitude demodulator at least functionally in parallel and receiving a signal coming from said sensor, a summer of the results provided by the demodulators, and a delay element in series with a first one of said demodulators, to compensate for a possible propagation time difference therebetween.

Abstract: Amplitude detection of a baseband electrical signal. The detection may be performed by performing full wave rectification on both an in-phase portion of the electrical signal, as on a quadrature-phase portion of the electrical signal. The output signal may be generated by summing the rectified in-phases signal and the rectified quadrature-phase signal. The peak amplitude of the output signal may then be used to determine the amplitude of the original baseband signal.

Abstract: A wireless communication apparatus prevents desensitization in a line signal frequency caused by clock signal harmonic. The wireless communication apparatus is provided with a receiver/demodulator for receiving a line signal of a predetermined frequency and for demodulating the line signal, a control section decoding the demodulated line signal using an operation clock signal, and a clock signal generating circuit supplying a clock signal. The control section controls the clock signal generating circuit to change a frequency of the clock signal in response to the line signal frequency, therefore, harmonic of the clock signal do not enter into a desensitization range corresponding to the line signal frequency.

Abstract: A digital communication system and method is provided for increasing bit-rates while maintaining the reliability of transmitted digital information and avoiding increased power demands. The communication system includes a transmitter that modulates one or more bits onto a carrier signal to generate and transmit a first transmission signal during the first part of a pulse time TB, receives an additional bit, and based on the value of the additional bit, either transmits the first transmission signal again during the second part of the pulse time TB or transmits a second transmission signal during the second part of the pulse time TB.

Abstract: An electromagnetic transponder including an oscillating circuit adapted to extracting from a radiating field a high-frequency amplitude-modulated signal, circuitry for extracting from said high-frequency signal an approximately D.C. supply voltage, a demodulator of data carried by the high-frequency signal, and circuitry for separately regulating the supply voltage and a useful voltage carrying the data.

Abstract: Integrated circuit layout for LF signal acquisition in the case of contactless data transmission Known circuit layouts for LF signal acquisition only provide for a very short communication distance between transponder and base unit, and consist of several ICs that need to be assembled. Using bipolar or MOS circuit layouts where the LF signal acquisition for the AM demodulator is effected on at least one of the two H bridge circuit branches. This increases system sensitivity and thus the communication distance between transponder and base unit. Due to the reduced voltage strength requirements with regard to the AM demodulator, it will become easy to integrate this circuit component jointly with the H bridge into an IC.

Abstract: A flexible sliding correlator for use in a spread spectrum receiver divides baseband signal samples into different groups, associates each group with a different section of a spreading code, and combines ones of the signal samples with corresponding values in the spreading code section. The groupings and spreading code sections can be changed during operation of the receiver to maximize performance of the receiver under different or changing conditions. In addition, the sample and spreading code value combinations can be further combined in different ways, and the further combinations can be changed during operation of the receiver. According to another aspect of the invention, the baseband signal can be sampled either uniformly or non-uniformly. The phase and frequency of the baseband sampling can be adjusted during operation of the receiver so that samples are taken very close to the optimum sampling position, at the peak of a chip waveform in the baseband signal.

Abstract: An amplitude and phase demodulator circuit for signals with very low modulation index, including: amplifier circuitry adapted to amplify a modulated signal coming from a transmitter, the modulated signal being composed by a carrier and by a modulating component, circuitry adapted to cancel said carrier from said modulated signal; the circuitry adapted to cancel the carrier receiving in input the output signal of the amplifier circuitry and a sync signal coming from the transmitter, the output signal of the amplifier circuitry being delivered to receiver circuitry.

Abstract: A PHS relay station demodulates a digital signal from a received radio-frequency signal by use of a reproduction clock produced from the digital signal. The relay station has an oscillator which generates a clock and a variable-ratio frequency divider for the clock outputted from the oscillator. A bit clock is produced from the output of the divider. A signal processor processes the digital signal by use of the bit clock. A detector detects a specific code in the digital signal in synchronism with the bit clock. The length of time that passes after the specific code detection signal is generated until the reproduction clock changes its level is detected as the phase deviation between the reproduction clock and the bit clock. The phase deviation is eliminated by temporarily changing the frequency division ratio of the divider in accordance with the amount of the deviation.

Abstract: A digital implementation for a carrier detector. The detector determines if the carrier frequency at any instant is within a predetermined frequency band. The detector further determines if the detected frequency remains within the predetermined frequency band for a predetermined period of time. The detector also provides an indication that there has not been any loss of carrier for another predetermined period of time.

Abstract: A complex baseband signal as long as one period of PN signal is divided into three sequences. The three partial signals are input to three correlators which then calculate the correlations between the three partial signals and three partial PN signals. The squares of the absolute values of outputs from the three partial correlators are summed and the peak of the resultant summed signal is detected, thereby performing initial acquisition and tracking of synchronization of PN signal. Outputs from the three partial correlators are added together by an adder for generating a correlation signal used for data demodulation. Since partial correlation signals output from three partial correlators have a phase difference corresponding to a frequency offset, and error signal corresponding to the frequency offset is provided by performing complex conjugate product operations on the partial correlation signals.

Abstract: A method and apparatus utilizing the techniques of frequency shifting and filtering for converting an input signal having a desired signal at intermediate frequency and an undesired DC offset to a baseband frequency signal in which the undesired DC offset is eliminated. The apparatus includes a first multiplier for multiplying the input signal by a signal having substantially the same intermediate frequency plus an offset frequency (.DELTA.f) to produce a first output signal wherein the desired signal is shifted in frequency to the offset frequency (.DELTA.f) and the undesired DC offset is unaffected. The apparatus also includes a second multiplier coupled to the first multiplier for multiplying the first output signal by a signal having substantially the same offset frequency (.DELTA.f) to produce a second output signal having the desired signal shifted to baseband frequency and the undesired DC offset shifted in frequency to the offset frequency .DELTA.f.

Abstract: A clock recovery circuit capable of outputting decision point data without causing any slip of a recovered clock in the case of operation in a continuous mode in a demodulator in which received signals are sampled by a fixed frequency clock to obtain the recovered clock and symbol data are demodulated by using this recovered clock. A shift register stores digital received signals obtained by an A/D conversion of quasi-coherent detection received signals, and a clock phase estimator calculates an estimated phase difference between an output value of a phase generator operated by the fixed frequency clock and a symbol clock of the received signals and outputs timing information and phase information of a decision point for discriminating the data of the received signals. An interpolator inputs the output signal of the clock phase estimator, takes in the digital received signals from the shift register and calculates decision point data by interpolation to output the same.

Abstract: An I/Q-modulator or I/Q demodulator circuit in which the modulating signals (2, 3) are input through the output phase transfer branches of the circuit. In relation to the RF-characteristics, a series resistor (16) and a series inductance (20) in the phase transfer circuits are grounded with small capacitors (23, 25). A capacitor (17) having a high impedance at the modulating frequency is located between the branches. Tho modulating signals are not summed through the capacitor (17), and, thus, their phase difference is not weakened.

Abstract: A symbol lock detector for an incoming coherent digital communication signal which utilizes a subcarrier modulated with binary symbol data, d.sub.k, and known symbol interval T by integrating binary values of the signal over nonoverlapping first and second intervals selected to be T/2, delaying the first integral an interval T/2, and either summing or multiplying the second integral with the first one that preceded it to form a value X.sub.k. That value is then averaged over a number M of symbol intervals to produce a static value Y. A symbol lock decision can then be made when the static value Y exceeds a threshold level .delta..

Abstract: A radio-frequency detection apparatus including a signal input for providing an input signal and a phase shifter having a first connection and a second connection. The phase shifter includes a SAW device having a first electrical connection and a second electrical connection, wherein the SAW first electrical connection is coupled to the phase shifter first connection and the SAW second electrical connection is coupled to the phase shifter second connection. The radio-frequency detection apparatus also includes a multiplier having a multiplier first input connection, a multiplier second input connection and at least one multiplier output connection, the multiplier first input connection being coupled to the signal input and the phase shifter first connection and the multiplier second input connection being coupled to the phase shifter second connection. The phase shifter introduces approximately a 90 degree phase shift into the input signal at approximately the frequency of minimum insertion loss.

Abstract: An amplitude modulated (AM) radio receiver uses a digital signal processor, responsive to in-phase (I) and quadrature-phase (Q) component signals, to compensate for carrier energy removed by a capacitive coupling circuit. A quadrature mixer converts the received AM signal to the I and Q component signals representative of the AM signal, and a signal filter passes a desired frequency segment of the I and Q component signals. A capacitive coupling circuit couples the I and Q component signals to provide representative I and Q signals with no DC bias to the input of an analog-to-digital converter. The analog-to-digital converter converts the representative unbiased I and Q signals to digital I and Q signals for processing by the digital signal processor.

Abstract: A media flaw detection apparatus having a sensitivity which is independent of the location of the flaw relative to the written test signal. The apparatus is equally sensitive to missing or extra bit defects. According to the invention, in-phase and quadrature-phase signals are heterodyned against the analog playback input signal. The resulting signals are squared and summed to produce a signal analogous to the effect of the flaw.

Abstract: A method of demodulating multi-standard TV signals consists of providing a plurality of signals at a frequency which is a multiple of a reference frequency whose value is a common submultiple of the frequencies of the multi-standard signals. Thereafter, the signal to be demodulated is multiplied by one of said plural signals having a frequency which differs therefrom by a value equal to the reference frequency; by filtering the result of the multiplication, a signal is obtained at the reference frequency but corresponding in amplitude to the one to be demodulated.

Abstract: An automated visual testing system is disclosed which presents an alternating steady state visual stimulus to a patient through an optical system that modifies the stimulus image. As the image changes, the patient produces evoked potentials that change. The evoked potentials are detected by a product detector which produces the amplitude of the evoked potentials. The product detector includes filters which isolate the patient's evoked potentials, a modulator which detects the response using the stimulus source frequency and a demodulator that determines the amplitude of the response. The product detector detects the level of the steady state evoked potential signals even in the presence of substantial background noise and extraneous electroencephalograhic signals. These detectors can be used to monitor the evoked potential produced by visual, aural or somatic steady state stimuli.

Abstract: An improved superregenerative detector including input elements for receiving a high frequency carrier signal having an amplitude envelope upon which an information signal is impressed, the detector also including a first and a second oscillator and output elements for producing an output signal corresponding to the information signal. The detector features use of feedback components among the output elements, the feedback components including an operational amplifier and reference signal connected to the first and second oscillators such that the output signal of the operational amplifier may be used to constrain a transistor that defines the first amplifier to operate within its linear portion.

Abstract: A method and apparatus for modulating or demodulating a radio frequency (RF) signal which incorporates a pair of quadrature couplers. In demodulating an RF signal, an LO signal and the RF signal are each phase shifted -90 degrees by the couplers. The RF and LO signals are mixed as are the phase-shifted RF and LO signals. Each mixed signal is low-pass filtered and the filtered signals are added thereby producing an intermediate frequency signal.

Abstract: A quadrature receiver is disclosed which contains two mixers (M1, M3) in an in-phase receiving path and two mixers (M2, M4) in a quadrature receiving path for converting a received signal to a low IF. Each of the mixers is fed with an oscillator signal (O1 through O4), with the oscillator signal fed to one mixer of the respective receiving path having alternately the same or opposite phase from that of the oscillator signal fed to the other mixer of the same receiving path. In each receiving path, the mixers are followed by a circuit (P', P") which delivers an in-phase signal and a quadrature signal, respectively. These circuits compensate for the DC offset caused by the mixers.

Abstract: In a synchronous demodulator for demodulating a carrier signal modulated with a useful signal, the demodulator including a filter circuit (2) for selecting the carrier signal, a limiter (3) for generating an amplitude-limited reference signal from the carrier signal, a phase shifter (4) for shifting the phase of the reference signal through a phase angle of essentially 90.degree. with respect to the carrier signal, and a multiplier (5) for multiplicatively combining the modulated carrier signal with the phase shifted reference signal, a simple arrangement effectively suppresses interference phase modulations, in that a dc mixing product is supplied (via 8) by the multiplier (5) as a measure of the frequency deviation of the carrier signal from the pass frequency of the filter circuit (2) as a control signal to this filter circuit for the purpose of controlling the pass frequency.

Abstract: A baseband carrier phase corrector is disclosed which permits rapid demodulation and demodulation of varying RF input signals. The baseband carrier phase corrector receives RF signals, or alternatively, IF signals, and converts the signals to baseband. An RF signal received by the baseband carrier phase corrector is split and multiplied with oscillating signals having a 90 degree phase differential. The resultant signals are baseband in-phase (I) and quadrature (Q) signals. The I and Q signals are filtered through low pass filters. The filtered I and Q signals are multiplied within a first complex multiplier with a generated phase error. The output of the first complex multiplier results in phase adjusted I and Q baseband signals. A symbol decision circuit estimates digital I and Q signals which are the allowed symbols closest in phase to the phase adjusted I and Q baseband signals. A second complex multiplier is coupled to the symbol decision circuit and to the outputs of the low pass filters.

Abstract: In a synchronous demodulation circuit for an IF television signal, having a passive carrier regenerator (37, 39), a quadrature component unwantedly demodulated by a synchronous in-phase demodulator (15) is compensated for by multiplying the output signal of this demodulator by the integrated (63) output signal of a synchronous in-phase demodulator (25) and by adding (79) the product obtained to the product of the output signal of a synchronous quadrature demodulator (19) and the integrated (65) output signal of a synchronous quadrature demodulator (29).

Abstract: A data signal is modulated by an exclusive-OR operation applied to a carrier signal and a data signal to be recorded. Demodulation is similarly performed by an exclusive-OR operation applied to the carrier signal and signal indicative of read data. This makes it possible to construct the modulating/demodulating circuit in the form of a digital circuit.