Abstract: A digital-to-analog converter includes an amplifier including at least two input terminals corresponding to a non-inverting input terminal; and a chopping unit performing a chopping operation between voltages provided to the at least two input terminals corresponding to the non-inverting input terminal. The digital-to-analog converter has an X+Y bit structure and removes an offset by performing an interpolation chopping operation and/or a main buffer chopping operation at the same time. The digital-to-analog structure can be embodied in a small area and can process high bit image data.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: A demodulator includes a sampler configured to sample a plurality of first amplitude values of a modulated carrier signal using a constant sampling frequency and a plurality of second amplitude values of the modulated carrier signal at different times using the same constant sampling frequency. The constant sampling frequency is equal to a carrier frequency of the modulated carrier signal with a tolerance of +/?1% of the carrier frequency.

Abstract: A method of detecting a communication mode is provided to rapidly detect which one of near field communication (NFC) protocols includes a communication frame pattern of data provided to a receiving device. The method includes receiving a communication frame pattern of data transmitted from an NFC initiator after synchronizing the communication frame pattern with a predetermined sampling clock. The detection of the communication mode may be done by analyzing a start pattern out of the communication frame pattern. Since a communication mode is rapidly detected and data is automatically received without performing an additional operation to set the communication mode, operation performance of a receiving device is improved.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.

Abstract: A receiver includes a receiving unit that receives a signal from a satellite, a frequency conversion-discretization unit that converts the signal received in the receiving unit into an intermediate frequency signal of a frequency bandwidth including 0 Hz, and discretizes the frequency-converted intermediate frequency signal with a predetermined sampling frequency, a filter unit that filters the discretized signal, which is output from the frequency conversion-discretization unit, through a predetermined filter, a synchronization acquisition unit that acquires synchronization of a spreading code in the discretized signal filtered by the filter unit, and a synchronization holding unit that holds the synchronization of the spreading code, which is acquired by the synchronization acquisition unit.

Abstract: The present invention relates to a demodulator for simultaneous multi-node receiving and a method therof; and, more particularly, a demodulator in a wireless communication system for receiving signals from multi nodes simultaneously and a method thereof. In accordance with the aspect of the present invention, there is provided a demodulator for simultaneous multi-node receiving which comprises: a clock generator for generating a pair of CW signals and a pair of demodulating modules, wherein the demodulating modules comprise a mixer for multiplying received signals and one of the CW signals, an integrator for integrating multiplied signal and data operating unit for calculating variation result of integrated signal at every certain symbol duration and deciding output data in accordance with the variation result.

Abstract: Some embodiments disclosed herein relate to a method. In the method, a duration of a first synchronization pulse is measured. A fixed, predetermined number of ticks are equally spaced at a first time interval over the first sync pulse, regardless of the duration of the first synchronization pulse. A duration of a first data pulse is then measured by periodically incrementing a tick count value at the first time interval during the entire duration of the first data pulse. The tick count value at an end of the first data pulse is then correlated to a first digital value encoded on the first data pulse.

Abstract: A burst mode receiver including a CDR circuit that does not perform bit synchronization determination at a wrong position even when a burst signal waveform containing a distortion is input is provided. The burst mode receiver includes a CDR circuit for reproducing clock and data from a received signal, a bit synchronization determination circuit for determining whether the CDR circuit is in an optimum phase, a waveform distortion determination circuit for determining from the received signal whether there is waveform distortion, and a CDR output enable determination circuit for determining whether an output of the CDR circuit is valid or invalid. The CDR output enable determination circuit performs CDR output enable determination based on a bit synchronization determination result and a waveform distortion determination result.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: Conventional modulation envelope demodulators for amplitude modulated signals (e.g. ASK coded signals RX) contain rectifier elements which extract a baseband signal BB. Disadvantageously, due to a non-linear characteristic of the rectifier elements, an amplitude of the baseband signal BB depends on an amplitude of the high-frequent carrier signal. The present invention discloses an improved demodulation circuit for demodulating of ASK coded or amplitude modulated signals. This is achieved by using a sampling mixer 4 and a phase adjusting regulation loop (5) by means of which the sampling of the ASK coded signal RX at its maxima is performed with high accuracy. Due to the absence of any rectifying elements, the baseband signal BB can be fully extracted from the ASK coded signals RX.

Abstract: The invention relates to a digital acquisition device for an amplitude modulation signal of a carrier. The acquisition device digitally acquires a useful signal. The useful signal modulates the amplitude of a carrier HF1 which has a frequency and a phase that are known. A modulation of the amplitude of the carrier by the useful signals forms a signal to be processed. According to the invention, the device has a summing device for creating an aggregate signal from a sum of the signal to be processed and a neutralizing signal. The neutralizing signal is a product of the carrier HF1 and of a neutralizing coefficient that can evolve over time, produced by a controlled-gain amplifier device. A load amplifier device amplifies the aggregate signal and produces an amplified aggregate signal. A quadrant comparison device QC is provided for the signal of the amplified aggregate signal and the sign of the carrier which delivers a comparison signal. A sampling device produces a bitstream from the comparison signal.

Abstract: An amplitude demodulation method and device comprising a converter sampling an input signal having its sampling frequency corresponding to three times the modulation carrier frequency.

Abstract: To improve the quality of the demodulated signal without altering the form in which an AM radio wave is transmitted, the received amplitude-modulated signal is converted to a single-sideband signal, and the information signal demodulated from the phase term of this converted single-sideband signal.

Abstract: An apparatus for measuring the inductance of a wire-loop with noise-cancellation, auto-calibration and wireless communication features, or detector circuit. The apparatus measures the effective change in inductance induced in a wire-loop as a vehicle passes over the wire-loop to produce an inductive signature corresponding to a vehicle.

Abstract: A demodulator for demodulating a modulated input signal transmitted at a carrier frequency includes a current mirror for receiving the modulated input signal and generating a first and a second current-mirror output signals of same amplitude and frequency as the modulated input signal. The demodulator further includes a first and a second switch-controlled sampling circuits connected to the current mirror for receiving the first and second current mirror output signals respectively. The demodulator further includes a switching signal generator provided for generating a first and a second switch control signals having a frequency substantially equals to the carrier frequency with a flexibly adjustable phase difference between the first and the second switch control signals.

Abstract: A bandpass phase tracker automatically samples at prescribed carrier phases when digitizing a vestigial-sideband intermediate-frequency signal, which VSB I-F signal is modulated in accordance with a baseband symbol code of a prescribed symbol frequency. Heterodyning circuitry mixes oscillations from a local oscillator with the VSB I-F signal received from the I-F amplifier to generate an analog low-frequency heterodyne signal offset from zero frequency. The heterodyne signal is digitized in accordance with a first sampling clock signal to supply input signal for digital demodulation circuitry that demodulates the VSB I-F signal to supply real and imaginary components of a demodulated signal at baseband. The real component of the demodulated signal is supplied to an equalizer and symbol decoded; the imaginary component controls the frequency and phase of the local oscillator.

Abstract: This invention discloses a demodulation method. The method includes steps of: A) Receiving a modulated input signal having an input signal frequency. B) Generating a first switch control signal at a first switching frequency substantially equal to the input signal frequency. C) Generating a second switch control signal having the same frequency as the first switch control signal and having a phase that is approximately 90 degrees different from a phase of the first switch control signal. And D) Controlling at least two switching circuits with the first and second switch control signals for obtaining at least two sets of sampled amplitudes of the input signals for generating switching output signals for each of the switching circuits defined by subtracting the sampled amplitudes when the first switch control signal is high by the sampled amplitudes when the first switch control signal is low for each of the switching circuits to generate demodulated output signals for the modulated input signal.

Abstract: A method for demodulating a voltage which has been ASK modulated by changing the amplitude between a low level and a high level, in particular for use during contactless data transmission from a card reader/writer to a smart card, is described. The method is distinguished, in that, in an initialization phase, a first mean value is produced from the high voltage level and a stored partial voltage derived therefrom in order to detect a change to a low voltage level. The change to the low voltage level represents a start value and is detected by a subsequent comparison of the modulated voltage with the first mean value. In a subsequent demodulation phase, a second mean value is produced from the detected low voltage level and the high voltage level in order to demodulate the modulated voltage by comparing the modulated voltage with the second mean value.

Abstract: A method and a system for phase sensitive rectification of signals from transducers driven by an AC excitation signal will be disclosed. The method and system demand a very moderate calculation capacity, thereby to facilitate the use of low cost microprocessors of ordinary speed. The present method and system utilize a sampling being synchronized with the transducer excitation frequency f. Sampling of the sensor signal is performed by an A/D-converter at a high sampling frequency, nf. The sampled signal then is averaged over half a period of the excitation signal frequency, whereby the starting point of the averaging is decided by the time of commutation. This is equal to filtering the sampled signal by a decimating filter. The rectification may then may be preformed with a number sequence sampled by the optimal sampling frequency 2f (twice the excitation frequency only) instead of the sampling frequency nf used for obtaining high resolution.

Abstract: An amplitude and phase demodulator circuit for signals with very low modulation index, including: amplifier circuitry adapted to amplify a modulated signal coming from a transmitter, the modulated signal being composed by a carrier and by a modulating component, circuitry adapted to cancel said carrier from said modulated signal; the circuitry adapted to cancel the carrier receiving in input the output signal of the amplifier circuitry and a sync signal coming from the transmitter, the output signal of the amplifier circuitry being delivered to receiver circuitry.

Abstract: An adaptable, variable rate symbol timing recovery system for a digital sal receiver comprises an analog to digital (A-D) signal converter having analog signal input and digital data signal output terminals. A source of selectable, substantially fixed rate, data sampling clock signals is coupled to the A-D signal converter for sampling a signal received at the input at a predetermined, substantially fixed clock rate, depending on data rate and modulation of the received signal. A digital signal processing loop is coupled to the digital data signal output terminal for adjustably producing interdependent signals in synchronism with the data signals at the output terminal which are asynchronous with respect to the fixed rate clock signals. A Controller is provided for selectively configuring the data sampling clock signal source and the digital signal processing loop according to the data rate and modulation characteristics of the received signal.

Abstract: A digital implementation for a carrier detector. The detector determines if the carrier frequency at any instant is within a predetermined frequency band. The detector further determines if the detected frequency remains within the predetermined frequency band for a predetermined period of time. The detector also provides an indication that there has not been any loss of carrier for another predetermined period of time.

Abstract: A digital receiver has a receiving section for receiving a digital modulated signal, a digital demodulation section for judging a logical state of a detection output signal obtained by performing a digital detection operation for the digital modulated signal, for demodulating the digital modulated signal and for generating a data signal. The digital demodulation section has a binary conversion circuit for converting the data signal into a binary signal and a receiving quality detection device for detecting a receiving quality of the data signal based on a wave-form of the binary signal. The receiving quality detection device has a pulse generator for generating pulses having a time width between a positive pulse width of the wave-form of the binary signal based on the digital modulated signal and a time width between a third time width and a time width which is obtained by subtracting a negative pulse width of the wave-form of the binary signal from a second pulse width.

Abstract: A radio frequency (rf) receiver adapted to receive a number of different digitally modulated rf input signals such as quadrature amplitude modulated (QAM) and vestigial side band (VSB) rf input signals includes circuitry for down converting the rf input signals to an intermediate frequency (IF) range having a center frequency fc2 and a bandwidth of Bhz and converter circuitry for sampling the IF signals and then producing corresponding baseband signals. In a preferred embodiment, the intermediate frequency signals are applied to a sample and hold circuit which is sampled at a frequency fs and whose output is coupled via a low pass filter to an analog-to-digital converter whose output is then applied to a Hilbert filter for demodulating the sampled signals and producing baseband signals. In-phase (I) and quadrature (Q) signals are produced whose phase and amplitude are not a function of different components and their tolerance of different conduction paths, as in the prior art.

Abstract: A burst-mode digital receiver which minimizes any reduction in the minimum input level as compared with a continuous-signal digital receiver includes a unipolar code-to-bipolar code converter for converging unipolar code pulses of an inputted burst signal into bipolar code pulses, an identifying circuit for identifying logic levels of "1" and "0" with an identifying level at a center of a pulse duration of bipolar code pulses outputted from the unipolar code-to-bipolar code converter, and a burst on/off detecting circuit for continuously outputting a signal until the inputted burst signal is finished when a pulse amplitude of the inputted burst signal exceeds a constant value. The burst-mode digital receiver produces an output signal when an AND gate connected to the output terminal of the identifying circuit is turned on at the time the output signal from the burst on/off detecting circuit is turned on.

Abstract: A modulation and demodulation scheme for video signals may be used for HDTV signals using VSB-PAM, analog NTSC signals using VSB-AM and digital video signals using QAM. VSB-PAM modulation and demodulation may be performed using in-phase and quadrature baseband filters. By adjusting the filter taps, a single modulator structure may be used for QAM and VSB-PAM modulation. Similarly, a single demodulator structure may be used for QAM and VSB-PAM demodulation. This demodulator may also be used for VSB-AM modulation.

Abstract: A demodulating method wherein the signal can be demodulated accurately even if the S/N ratio is lower by calculating an amplitude peak value by a specific formula from two values of an amplitude of an acoustic signal corresponding to a phase difference of 90 degrees at a carrier frequency transmitted by an acoustic signal transmitter, setting a threshold level preliminarily for the amplitude peak value, and demodulating the amplitude peak value by binarization on the basis of the threshold level, and a demodulating circuit and a demodulating apparatus used in the execution thereof.

Abstract: A sampling synchronous envelope detector adopts a specialized sample-and-hold ("S&H") approach, basing a detected output on instantaneous values of the carrier waveform which are sampled at specially chosen instants. Non-linear distortion is avoided by timing the sampling instants to occur at or near a carrier wave peak which is subsequent to an earlier carrier wave peak which serves as a time base. Sampling instants occur only at or near positive carrier peaks (or only at or near negative peaks) in a half-wave embodiment, and sampling instants occur at or near both positive and negative carrier peaks in a full wave embodiment. Another aspect of the detector provides means, such as a phase locked loop, for ensuring that the phase of the sampling instants is maintained continuously, even in the event of carrier pinch-off or other event which distorts or minimizes the carrier waveform from which the timing instants would otherwise be determined.

Abstract: An AM demodulator circuit arrangement includes an operational amplifier having at least two alternate input networks and at least two alternate feedback networks which can be selectively activated by switching signals so as to establish an amplifier gain factor having at least two different predetermined values. The switching signals are derived from a square wave clock control signal of a frequency which is an integral multiple of the carrier frequency of the AM input signal supplied to the demodulator. As a result of the periodic variation of the amplifier gain factor, the demodulated signal is produced at the output of the amplifier. Such a demodulator avoids offsets or interference frequencies due to manufacturing tolerances. Sensitivity to interference at higher harmonics of the carrier frequency can be suppressed by appropriate selection of the waveform of the gain factor variation, which is determined by the waveform of the switching signal.

Abstract: Amplitude Shift Keying (ASK) modulation system and method with an ASK demodulator that is implemented with an analog-emulating digital bandpass filter. The bandpass filter also generates a carrier detect signal when it detects a carrier frequency that passes the filter pass band.

Abstract: In an amplitude demodulator for radio receivers, an intermediate frequency signal is converted into a digital intermediate frequency signal. The digital intermediate frequency signal is mixed into the baseband and amplitude demodulated. Either the intermediate frequency signal, or the amplitude demodulated signal, is controlled and amplified or attenuated so that the DC component of the amplitude demodulated signal is kept constant.

Abstract: To demonstrate a signal, the signal is sampled and each sample of the signal is multiplied by the sine and the cosine of a phase angle indicating when the sample was taken from the signal. The sinusoidal signal for producing an in-phase demodulated signal is Chebychev-approximation derived and computed as a selected even or odd polynomial, depending on whether the phase angle falls within one of a plurality of angular ranges. So that the error in the synthetic sinusoid is minimax and so that the even and odd polynomials have similar computational complexity, the angular ranges for the even polynomial exceed the angular ranges for the odd polynomial. Preferably, the sinusoid for producing a quadrature-phase demodulated signal is computed as a differential of the sinusoid spliced from the odd and even polynomials. Therefore the quadrature-phase demodulated signal can be provided with a minimal increase in computational complexity.

Abstract: A receiver array in accordance with the reception principle of synchronous demodulation, in which a controllable oscillator array is pre-synchronized to a set value for the oscillator frequency by a digital first control circuit having a reference frequency source during a pre-synchronization phase, and a heterodyne signal derived from the oscillator frequency is then synchronized with phase locking to the received useful signal by switching the oscillator control input to an analog second control circuit.

Abstract: Generally, and in one form of the invention, a composite signal decoder (60) is disclosed which does not require synchronizing the sampling rate to the phase of the incoming pilot signal. Curve fitting filter (126) up-samples and interpolates the incoming composite signal (A) using a bank of coefficient filters selected from filter coefficient bank storage (122) by Bank Selector (124). Bank selector (124) operates in response to a phase offset value produced by phase calculator (112). Because curve fitting filter (126) need not be synchronous with the incoming pilot signal, the output sample rate can be asynchronous from the input sample rate. Other devices, systems and methods are also disclosed.

Abstract: A signal processing method and system in a receiving apparatus including a receiving equalizer circuit are provided for extracting transmission data from a received signal inputted via a transmission path every transmission frame having a predetermined synchronization pattern and transmission data. A phase error is detected from the received signal extracted in synchronism with a sampling signal in the receiving equalizer circuit. The frequency of the sampling signal is controlled until the phase error becomes minimum. In parallel, it is detected whether the frame synchronization pattern is present in the received signal in a predetermined interval or not. When the presence of the frame synchronization pattern is not detected after the phase has been stabilized by frequency control of the sampling signal, the sampling phase of the received signal is judged to be in the quasi-convergence state. Then the frequency of the sampling signal is forcibly changed largely.

Abstract: An infrared detector output of a radiometer is amplified and inverted to provide a first signal which is amplified to a predetermined level and a second signal which is inverted with respect to the first signal and amplified to a fraction of the predetermined level of the first signal. The first and second signals are alternately sampled to sample portions of those signals which occur when the detector of the radiometer is viewing the target and then viewing the reference. The signals are sampled once while the detector of the radiometer is looking at the target and twice occurring on each side of the target sample when the detector is looking at the reference signal. The first and second signals are separately integrated in accordance with a predetermined timing pattern determined by the sampling rate of the first (target) and second (reference) signals. The peak integrated outputs of the first and second signals are held then sampled to produce the demodulated output from the radiometer.

Abstract: A synchronous demodulator includes a switch which is operated in synchronism with an incoming periodic signal and both divides and applies that signal to two signal channels. The two channels each include a network for computing and holding, for a predetermined length of time, the average signal value on that channel and applies those values, in the form of two other signals, to the inputs of a diffferential amplifier. The networks may be R-C networks. The output of the differential amplifier may or may not form the output of the synchronous detector and may or may not be filtered. The output will not include a periodic signal due to the presence of a dc offset. Additionally, the output will not contain any substantial ripple due to periodic components in the input signal.

Abstract: A digital receiver samples data from an amplitude modulated subcarrier at a rate less than twice the subcarrier's maximum frequency by sampling at known phase points. Sampling at known phase points is achieved by generating a sampling clock from a signal phase locked to and transmitted with the modulated data subcarrier.