Abstract: Disclosed herein is a demodulator, including: a splitting/matching section for carrying out a matching process of making the amplitude and phase of a first modulated signal match respectively the amplitude and phase of a second modulated signal; and a demodulation section for generating a demodulated signal on the basis of the first modulated signal and the second modulated signal, which have been subjected to the matching process carried out by the splitting/matching section, wherein the splitting/matching section has a splitting section, a first matching section, and a second matching section, the first circuit-element constants determining the first input impedance of the first matching section and the second circuit-element constants determining the second input impedance of the second matching section are set at values determined in advance in order to make the first input impedance equal to the second input impedance.

Abstract: The present invention relates to a demodulator for simultaneous multi-node receiving and a method therof; and, more particularly, a demodulator in a wireless communication system for receiving signals from multi nodes simultaneously and a method thereof. In accordance with the aspect of the present invention, there is provided a demodulator for simultaneous multi-node receiving which comprises: a clock generator for generating a pair of CW signals and a pair of demodulating modules, wherein the demodulating modules comprise a mixer for multiplying received signals and one of the CW signals, an integrator for integrating multiplied signal and data operating unit for calculating variation result of integrated signal at every certain symbol duration and deciding output data in accordance with the variation result.

Abstract: A receiver has an input stage (LNA) that comprises, in a signal direction from an input (SI) to an output (SO), an input transistor (Q1) and an attenuator (D1, D2, R7-R12, C2-C5). The attenuator provides an attenuation that depends on a control signal (VDC). The input stage comprises a transistor-biasing circuit (R2) that biases the input transistor in dependence on the control signal.

Abstract: A semiconductor device is provided, which comprises a first demodulation circuit, a second demodulation circuit, a first bias circuit, a second bias circuit, a comparator, an analog buffer circuit, and a pulse detection circuit. An input portion of the pulse detection circuit is electrically connected to an output portion of the analog buffer circuit, a first output portion of the pulse detection circuit is electrically connected to an input portion of the first bias circuit, and a second output portion of the pulse detection circuit is electrically connected to an input portion of the second bias circuit.

Abstract: The present invention shows a contactless chip card comprising a controllable demodulation unit for demodulating an amplitude-modulated carrier signal, a measuring unit for determining a degree of modulation of the modulated carrier signal, and a control unit for controlling the demodulation unit on the basis of the determined degree of modulation of the carrier signal.

Abstract: An RFID reader device (31), of the type comprising a demodulator (6) for receiving from a RFID tag (11) an AM (Amplitude Modulation) wave (20) having a predetermined frequency (f) and for retrieving, from the AM wave (20), a demodulated output (6a) associated to predetermined positive or negative Amplitudes of said AM wave (20), said demodulated output having a portion with a frequency F. The AM demodulation system comprises at least a second demodulator (26) for receiving the AM wave (20) and retrieving a second demodulated output (26a) associated to Amplitudes opposite to the predetermined positive or negative Amplitudes, said second demodulated output having a portion with said frequency F; the RFID reader includes a block (27) having, in input, the demodulated output (6a) and the second demodulated output (26a) and returning, in output, an enforced demodulated output (30) with a portion with frequency (f1) doubled with respect to said frequency (F).

Abstract: Disclosed herein is a demodulator, including: a splitting/matching section for carrying out a matching process of making the amplitude and phase of a first modulated signal match respectively the amplitude and phase of a second modulated signal; and a demodulation section for generating a demodulated signal on the basis of the first modulated signal and the second modulated signal, which have been subjected to the matching process carried out by the splitting/matching section, wherein the splitting/matching section has a splitting section, a first matching section, and a second matching section, the first circuit-element constants determining the first input impedance of the first matching section and the second circuit-element constants determining the second input impedance of the second matching section are set at values determined in advance in order to make the first input impedance equal to the second input impedance.

Abstract: A receiving circuit and method for receiving an amplitude shift keying signal is provided. At least one exponent signal, an exponent-removed in-phase signal, and an exponent-removed quadrature-phase signal are generated from an in-phase input signal and a quadrature-phase input signal. An amplitude is determined as a sum of several summands, whereby the summands are determined from the exponent signal and/or from the exponent-removed in-phase signal and/or from the exponent-removed quadrature-phase signal (Q?), and wherein the amplitude (A) is demodulated.

Abstract: An electronic circuit includes: a circuit generating first and second balanced differential input signals; a first envelope detection circuit including a first output terminal and first and second input terminals receiving the first and second input signals, respectively, via first and second impedance elements, respectively, and outputs from the first output terminal a first output signal that is the sum of the squares of the first and second input signals; a second envelope detection circuit including a second output terminal and third and fourth input terminals receiving the first and second input signals, respectively, via third and fourth impedance elements, respectively, and outputs from the second output terminal a second output signal that is twice the value obtained by squaring the average of the first and second input signals; and a differential circuit generating a differential signal from the first and second output signals.

Abstract: A digital demodulation device for demodulating an amplitude modulation (AM) signal whose carrier has a first frequency includes: a processing circuit for performing first path digital processing and second path digital processing according to a second frequency and digital values of the AM signal, where the first path digital processing represents performing down conversion by mixing the AM signal with a first sinusoidal signal whose frequency is equal to the second frequency, the second path digital processing represents performing down conversion by mixing the AM signal with a second sinusoidal signal whose frequency is equal to the second frequency, the second frequency is equal to the first frequency plus a predetermined frequency shift, and the second sinusoidal signal is orthogonal to the first sinusoidal signal; and an output stage for outputting an output signal according to processing results of the first path digital processing and the second path digital processing.

Abstract: An RFID reader device (31), of the type comprising a demodulator (6) for receiving from a RFID tag (11) an AM (Amplitude Modulation) wave (20) having a predetermined frequency (f) and for retrieving, from the AM wave (20), a demodulated output (6a) associated to predetermined positive or negative Amplitudes of said AM wave (20), said demodulated output having a portion with a frequency F. The AM demodulation system comprises at least a second demodulator (26) for receiving the AM wave (20) and retrieving a second demodulated output (26a) associated to Amplitudes opposite to the predetermined positive or negative Amplitudes, said second demodulated output having a portion with said frequency F; the RFID reader includes a block (27) having, in input, the demodulated output (6a) and the second demodulated output (26a) and returning, in output, an enforced demodulated output (30) with a portion with frequency (f1) doubled with respect to said frequency (F).

Abstract: A test apparatus includes digital modulators provided in increments of multiple channels. A baseband signal generator performs retiming of data input as a modulation signal for the in-phase (quadrature) component, using a timing signal the timing of which can be adjusted, thereby generating a baseband signal. A driver generates a multi-value digital signal having a level that corresponds to the baseband signal output from the baseband signal generator. A multiplier amplitude-modulates a carrier signal with the multi-value digital signal. An adder sums the output signals of the multipliers.

Abstract: AM (Amplitude Modulation) demodulation system (36) for an RFID reader device (31), of the type comprising a demodulator (6) for receiving from a RFID tag (11) an AM (Amplitude Modulation) wave (20) having a predetermined frequency (f) and for retrieving, from the AM wave (20), a demodulated output (6a) associated to predetermined positive or negative Amplitudes of said AM wave (20). The AM demodulation system comprises at least a second demodulator (26) for receiving the AM wave (20) and retrieving a second demodulated output (26a) associated to Amplitudes opposite to the predetermined positive or negative Amplitudes and a block (27) having, in input, the demodulated output (6a) and the second demodulated output (26a) and returning, in output, an enforced demodulated output (30) with a frequency (f1) greater than the predetermined frequency (f).

Abstract: An arrangement is described for demodulating a vestigial sideband signal component contained in an amplitude-modulated frequency signal, and preferably in a vision intermediate-frequency signal derived from a television signal.

Abstract: An amplitude modulation receiver including an antenna for receiving a signal and an input filter connected to the antenna. A variable gain amplifier is connected to the input filter and is responsive to a gain control signal. An A/D converter is connected to the variable gain amplifier and is responsive to a sampling signal and provides a sampled digital signal. A D/A converter receives a demodulated signal and provides an analog output signal. A controller receives and demodulates the sampled digital signal from the A/D converter, generates the gain control signal for the variable gain amplifier, generates the sampling signal for the A/D converter, and provides the demodulated signal to the D/A converter. The demodulation and generation of the gain control signal and the sampling signal are performed in software.

Abstract: Digitally sampled real or sampled and down-converted complex data representing an RF signal are received. One or more statistical computations are calculated for each group of N data values. The one or more statistical computations are calculated for groups of N data values until a particular number of data values (K) are acquired. The one or more statistical computations calculated for each group are computed and stored at the time of acquisition and are available for immediate viewing on a display.

Abstract: Two capacitors are provided for demodulating an amplitude-modulated signal and can be supplied with a signal that is rectified by a diode and that is at a voltage. The half-cycles of this signal are used for alternately charging the first or second capacitor using a switch. The capacitors are discharged using switches. Comparing the amplitude values, which are stored in the capacitors, of successive half-cycles in an evaluation unit allows simple and precise demodulation, which can be achieved with few components and can be carried out at very high frequencies.

Abstract: A high speed demodulator system is comprised of an analog to digital converter (ADC); a high speed demultiplexer connected to an input of the ADC; a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer; a timing interface connected to the bank of parallel programmable demodulators; and a phase reference interface connected to the bank of parallel programmable demodulators and a data processor. A parallel programmable demodulator includes a reconfigurable FIR filter, has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The programmable FIR filter provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory.

Abstract: A receiver is adaptively calibrated by using a coherent reference signal. The reference signal is selected to be offset from a center frequency of the calibration signal such that the resultant product is offset from baseband by some small amount. The resultant product is used to determine a next value of the calibration parameters.

Abstract: A signal detection circuit employs a delay line with edge detection logic for capturing and buffering timing information about an input signal. A plurality of comparators for comparing the input signal to different reference potentials capture amplitude information in the input signal launching bits into respective delay lines. Preferably, each delay line includes a counter for counting detected bit edges.

Abstract: A modulation and demodulation scheme for video signals may be used for HDTV signals using VSB-PAM, analog NTSC signals using VSB-AM and digital video signals using QAM. VSB-PAM modulation and demodulation may be performed using in-phase and quadrature baseband filters. By adjusting the filter taps, a single modulator structure may be used for QAM and VSB-PAM modulation. Similarly, a single demodulator structure may be used for QAM and VSB-PAM demodulation. This demodulator may also be used for VSB-AM modulation.

Abstract: A sampling synchronous envelope detector adopts a specialized sample-and-hold ("S&H") approach, basing a detected output on instantaneous values of the carrier waveform which are sampled at specially chosen instants. Non-linear distortion is avoided by timing the sampling instants to occur at or near a carrier wave peak which is subsequent to an earlier carrier wave peak which serves as a time base. Sampling instants occur only at or near positive carrier peaks (or only at or near negative peaks) in a half-wave embodiment, and sampling instants occur at or near both positive and negative carrier peaks in a full wave embodiment. Another aspect of the detector provides means, such as a phase locked loop, for ensuring that the phase of the sampling instants is maintained continuously, even in the event of carrier pinch-off or other event which distorts or minimizes the carrier waveform from which the timing instants would otherwise be determined.

Abstract: A demodulation system extracts data from an input amplitude modulated signal electromagnetic wave with a signal multiplying means that has two input terminals both of which are coupled to receive the input amplitude modulated signal. An output terminal of the multiplying means provides an output signal which is the instantaneous square of the input amplitude modulated signal. A lowpass filter is coupled to the output terminal of the signal multiplying means to reject at least twice the carrier frequency 2(.omega..sub.c) and higher frequency components, and to pass the second harmonic and lower frequencies of the modulation signal 2(.omega..sub.m(max)) to provide a filtered signal that is representative of the square of the amplitude modulation of the input signal. This demodulation method approaches ideal square law detection with power measurement of the input amplitude modulated signal. The filtered signal is supplied to an analog-to-digital converter to supply a digital data output.

Abstract: A demodulator receives a radio signal and causes a carrier signal reproducing circuit to reproduce the carrier signal of the received signal. One amplifier amplifies the amplitude of the reproduced carrier signal by K, and another amplifies the amplitude of the reproduced carrier signal by (K+2). An adder adds the reproduced carrier signal, amplified by K, and the received signal. A subtracter subtracts the received signal from the reproduced carrier signal amplified by (K+2). The output signal of the adder is demodulated by a first FM demodulator and the output signal of the subtracter is demodulated by a second FM demodulator. Another subtracter outputs the difference between the demodulated signals from the first and second FM demodulators as a demodulated signal of the received signal.

Abstract: A detector (100) determines whether an input signal (10) comprises a first signal or a second signal. A first local signal (207) is generated based on the first signal and a second local signal (307)is generated based on the second signal. A first error (211) is formed based on the first local signal and a scaled input signal (50), and a second error (311) is formed based on the second local signal and the scaled input signal. A first distance (215) between the scaled input signal and the first local signal is formed based on the first error, while a second distance (315) between the scaled input signal and the second local signal is formed based on the second error. Whether the input signal comprises the first signal or the second signal is determined by comparing (60) the first distance to the second distance.

Abstract: A radio-frequency detection apparatus including a signal input for providing an input signal and a phase shifter having a first connection and a second connection. The phase shifter includes a SAW device having a first electrical connection and a second electrical connection, wherein the SAW first electrical connection is coupled to the phase shifter first connection and the SAW second electrical connection is coupled to the phase shifter second connection. The radio-frequency detection apparatus also includes a multiplier having a multiplier first input connection, a multiplier second input connection and at least one multiplier output connection, the multiplier first input connection being coupled to the signal input and the phase shifter first connection and the multiplier second input connection being coupled to the phase shifter second connection. The phase shifter introduces approximately a 90 degree phase shift into the input signal at approximately the frequency of minimum insertion loss.

Abstract: An amplitude modulated (AM) radio receiver uses a digital signal processor, responsive to in-phase (I) and quadrature-phase (Q) component signals, to compensate for carrier energy removed by a capacitive coupling circuit. A quadrature mixer converts the received AM signal to the I and Q component signals representative of the AM signal, and a signal filter passes a desired frequency segment of the I and Q component signals. A capacitive coupling circuit couples the I and Q component signals to provide representative I and Q signals with no DC bias to the input of an analog-to-digital converter. The analog-to-digital converter converts the representative unbiased I and Q signals to digital I and Q signals for processing by the digital signal processor.

Abstract: The order statistic signal processor obtains continuing estimates of amplitude, phase, or frequency of an input signal based on order statistics. By way of definition, the P'th order statistic for a set of samples from a continuously distributed process is the P'th largest of the samples. Where a signal parameter fluctuates with time as a result of contamination by noise and interference and where the noise fluctuation rate is much greater than the rate at which changes in a signal parameter occur, an order statistic associated with a set of signal parameter samples can serve as an estimate of the signal parameter. The order statistic signal processor is based on an iterative process whereby the prior estimate of a signal parameter, i.e. amplitude or phase, is subtracted from each of a plurality of signal parameter samples obtained over a period of time. The differences are converted to quantities of fixed magnitude with signs corresponding to the differences.

Abstract: A circuit array for frequency translation by means of quadrature heterodyne signals has very low quadrature errors even at very high frequencies and is monolithically integratable with little external circuitry. The circuit array includes a first mixer which receives a first portion of an input signal, a second mixer which receives a second portion of the input signal, and a heterodyne signal generator which receives a local oscillator signal and supplies quadrature heterodyne signals to the mixers. The heterodyne signal generator includes a control loop to ensure a 90.degree. phase shift between the quadrature heterodyne signals. The circuit array can be used in a modulator for a transmitter or in a demodulator for a receiver.

Abstract: There is disclosed a system and method for demodulating an analog signal using digital conversion of the analog signal. In one embodiment the incoming modulated signal is digitally sampled and a calculation is made as to both the short term and long term energy of the digitized version of the analog signal. The deviation between the short and long term energy levels is used to determine the amount of modulation of the incoming analog signal. An analog demodulated signal is then reconstructed from the digitized deviation calculations. In an alternate embodiment, a digital signal processor is used to derive the demodulated signal.

Abstract: Several techniques are disclosed for producing modulation of a carrier signal wherein each transition of the modulated carrier signal includes a midrange level and/or two midrange characteristics, the level and/or ratio of the two midrange characteristics representing data carried by that transition. A simplified method over that disclosed in parent application Ser. No. 590,281, filed Mar. 16, 1984 now U.S. Pat. No. 4,613,974 is disclosed herein, and is referred to as a "flipped sine wave" method of producing the modulated carrier signal. Another technique, referred to as a "third harmonic modulation" technique uses the phase relationship between a fundamental and its third harmonic to produce the modulated carrier signal. A technique for storing the modulated carrier on magnetic media and correcting for offset resulting therefrom or from attenuation and advance of the third harmonic relative to the fundamental to permit accurate demodulation is disclosed.

Abstract: A digitized synchronous demodulator is constructed entirely of digital components including timing logic, an accumulator, and means to digitally filter the digital output signal. Indirectly, it accepts, at its input, periodic analog signals which are converted to digital signals by traditional analog-to-digital conversion techniques. Broadly, the input digital signals are summed to one of two registers within an accumulator, based on the phase of the input signal and mediated by timing logic. At the end of a predetermined number of cycles of the inputted periodic signals, the contents of the register that accumulated samples from the negative half cycle is subtracted from the accumulated samples from the positive half cycle. The resulting difference is an accurate measurement of the narrow band amplitude of the periodic input signal during the measurement period.

Abstract: A quadrature receiver is disclosed which contains two mixers (M1, M3) in an in-phase receiving path and two mixers (M2, M4) in a quadrature receiving path for converting a received signal to a low IF. Each of the mixers is fed with an oscillator signal (O1 through O4), with the oscillator signal fed to one mixer of the respective receiving path having alternately the same or opposite phase from that of the oscillator signal fed to the other mixer of the same receiving path. In each receiving path, the mixers are followed by a circuit (P', P") which delivers an in-phase signal and a quadrature signal, respectively. These circuits compensate for the DC offset caused by the mixers.

Abstract: In a synchronous demodulator for demodulating a carrier signal modulated with a useful signal, the demodulator including a filter circuit (2) for selecting the carrier signal, a limiter (3) for generating an amplitude-limited reference signal from the carrier signal, a phase shifter (4) for shifting the phase of the reference signal through a phase angle of essentially 90.degree. with respect to the carrier signal, and a multiplier (5) for multiplicatively combining the modulated carrier signal with the phase shifted reference signal, a simple arrangement effectively suppresses interference phase modulations, in that a dc mixing product is supplied (via 8) by the multiplier (5) as a measure of the frequency deviation of the carrier signal from the pass frequency of the filter circuit (2) as a control signal to this filter circuit for the purpose of controlling the pass frequency.

Abstract: A baseband carrier phase corrector is disclosed which permits rapid demodulation and demodulation of varying RF input signals. The baseband carrier phase corrector receives RF signals, or alternatively, IF signals, and converts the signals to baseband. An RF signal received by the baseband carrier phase corrector is split and multiplied with oscillating signals having a 90 degree phase differential. The resultant signals are baseband in-phase (I) and quadrature (Q) signals. The I and Q signals are filtered through low pass filters. The filtered I and Q signals are multiplied within a first complex multiplier with a generated phase error. The output of the first complex multiplier results in phase adjusted I and Q baseband signals. A symbol decision circuit estimates digital I and Q signals which are the allowed symbols closest in phase to the phase adjusted I and Q baseband signals. A second complex multiplier is coupled to the symbol decision circuit and to the outputs of the low pass filters.

Abstract: In a synchronous demodulation circuit for an IF television signal, having a passive carrier regenerator (37, 39), a quadrature component unwantedly demodulated by a synchronous in-phase demodulator (15) is compensated for by multiplying the output signal of this demodulator by the integrated (63) output signal of a synchronous in-phase demodulator (25) and by adding (79) the product obtained to the product of the output signal of a synchronous quadrature demodulator (19) and the integrated (65) output signal of a synchronous quadrature demodulator (29).