Abstract: Disclosed herein is a demodulator, including: a splitting/matching section for carrying out a matching process of making the amplitude and phase of a first modulated signal match respectively the amplitude and phase of a second modulated signal; and a demodulation section for generating a demodulated signal on the basis of the first modulated signal and the second modulated signal, which have been subjected to the matching process carried out by the splitting/matching section, wherein the splitting/matching section has a splitting section, a first matching section, and a second matching section, the first circuit-element constants determining the first input impedance of the first matching section and the second circuit-element constants determining the second input impedance of the second matching section are set at values determined in advance in order to make the first input impedance equal to the second input impedance.

Abstract: Disclosed herein is a demodulator, including: a splitting/matching section for carrying out a matching process of making the amplitude and phase of a first modulated signal match respectively the amplitude and phase of a second modulated signal; and a demodulation section for generating a demodulated signal on the basis of the first modulated signal and the second modulated signal, which have been subjected to the matching process carried out by the splitting/matching section, wherein the splitting/matching section has a splitting section, a first matching section, and a second matching section, the first circuit-element constants determining the first input impedance of the first matching section and the second circuit-element constants determining the second input impedance of the second matching section are set at values determined in advance in order to make the first input impedance equal to the second input impedance.

Abstract: An electronic circuit includes: a circuit generating first and second balanced differential input signals; a first envelope detection circuit including a first output terminal and first and second input terminals receiving the first and second input signals, respectively, via first and second impedance elements, respectively, and outputs from the first output terminal a first output signal that is the sum of the squares of the first and second input signals; a second envelope detection circuit including a second output terminal and third and fourth input terminals receiving the first and second input signals, respectively, via third and fourth impedance elements, respectively, and outputs from the second output terminal a second output signal that is twice the value obtained by squaring the average of the first and second input signals; and a differential circuit generating a differential signal from the first and second output signals.

Abstract: An electronic circuit includes: a circuit that generates a first input signal and a second input signal that are balanced differential signals; a first envelope detection circuit that includes a first input terminal, a second input terminal, and a first output terminal, the first input signal being input to the first input terminal via a first impedance element, the second input signal being input to the second input terminal via a second impedance element, and outputs from the first output terminal a first output signal that is the sum of the square of the first input signal and the square of the second input signal; a second envelope detection circuit that includes a third input terminal, a fourth input terminal, and a second output terminal, the first input signal being input to the third input terminal via a third impedance element, the second input signal being input to the fourth input terminal via a fourth impedance element, and outputs from the second output terminal a second output signal that is twi

Abstract: A system and method is disclosed for demodulating RF amplitude modulated signals in a demodulator circuit of an EPC0 compliant RFID tag. One advantageous embodiment of the invention comprises first and second input ports, a +ve envelope detector circuit for each of the first and second input ports, a ?ve envelope detector circuit for each of the first and second input ports, a +ve envelope differentiator circuit, a +ve low pass filter, a ?ve envelope differentiator circuit, a ?ve low pass filter, and a zero crossing detector. The zero crossing detector detects a transition in the RF input signal using a voltage difference between a +ve filtered differentiated envelope signal and a ?ve filtered differentiated envelope signal.

Abstract: One embodiment of the present invention includes a gating circuit, a demultiplexer, and an integrator. The gating circuit gates an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock. The demultiplexer demultiplexes the gated input sample to generate in-phase and quadrature samples. The integrator integrates the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively. Each of the in-phase and quadrature decimated samples having K bits.

Abstract: This invention provides a demodulation method and a demodulator for demodulating by converting analog signal obtained by reading information stored in a recording medium to digital signal so as to generate data representing that information. Consequently, correct data is obtained from signal having low S/N ratio.

Abstract: A diode device with a low or negligible threshold voltage includes at least one field effect transistor, the gate of the field effect transistor being connected to the drain of the field effect transistor. The threshold voltage of the diode device is approximately of the same magnitude as the potential of the gate of the field effect transistor forming part of the diode device.

Abstract: A signal envelope measurement preprocessing circuit including: input signal adjuster for interdicting a DC component contained in a signal input for measurement of the degree of flatness of an envelope or for passing only frequencies above a predetermined frequency; first and second half-wave rectifiers for separating into upper and lower portions the envelope of a signal output from the input signal adjusting means to thereafter detect the same; first and second frequency converters for converting a high frequency signal respectively from the first and second half-wave rectifiers into a low frequency signal; an analog-to-digital converters for converting a signal selected from low frequency signals output from the first and second frequency converters to a digital signal; and a system controller for comparing a data output from the analog-to-digital converter with a data stored on an internal program to thereafter measure the degree of flatness of a signal envelope.