Modulator-demodulator-type Amplifier Patents (Class 330/10)
  • Patent number: 11405007
    Abstract: An amplifier, such as a Class D amplifier, having one or more feedback loops comprising a path from the input to the primary amplifier input, where the paths comprise a low pass filter and a compensator which is disabled when the primary amplifier clips.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 2, 2022
    Assignee: PURIFI APS
    Inventors: Bruno Putzeys, Lars Risbo
  • Patent number: 11394355
    Abstract: A semiconductor device includes: a first buffer at which a predetermined signal is input and that outputs a first output signal; a second buffer at which an inverted signal of the predetermined signal is input and that outputs a second output signal; and a short circuit detection circuit that, in accordance with a potential difference between the first output signal and the second output signal, outputs a short circuit evaluation signal evaluating whether or not there is a ground fault in at least one of a first terminal at an output side of the first buffer or a second terminal at an output side of the second buffer or evaluating whether or not there is a short circuit between the first terminal and the second terminal.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: July 19, 2022
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Suguru Kawasoe
  • Patent number: 11387793
    Abstract: This application relates to amplifier circuitry, in particular class-D amplifiers, operable in open-loop and closed-loop modes. An amplifier (300) has a forward signal path for receiving an input signal (SIN) and outputting an output signal (SOUT) and a feedback path operable to provide a feedback signal (SFB) from the output. A feedforward path provide a feedforward signal (SFF) from the input and a combiner (105) is operable to determine an error signal (?) based on a difference between the feedback signal and the feedforward signal. The feedforward comprises a compensation module (201) configured to apply a controlled transfer function to the feedforward signal in the closed-loop mode of operation, such that an overall transfer function for the amplifier is substantially the same in the closed-loop mode of operation and the open-loop mode of operation.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: July 12, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John Paul Lesso
  • Patent number: 11381203
    Abstract: A transmitter that reduces 3rd order harmonic (HD3) and inter modulation distortion (IMD3) for a gm stage of a mixer while reducing flicker noise is disclosed. The transmitter may include a balanced mixer, a transconductance stage connected to the mixer, and a bias circuit. The bias circuit may include a programmable current source configured to provide a reference current. Further, the bias circuit may include a replica circuit configured to replicate a DC signal of the transconductance stage. The bias circuit may also include a bias transistor configured to level shift a bias signal obtained from a signal source based on the reference current and the DC signal of the transconductance stage as determined from the replica circuit.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 5, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Aritra Dey, Tolga Pamir, Mostafa Haroun
  • Patent number: 11349441
    Abstract: An audio driver circuit includes a modulator circuit configured to receive an audio input signal and produce a first modulated digital pulse signal. The first modulated digital pulse signal has a magnitude that switches between a supply power voltage and a supply ground voltage. The audio driver circuit also includes a switched driver circuit coupled to the modulator circuit to receive the first modulated digital pulse signal and configured to provide a second modulated digital pulse signal for driving an MOS (metal oxide semiconductor) output transistor. The second modulated digital pulse signal has a same timing pattern as the first modulated digital pulse signal and has a magnitude that tracks linearly with the magnitude of the audio input signal.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: May 31, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Peter Holzmann
  • Patent number: 11342888
    Abstract: According to an aspect, there is provided a method for power-amplification of a transmission signal, comprising: obtaining the transmission signal with phase and amplitude modulation; generating a power-amplified polar signal for approximating a power-amplified transmission signal by power-amplifying a first constant-envelope signal with one of two or more first amplification factors based on the transmission signal; generating an outphasing pair of a first power-amplified outphasing signal and a second power-amplified outphasing signal based on the transmission signal; and combining the power-amplified polar signal, the first power-amplified outphasing signal and the second power-amplified outphasing signal to provide the power-amplified transmission signal.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 24, 2022
    Assignee: NOKIA SOLUTIONS AND NETWORKS OY
    Inventors: Jerry Lemberg, Mikko Martelius, Marko Kosunen, Enrico Roverato, Kari Stadius, Jussi Ryynänen
  • Patent number: 11329618
    Abstract: Differential control circuitry configured to control the operation of a power converter. The control circuitry of this disclosure is configured to receive two differential feedback signals from a fully differential amplifier. The amplifier receives an output voltage (Vout) from the switched mode power supply as well as a reference voltage (Vref). When Vout is less than Vref, the control circuitry may output a pulse width modulation (PWM) control signal to the switched mode power supply with a duty cycle of the PWM control signal based on a relative difference between a positive difference voltage and a negative difference voltage. When Vout is greater than Vref, the control circuitry may output a pulse frequency modulation (PFM) control signal to the switched mode power supply with a switching time of the PFM control signal based on a relative difference between the positive difference voltage and the negative difference voltage.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: May 10, 2022
    Assignee: Infineon Technologies AG
    Inventors: Davide Dal Bianco, Cristian Garbossa
  • Patent number: 11329617
    Abstract: Class-D amplifiers and modulators therefor provide control of the DC operating point of the outputs of the amplifiers. The modulators generate a sum and difference signal using combiners and introduce the sum signal to a reference input of the quantizer, while the quantization input of the quantizer receives the difference signal. A difference mode loop filter circuit may filter the difference signal and a common mode loop filter may filter the sum signal. Outputs of the quantizer operate a pair of switching circuits to provide either a differential output with the sum signal set to a constant voltage and the difference signal provided by the signal to be reproduced, or a pair of single-ended outputs with the individual input signals used to generate the sum and difference signal, and selection of a differential or dual single-ended operating mode may be performed by a control circuit that reconfigures the combiners.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: May 10, 2022
    Assignee: CIRRUS LOGIC, INC.
    Inventors: Cory J. Peterson, Chandra Prakash, Ramin Zanbaghi, Eric Kimball
  • Patent number: 11323082
    Abstract: A class-D amplifier configured to adjust at least one input signal to at least one output signal. The class-D amplifier comprises: a loop filter, configured to receive the input signal; a PWM circuit, configured to generate at least one PWM signal; a summing circuit, coupled between an output of the loop filter and an input of the PWM circuit; an output circuit operating at a supply voltage, configured to generate the output signal responding to the PWM signal; and a supply voltage filter, configured to monitor the supply voltage to generate a filtered signal to the summing circuit. The summing circuit is configured to sum the output of the loop filter and the filtered signal to adjust a common-mode level of the input of the PWM circuit.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: May 3, 2022
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Yang-Jing Huang, Shao-Ming Sun, Jhe-Jia Jhang
  • Patent number: 11297421
    Abstract: A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: April 5, 2022
    Assignee: Beken Corporation
    Inventors: Desheng Hu, Donghui Gao, Jiazhou Liu, Dawei Guo
  • Patent number: 11296685
    Abstract: A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: April 5, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Ramin Zanbaghi, Anuradha Parsi, Kyehyung Lee, John L. Melanson
  • Patent number: 11290071
    Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: March 29, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Ramin Zanbaghi, Cory J. Peterson, Anand Ilango, Eric Kimball
  • Patent number: 11271532
    Abstract: This application relates to an amplifier selectively operable in first or second modes. The first mode is a BTL mode with first and second output drivers (103p, 103n) both active to generate respective driving signals that vary with an input signal. The second mode is an SE mode, where the first output driver (103p) is active to generate a driving signal at and the output of the second driver (103n) is held constant. A controller (201) selectively controls the mode based on an indication of output signal amplitude. In the first mode, a ratio of magnitude of the two driving signals varies with the indication of output signal amplitude, i.e. the magnitudes of the two driving signals may vary so as to be not equal.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: March 8, 2022
    Assignee: Cirrus Logic, Inc.
    Inventor: John P. Lesso
  • Patent number: 11255718
    Abstract: Certain implementations of the disclosed technology may include systems and methods for extending a frequency response of a transducer. A method is provided that can include receiving a measurement signal from a transducer, wherein the measurement signal includes distortion due to a resonant frequency of the transducer. The method includes applying a complementary filter to the measurement signal to produce a compensated signal, wherein applying the complementary filter reduces the distortion to less than about +/?1 dB for frequencies ranging from about zero to about 60% or greater of the resonant frequency. The method further includes outputting the compensated signal.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: February 22, 2022
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Joe VanDeWeert, Adam Hurst, Joseph Carter, Douglas R. Firth, Alan R. Szary
  • Patent number: 11258411
    Abstract: A Class D amplifier having an integrating primary amplifier with an internal feedback, the amplifier further comprising a feedback loop with a filter of at least second order.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: February 22, 2022
    Assignee: PURIFI APS
    Inventors: Bruno Putzeys, Lars Risbo
  • Patent number: 11251754
    Abstract: A clipping detector circuit includes a timer circuit and a counter circuit. The timer circuit is configured to monitor a time period elapsing since a last occurrence of an edge in a PWM signal, assert a first signal when the time period elapses, and de-assert the first signal and reset the time period as a result of an edge occurring in the PWM signal. The counter circuit is configured to determine a number of pulses in the PWM signal since the last de-assertion of the first signal, and assert a second signal when the number of pulses in the PWM signal since the last de-assertion of the first signal reaches m pulses. The clipping detector circuit is configured to generate a clipping detection signal indicative of whether the pulse-width modulated signal is clipped or not as a function of the first signal and the second signal.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: February 15, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Noemi Gallo, Edoardo Botti
  • Patent number: 11245369
    Abstract: An integrated circuit includes a die that includes a circuit configured to generate a PWM signal in response to a first clock signal, and a first set of pads configured to provide amplified PWM signals to external filters. An amplifier stage is configured to provide the amplified PWM signals. The die includes two pads configured to be coupled to an external inductor, and a second set of pads configured to provide regulated voltages. An electronic converter circuit is configured to generate the regulated voltages to supply the amplifier stage. The electronic converter circuit includes a control circuit configured to drive electronic switches in response to a second clock signal to regulate the regulated voltages to a respective target value. The die includes a control block to synchronize the switching activity of the electronic switches with the switching activity of the amplifier stage.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: February 8, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Edoardo Botti, Tommaso Barbieri, Davide Luigi Brambilla, Cristiano Meroni
  • Patent number: 11245368
    Abstract: A class D amplifier includes a self-oscillating class D amplification circuit that is driven by an output current signal; and a voltage-current converting circuit that outputs an output current signal in response to an input signal voltage and an output signal voltage from a feedback signal voltage.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: February 8, 2022
    Assignee: Yamaha Corporation
    Inventors: Takeshi Togawa, Masao Noro
  • Patent number: 11245370
    Abstract: A Class-D amplifier includes a plurality of power rails, a quantizer, and a driver stage. The quantizer and the driver stage have a combined gain. For each power rail of the plurality of power rails, the Class-D amplifier senses a voltage value for the power rail and determines a ramp amplitude based on the sensed voltage value. The Class-D amplifier concurrently switches from the driver stage using a first power rail to a second power rail of the plurality of power rails and switches from the quantizer using the ramp amplitude associated with the first power rail to using the ramp amplitude associated with the second power rail so that the combined gain is constant.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: February 8, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Zhaohui He, Ruoxin Jiang, Rahul Singh
  • Patent number: 11239869
    Abstract: A multistage Doherty power amplifier and a transmitter are provided, and the multistage Doherty power amplifier includes: a generalized carrier amplifier, which is a nested 2-way inverted Doherty sub amplifier, and a generalized peaking amplifier, connected to the generalized carrier amplifier, which is a nested single ended sub amplifier or a nested 2-way normal Doherty sub amplifier, the generalized carrier amplifier and the generalized peaking amplifier are arranged in a generalized 2-way inverted Doherty power amplifier form. With the multistage Doherty power amplifier, signal power probability distribution function (PDF) oriented for a cost-effective multi stage Doherty PA design is applied, and 2-way normal and inverted Doherty PA cells are used as basic units to construct multistage Doherty PA with gain extension effect.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: February 1, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Zhancang Wang
  • Patent number: 11240606
    Abstract: Systems and methods of audio processing and control for improved audibility and performance in a parametric loudspeaker system. The parametric loudspeaker system includes a parametric loudspeaker providing a capacitive load, an output stage having a plurality of switches interconnected in a bridge configuration and connected to the capacitive load of the parametric loudspeaker, and a controller operative to generate a series of pulse width modulation (PWM) pulses, and to generate a plurality of control signals synchronized with the series of PWM pulses for switchingly controlling the plurality of switches in the bridge configuration, thereby driving the capacitive load of the parametric loudspeaker.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: February 1, 2022
    Inventor: Frank Joseph Pompei
  • Patent number: 11239763
    Abstract: The transformer includes a core. The transformer includes a first rectifier voltage connection winding wound on the core operable to conduct with the first rectifier voltage connection. The transformer includes a second rectifier voltage connection winding wound on the core operable to conduct with the second rectifier voltage connection, the second rectifier voltage connection winding operable to form a first magnetic flux with the first rectifier voltage connection winding. The transfer includes a first rectifier return connection winding wound on the core operable to conduct with the first rectifier return connection. The transformer includes a second rectifier return connection winding wound on the core operable to conduct with the second rectifier return connection, the second rectifier return connection winding operable to form a second magnetic flux with the first rectifier return connection winding and operable to form a net flux with the first rectifier voltage connection winding.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: February 1, 2022
    Assignee: HAMILTON SUNDSTRAND CORPORATION
    Inventor: Frank Z. Feng
  • Patent number: 11228282
    Abstract: An H-bridge power amplifier arrangement with envelope tracking is disclosed. The power amplifier arrangement comprises four elements form the four corner bars of a first H-bridge structure with a load formed as the cross bar of the first H-bridge structure. The power amplifier arrangement further comprises a rectifier circuit coupled between the first positive power supply and the third positive power supply configured to recycle the sinking envelope current.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 18, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Zhancang Wang
  • Patent number: 11228466
    Abstract: An isolation circuit that isolates a driver circuit that is biased at a first common mode voltage from a detection circuit that is biased at a second common mode voltage using isolation capacitors. The detection circuit includes a transimpedance amplifier having improved susceptibility to transient common-mode input signals and improved insensitivity to parasitic capacitance on the isolation capacitor terminals. Included within the transimpedance amplifier are circuits for mirroring current to convert the input current from the isolation capacitors into a voltage value and to amplify that voltage value. The transimpedance amplifier outputs a differential voltage value that is held by a latch circuit so that a comparator in the detection circuit can process the differential voltage value and output a differential signal with fully restored logic levels.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: January 18, 2022
    Assignee: Allegro MicroSystems, LLC
    Inventors: Craig S. Petrie, Srujan Shivanakere
  • Patent number: 11228284
    Abstract: A method for controlling one or more parameters of an amplifier system may include receiving an indication of a physical quantity associated with the amplifier system, determining one or more parameters of the amplifier system in response to the indication, and causing the amplifier system to operate in accordance with the one or more parameters.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: January 18, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Eric Lindemann, Itisha Tyagi
  • Patent number: 11211903
    Abstract: An over charge protection method applied to a voltage converter which can operate in a quaternary modulation mode (Q mode) or a ternary modulation mode (T mode). The over charge protection method comprises: (a) determining whether the voltage converter operates in the Q mode or the T mode; and (b) setting a current threshold of the voltage converter to a first over current threshold if the voltage converter operates in the T mode; and (c) setting the current threshold to a second over current threshold if the voltage converter operates in the Q mode, wherein the first current threshold is smaller than the second over current threshold.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: December 28, 2021
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Ya-Mien Hsu, Deng-Yao Shih, Yang-Jing Huang
  • Patent number: 11194356
    Abstract: Techniques for efficient operation of a linear stage in an H-bridge system are provided. In an example, a linear stage can switch between voltage regulation and current regulation over a range of a command signal. The particular regulation mode can depend on the regulation mode of a switched stage of the H-bridge system. Efficiency can be realized by using current regulation of the linear stage when the output voltage of the linear stage moves away from the voltage of a supply rail. Such a control scheme can reduce the voltage across the linear stage for a larger range of the command signal resulting in less heat dissipation of the linear stage compared to conventional control of H-bridge linear stages.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 7, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Fu Sun, Xiaohua Su, Stephen Todd Van Duyne, Yanfeng Lu, Mathew Todd Wich
  • Patent number: 11196392
    Abstract: A device having device function circuitry configured to receive a device signal and output a modified device signal is disclosed. The device includes a device temperature sensor configured to generate a device temperature signal that is proportional to a temperature of the device function circuitry. The device function circuitry is further configured to maintain power dissipation of the device function circuitry to below a predetermined safe power dissipation level in response to a control signal that is generated based upon the device temperature signal.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 7, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Chong Woo
  • Patent number: 11189140
    Abstract: Described is a system for producing an acoustic field from a plurality of ultrasonic transducer arrays, each of which has known relative positions and orientations. The acoustic field comprises a carrier wave and a modulated wave. The carrier wave has a plurality of modulated focal areas. A plurality of control points having a known spatial relationship relative to at least one of the plurality of ultrasonic transducer arrays is used. The plurality of ultrasonic transducer arrays are calibrated by using the relative position of each of the plurality of ultrasonic transducer arrays.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: November 30, 2021
    Assignee: ULTRAHAPTICS IP LTD
    Inventors: Benjaimin John Oliver Long, Michele Iodice, Thomas Andrew Carter
  • Patent number: 11184198
    Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 23, 2021
    Assignee: Rambus Inc.
    Inventors: Marko Aleksic, Pravin Kumar Venkatesan, Simon Li, Nikhil Vaidya
  • Patent number: 11183975
    Abstract: A supply voltage conditioning circuit comprises a differential amplifier, a comparator, a sample and hold (S/H) circuit, and a delay circuit. The differential amplifier receives an input supply voltage and a reference voltage, and outputs a difference signal. The comparator receives the difference signal and a value representative of a noise margin, and outputs a control signal indicative of whether the difference signal is greater than the value representative of the noise margin. The S/H circuit samples the input supply voltage in response to the control signal indicating the difference signal is greater than the noise margin, and outputs a substantially noise free supply voltage. This allows the output supply voltage to track underlying changes in the input supply voltage but filter out noise in the input supply voltage. The delay circuit receives and delays the output supply voltage to generate the reference voltage.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: November 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sahiti Priya C
  • Patent number: 11183932
    Abstract: A switch-mode AC-DC power converter includes a pair of input terminals, a pair of output terminals, and four switches coupled in a bridgeless totem-pole circuit arrangement between the pair of input terminals and the pair of output terminals. A control circuit is coupled to the four switches and configured to, during a cycle of an AC voltage input, turn on the first switch, turn off the second switch, and apply pulse-width modulation (PWM) control signals to the third and fourth switches. The control circuit is also configured to, during a zero crossing of the AC voltage input, supply a PWM control signal to the fourth switch to reduce a rate of voltage change across the second switch at the zero crossing to reduce common mode noise of the power converter.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: November 23, 2021
    Assignee: Astec International Limited
    Inventors: Zhihua Gu, Siu Chik Wong, Kim Ly Kha
  • Patent number: 11177785
    Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: November 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shaik Asif Basha, Mohit Chawla, Jasjot Singh Chadha
  • Patent number: 11159128
    Abstract: A device having device function circuitry configured to receive a device signal and output a modified device signal is disclosed. The device includes a device temperature sensor configured to generate a device temperature signal that is proportional to a temperature of the device function circuitry. The device function circuitry is further configured to maintain power dissipation of the device function circuitry to below a predetermined safe power dissipation level in response to a control signal that is generated based upon the device temperature signal.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: October 26, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Chong Woo
  • Patent number: 11159132
    Abstract: The technology described in this document can be embodied in an audio power amplifier that includes a first channel and a second channel. Each of the first channel and the second channel includes an input to receive an input signal, a pair of switching devices, drive circuitry for driving the pair of switching devices to produce a signal, and an output filter to filter the signal from the pair of switching devices. The output filter is configured to provide the filtered signal to an audio load. Each of the first channel and the second channel includes a voltage feedback loop to provide a voltage of the filtered signal to a voltage controller of the audio power amplifier, and a current feedback loop to provide a current of the filtered signal to a current controller of the audio power amplifier. The audio power amplifier includes a summer for combining the input of the first channel and the input of the second channel when an output of the first channel is connected to an output of the second channel.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Bose Corporation
    Inventor: Zoran Coric
  • Patent number: 11152927
    Abstract: A low distortion triangular wave generator circuit generates a triangular wave signal by performing integration on an integration capacitor via a charging current and a discharging current during a charging period and a discharging period within a switching period of an external clock signal. A time length of the charging period is identical to a time length of the discharging period. A common mode related signal related to a common mode characteristic of the triangular wave signal is generated. An adjusting signal is generated according to a difference between the common mode related signal and a predetermined DC (direct current) level. The adjusting signal adjusts at least one of the charging current and the discharging current via feedback mechanism such that the triangular wave signal is a symmetrical triangular wave, and an average voltage of the triangular wave signal is equal to a target DC level.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: October 19, 2021
    Inventors: Yi-Kuang Chen, Ming-Jun Hsiao
  • Patent number: 11133785
    Abstract: An amplifier for headphones including a current digital-to-analog converter (DAC) configured to output a current based on a digital audio input signal, an output electrically connected to a speaker and configured to output an output signal to the speaker, and a pulse width modulation (PWM) loop configured to receive an error signal, the error signal based on a difference between the current from the current DAC and a current of the output signal, and generate the output signal based on the error signal. The PWM loop includes an analog-to-digital converter (ADC) configured to receive an analog signal based on the current from the current DAC and output a digital signal representing the analog signal, and an encoder configured to receive the digital signal and output a pulse having a width based on the analog signal.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 28, 2021
    Assignee: AVNERA CORPORATION
    Inventor: Wai Laing Lee
  • Patent number: 11128270
    Abstract: A class-D amplifier with multiple “nested” levels of feedback. The class-D amplifier surrounds an inner feedback loop, which takes the output of a switching amplifier and corrects for errors generated across the switching amplifier, with additional feedback loops that also take the output of the switching amplifier.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: September 21, 2021
    Assignee: QSC, LLC
    Inventor: Anders Lind
  • Patent number: 11121682
    Abstract: A boost class-D amplifier includes a PWM modulator, a boost level controller coupled to the PWM modulator, a pre-driver coupled to the PWM modulator and the boost level controller, a system voltage source, an inductor coupled to the system voltage source, a first switch, a second switch, a third switch, a fourth switch, a first diode coupled between the third switch and a voltage ground, a second diode coupled between the fourth switch and the voltage ground, and a capacitor coupled between the first switch and the fourth switch. The PWM modulator is for receiving an input signal and generating a first modulated signal accordingly. The boost level controller is for receiving the first modulated signal and generating a second modulated signal accordingly. The pre-driver is for receiving the first modulated signal and the second modulated signal and generating control signals accordingly.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: September 14, 2021
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Che-Wei Hsu, Wun-Long Yu, Deng-Yao Shih
  • Patent number: 11119144
    Abstract: A method for performing a Bode measurement on a device under test having a specified working input range and a specified working output range using a measurement system comprising: receiving at least one input boundary parameter of the working input range and at least one output boundary parameter of the output working range; generating a first stimulus signal using a stimulus signal generator of the measurement system based on the at least one input boundary parameter; feeding the first stimulus signal to an input of the device under test; and measuring an output signal of the device under test using a measurement unit of the measurement system in a measurement range based on the at least one output boundary parameter obtaining a measurement result. Further, a measurement setup is shown.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: September 14, 2021
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Sven Barthel
  • Patent number: 11121690
    Abstract: This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (?) from the output signal and the input signal. In various embodiments the extent to which the error signal (?) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 14, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: John Paul Lesso, Toru Ido
  • Patent number: 11115083
    Abstract: A polar transmitter for an RFID reader and a system using the polar transmitter are disclosed. An RFID system according to at least some embodiments of the invention includes a polar transmitter, a receiver to receive responses from RFID tags, and a coupler connected to the polar transmitter, the receiver and one or more antennas. In at least some embodiments, the polar transmitter of the RFID system includes an envelope amplifier and a power amplifier. In some examples, a polar transmitter includes direct conversion of baseband data to provide angle modulation plus drive modulation. In addition to the envelope amplifier and power amplifier, the polar transmitter in such an example includes a quadrature modulator connected to the power amplifier to provide modulation for the transmitter output signal using a Cartesian input signal.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: September 7, 2021
    Assignee: CLAIRVOYANT TECHNOLOGY, INC.
    Inventor: Thomas J. Frederick
  • Patent number: 11101778
    Abstract: The present disclosure relates to Class D amplifier circuitry comprising: an input for receiving an input signal; first and second output nodes for driving a load connected between the first and second output nodes. A first driver stage is provided for switching the first node between a first supply rail and a second supply rail, and a second driver stage is provided for switching the second node between the first supply rail and the second supply rail. The Class D amplifier circuitry also includes first driver control circuitry configured to receive a first carrier wave and control the switching of the first driver stage based in part on the first carrier wave; second driver control circuitry configured to receive a second carrier wave and control the switching of the second driver stage based in part on the second carrier wave; and a carrier wave generator configured to provide the first carrier wave and the second carrier wave.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 24, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: John Paul Lesso, Toru Ido
  • Patent number: 11088662
    Abstract: A digital amplifier that minimizes and restricts an analog signal system and uses a feedback signal and a dither signal is achieved. A pulse width modulator that adjusts a pulse width of a digital signal, a switching circuit that amplifies an output signal from the pulse width modulator, and a feedback signal generation unit that generates a feedback signal based on an output signal from the switching circuit are included, the pulse width modulator adjusts the pulse width of the digital signal with reference to the feedback signal, and the feedback signal generation unit includes a first amplifier that outputs a first amplified signal in which a difference between the output signal from the switching circuit and one of a reference voltage and a dither signal is amplified and a second amplifier that amplifies a difference between the first amplified signal and the other of the dither signal and the reference voltage and outputs the amplified difference as the feedback signal.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: August 10, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tsuyoshi Nakahira, Akihiro Nishigaki
  • Patent number: 11076249
    Abstract: An electronic device is provided. The electronic device includes an integrated circuit (IC); a sonic vibrator arranged on one side of the IC; a speaker; and a processor configured to: control the speaker based on a sound signal, and filter a low-frequency band signal that is less than or equal to a threshold frequency from the sound signal and provide the low-frequency band signal to the sonic vibrator.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyeungrae Cho
  • Patent number: 11070178
    Abstract: A class D power amplifier with novel design is provided. The amplifier includes an input stage, a periodic signal generator, a comparator, a power output stage, and a boost circuit. The input stage is coupled to a first supply voltage. The periodic signal generator generates a periodic signal and a reference signal. The power output stage is coupled to a second supply voltage. The boost circuit compares an output of the input stage with the reference signal, and thereby adjusts a value of the second supply voltage. The value of the second supply voltage is larger than a value of the first supply voltage. The reference signal is proportional to an amplitude of the periodic signal, and the amplitude of the periodic signal is determined by the value of the second supply voltage.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: July 20, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Shao-Ming Sun
  • Patent number: 11070179
    Abstract: An apparatus measures a speaker impedance. A DAC converts a known digital input signal to an audio frequency first analog voltage signal. Resistors with known resistance attenuate the first analog voltage signal to generate a current. The known resistance effectively determines the current because the known resistance is high relative to the speaker impedance. The current is sourced into the speaker to generate a second analog voltage signal. The known resistance is sufficiently high to cause the second analog voltage signal to be inaudible as transduced by the speaker. An amplifier amplifies the second analog voltage signal with a known gain to generate a third analog voltage signal. An ADC converts the third analog voltage signal to a digital output signal. A processing element calculates the impedance of the speaker proportional to the digital output signal based on the known digital input signal, the known resistance, and the known gain.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: July 20, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Frank Cheng, Ruoxin Jiang, Zhong You
  • Patent number: 11063566
    Abstract: An RF module with improved testing capabilities is provided. The module has a first switch with signal outputs and an additional auxiliary connection connected to an auxiliary terminal. The auxiliary terminal can be connected to an RF filter while a power amplifier is decoupled from the filter.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 13, 2021
    Assignee: Snaptrack, Inc.
    Inventors: Miguel Angel Falagan Bobillo, Andreas Detlefsen
  • Patent number: 11062650
    Abstract: A sensing circuit of a display device is provided. The sensing circuit includes a chopper circuit, a first operational amplifier and a filter. The chopper circuit is configured to receive a sensing input signal of the display device and modulate the sensing input signal. The first operational amplifier is coupled to the chopper circuit. The first operational amplifier is configured to receive the modulated sensing input signal and output the modulated sensing input signal to the chopper circuit. The chopper circuit is further configured to demodulate the modulated sensing input signal from the first operational amplifier and output the demodulated sensing input signal. The filter is coupled to the chopper circuit. The filter is configured to filter the demodulated sensing input signal from the chopper circuit and output the filtered sensing input signal as a sensing output signal. A source driver including the sensing circuit is also provided.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: July 13, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chih-Yuan Chang, Feng-Lin Chan
  • Patent number: 11057009
    Abstract: A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: July 6, 2021
    Assignee: Apple Inc.
    Inventors: Utku Seckin, Hanwen Yang