Abstract: A nuclear magnetic resonance (NMR) power supply system and method are disclosed. The architecture adopts a two-stage topology to reduce the required capacitance by over ten times, leading to a four-fold improvement in power density. The first stage is an isolated converter that only supplies average power, therefore input filter and transformer sizes can be reduced. The second stage is a fast response DC-DC converter followed by a RF transmitter to produce a pulsed RF signal, so that the mid-point voltage after the first stage can be allowed to droop considerably, leading to much smaller sized capacitors. These and other embodiments enforce the isolated converter to only transfer average power, which reduces the power rating and the volume of the system's transformer.

Abstract: Circuits for protecting devices, such as gallium nitride (GaN) devices, and operating methods thereof are described. The circuits monitor a magnitude of the current in a device and reduce the magnitude of the current and/or shut down the device responsive to the magnitude of the current exceeding a threshold. These circuits safeguard devices from damaging operating conditions to prolong the operating life of the protected devices.

Abstract: An apparatus for amplifying an audio source includes a speaker and a chip. The chip includes a processor configured to generate a signal and an amplifier element configured to amplify the signal into an amplified signal. The chip further includes a current monitor configured to monitor the current of the amplified signal prior to the amplified signal being output from the chip to the speaker and a voltage monitor configured to monitor the voltage of the amplified signal prior to the amplified signal being output from the chip to the speaker. The processor of the chip is configured to control a power of the amplified signal output from the chip to the speaker based at least on the current and the voltage.

Abstract: The present disclosure provides a current detection circuit for a loudspeaker 500, comprising a first detection resistor RSP, a second detection resistor RSN, a sampling selection circuit 100, an input selection circuit 200, and a processing circuit 300. By adding the sampling selection circuit 100 and the input selection circuit 200, voltages on two ends of the corresponding detection resistors (RSP, RSN) are sampled according to the fact that potential differences of an output stage VOP and an output stage VON of a class-D audio power amplifier 400 are in different semi-periods, and the current of the loudspeaker 500 is obtained through processing, thereby detecting the current of the loudspeaker 500 without adding an anti-clipping distortion function to the class-D audio power amplifier 400.

Abstract: An adaptive sample and hold circuit for signal amplifier range selection is presented. The adaptive sample and hold circuit has an input for receiving an input signal and an output for providing a sample-and-hold-voltage. It also includes a sample-and-hold-capacitor to generate the sample-and-hold-voltage from the input signal, and a range detector. The range detector is adapted to identify a range of the input signal and to adjust a voltage at the sample-and-hold-capacitor based on the range of the input signal to maintain the sample-and-hold-voltage within a predetermined voltage span.

Abstract: A method for adjusting a parameter of an audio service and a terminal includes obtaining, by the terminal, first information, where the first information includes at least one of a first battery level or a first temperature, and adjusting, by the terminal, a parameter of an audio service of the terminal when a first condition is met, where the first condition includes one or more of the first battery level is less than a first preset threshold or greater than a second preset threshold, or the first temperature is less than a third preset threshold or greater than a fourth preset threshold.

Abstract: An analog front end circuit with pulse width modulation current compensation comprises sensing a current condition and determining if the current condition is a positive or negative current condition. An appropriate control signal is determined according to the current condition and sent to turn on a positive current electronic switch if the current condition is a negative current condition or sent to turn on a negative current electronic switch if the current condition is a positive current condition. A positive compensation current flows to offset negative parasitic current when the positive current electronic switch is turned on and a negative compensation current flows to offset positive parasitic current when the negative current electronic switch is turned on. A master control unit utilizes pulse width modulation signals of various widths associated with various current conditions to be sent to turn on the positive electronic switch or the negative electronic switch.

Abstract: An assembly for powering a first circuit, including at least one ferrite bead in series with a diode between a first terminal of application of a first voltage and a first terminal of said first circuit.

Abstract: The application describes a switched driver (401) for outputting a drive signal at an output node (402) to drive a load such as a transducer. The driver receives respective high-side and low-side voltages (VinH, VinL) defining an input voltage at first and second input nodes and has connections for first and second capacitors (403H, 403L). A network of switching paths is configured such that each of the first and second capacitors can be selectively charged to the input voltage, the first input node can be selectively coupled to a first node (N1) by a path that include or bypass the first capacitor, and the second input node can be selectively coupled to a second node (N2) by a path that includes or bypasses the second capacitor. The output node (402) can be switched between two switching voltages at the first or second nodes. The driver is selectively operable in different operating modes, where the switching voltages are different in each of said modes.

Abstract: A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.

Abstract: A method for powering an audio amplifier includes receiving an input audio signal in an audio signal processor, delaying the input audio signal in the audio signal processor to generate a delayed audio signal, predicting a power demand estimate by analyzing the input audio signal to calculate the power demand estimate in the audio signal processer, and selecting, by the audio signal processor, power conversion settings for a DC to DC converter on the basis of the power demand estimate. The method further includes supplying power input to the DC to DC converter, converting the power input in accordance with the power conversion settings to provide a power output, powering the audio amplifier using the power output, and supplying the delayed audio signal to the audio amplifier from the audio signal processor to generate an amplified audio signal.

Abstract: Examples of amplifiers and nth-order loop filters thereof are configured to enable fast and robust recovery from saturation, while limiting signal distortion at or near full power delivery across multiple process and temperature corners. An example nth-order loop filter comprises n series-coupled resistor-capacitor (RC) integrators. In an example, each of the second RC integrator to the (n?1)th RC integrator has a reset mechanism responsive to a reset signal output from a reset controller when an input signal overload condition is detected at the input. Upon detecting the overload condition, each of the third RC integrator to the (n?1)th RC integrator is hard reset, the nth RC integrator is not reset, and a controlled reset is performed on the second RC integrator to recover from saturation caused by the signal overload condition, while maintaining the output signal below the 1% total harmonic distortion (THD) level at or near full power delivery.

Abstract: Provided are a frame configuring unit configured to configure a frame using a plurality of orthogonal frequency-division multiplexing (OFDM) symbols, by allocating time resources and frequency resources to a plurality of transmission data, and a transmitter which transmits the frame. The frame includes a first period in which a preamble which includes information on a frame configuration of the frame is transmitted, a second period in which a plurality of transmission data are transmitted by time division, a third period in which a plurality of transmission data are transmitted by frequency division, and a fourth period in which a plurality of transmission data are transmitted by time division and frequency division.

Abstract: An audio amplifier system is described herein, comprising: an amplifier adapted to amplify an audio signal and comprising an output enable/disable input, the amplifier further adapted to receive an output enable signal at the output enable/disable input that enables/disables an output of the amplifier; a Zobel network connected to the output of the audio amplifier and comprising a Zobel capacitor and a Zobel resistor arranged such that they form a high pass frequency filter function and wherein the Zobel network is adapted to be substantially resistive when a frequency of an audio signal output from the audio amplifier is within a first frequency range; a mirroring resistor connected in parallel to the Zobel resistor and adapted to mirror a power that is dissipated in the Zobel resistor, and wherein a printed circuit board upon which the mirroring resistor is located is adapted to conduct heat generated by the mirroring resistor; a negative temperature coefficient (NTC) resistor located in close proximity to

Abstract: An audio amplifier that implements current mode control without the use of an explicit or separate current mode sensor is disclosed. The audio amplifier may include a pair of feedback loops that provide current from a node located before an inductor of an output filter and current from a node located after the inductor of the output filter to an integrator circuit. The integrator circuit may be formed from existing circuitry of the audio amplifier controller. Thus, current mode control can be implemented without a separate current mode sensor.

Abstract: A power supply system controls the source impedance of a generator utilizing two amplifiers having asymmetrical power profiles in reference to a nominal load impedance that are diametrically opposite in reference to the nominal load impedance. Variations in power profiles may be achieved by using different topologies for each of the amplifiers or implementing a phase delay network. The output power from the first and second amplifiers may be combined using a combiner circuit or device and the output power from the combiner is transmitted to a plasma load. The output power of each amplifier may be independently controlled to alter one or more characteristics of the output power signal provided by the individual amplifiers. By changing the ratio of the output power of the first amplifier to the output power of the second amplified, the source impedance of the generators may be varied.

Abstract: A control method includes sequentially updating a next cycle pulse width modulation command for each of an upper switch and lower switch of a phase leg of a power converter according to an order defined by timing of a rising edge of the next cycle pulse width command for one of the switches relative to a rising edge of a previous cycle pulse width command for the one of the switches.

Abstract: The present disclosure relates to amplifier circuitry (300) that includes a linear amplifier stage (110) that receives an input signal and outputs a first drive signal to an output node (302) and a switching amplifier stage (130) operable to output a second drive signal to the output node (302). A controller (340) is selectively operable in a first dual-amplifier mode, in which switching of the switching amplifier stage is controlled based on a current of the first drive signal, such that the current of the first drive signal does not exceed a first current threshold magnitude; and at least one other mode, in which the controller controls the switching amplifier stage such that the current of the first drive signal may exceed the first current threshold magnitude. The controller (340) selectively controls the mode of operation based on an indication (SSL) of signal level of the output signal.

Abstract: An audio system includes an H-bridge. The audio system implements one or more techniques for ensuring a transistor within the H-bridge does not turn on in the event of the detection of a short-circuit on the output of the H-bridge. Other transistors within the H-bridge can turn and thus audio can still be played to a speaker.

Abstract: A power control system for audio power amplifiers, especially in the automotive segment, dynamically controlling the output voltage through the reading of the input and output currents, and other parameters, automatically adjusting the amplifier to the load and to the operation conditions, allowing that the amplifier always operates within the safe operation range.

Abstract: An exemplary system and method is disclosed employing a floating inverter amplifier comprising an inverter-based circuit comprising an input configured to be switchable between a floating reservoir capacitor during a first phase of operation and to a device power source during a second phase of operation. In some embodiments, the floating inverter amplifier is further configured for current reuse and dynamic bias. In other embodiments, the floating inverter amplifier is further configured with a dynamic cascode mechanism that does not need any additional bias voltage. The dynamic cascode mechanism may be used in combination with 2-step fast-settling operation to provide high-gain and high-speed noise suppression operation.

Abstract: In one aspect, a magnetic field sensor includes a plurality of tunneling magnetoresistance (TMR) elements that includes a first TMR element, a second TMR element, a third TMR element and a fourth TMR element. The first and second TMR elements are connected to a voltage source and the third and fourth TMR elements are connected to ground. Each TMR element has a pillar count of more than one pillar and the pillar count is selected to reduce the angle error below 1.0°.

Abstract: Isolated circuit systems are provided. The systems include a primary side circuit and a secondary circuit, electrically isolated from each other. The primary side and secondary side circuits each utilize a direct current (DC) reference signal. The primary side circuit may use the DC reference signal in a modulation operation. The secondary side circuit may use the DC reference signal in a demodulation operation. The DC reference signal may be sent from the primary side circuit to the secondary side circuit, or from the secondary side circuit to the primary side circuit.

Abstract: Various techniques are provided to reduce common mode disturbance associated with an amplifier, such as a class D amplifier. In one example, an amplifier includes a power stage configured to generate first and second PWM signals. The amplifier further includes an integration stage comprising input nodes configured to receive an input differential analog signal. The integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal. The amplifier further includes an active compensation circuit configured to provide a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode. Additional devices, systems, and methods are also provided.

Abstract: An audio device includes a network interface, an amplifier that amplifies an audio signal received through the network interface, and a processor configure to obtain an output value of a signal from the amplifier and sends the output value of the signal through the network interface.

Abstract: Current monitoring techniques are included in an electronic system that provides power to a load from a power output stage that supplies power to a load. Multiple current control devices form the power output stage in series with multiple sense resistors that provide corresponding sense voltages indicative of current provided through the multiple current control devices to the load in the same or different time intervals. A calibration control circuit controls injection of current through the multiple sense resistors individually and measures the corresponding sense voltages generated by the current to determine resistance values of the multiple sense resistors. A correction subsystem computes a first ratio of a first resistance to a second resistance and a second ratio of a third resistance to a fourth resistance of the multiple sense resistors, and controls compensation for a difference between the first ratio and the second ratio to remove the measurement error.

Abstract: A switch circuit provides a first output signal and a second output signal for switching between ternary modulation and quaternary modulation for a target device. A first output signal is provided from one of a first signal, a second signal and a ground signal according to an input signal and a duty signal, wherein the first signal is generated through performing a one-bit left-shift operation for the input signal, and the second signal is generated through adding the input signal and the duty signal. A second output signal is provided from one of a third signal, a fourth signal and the ground signal according to the input signal and the duty signal, wherein the third signal is generated through subtracting the input signal from the duty signal, and the fourth signal is generated through performing a two's-complement transformation and the one-bit left-shift operation for the input signal.

Abstract: An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage.

Abstract: An electronic actuator device and a control method thereof are provided. The electronic actuator device includes a plurality of first and second power switches and a driving circuit. The first power switches respectively provide a first reference voltage to a plurality of voltage receiving ends of a motor respectively according to a plurality of first control signals. The second power switches respectively provide a second reference voltage to the voltage receiving ends respectively according to a plurality of second control signals. The driving circuit generates the first and second control signals. In a braking operation, the first power switches are turned on during a plurality of first time periods, and the second switches are turned on during a plurality of second time periods that are alternate and non-overlapped with the first time periods. An interval time period is present between each adjacent two of the first and second time periods.

Abstract: A method and apparatus is provided for control of plural optical phase shifters in an optical device, such as a Mach-Zehnder Interferometer switch. Drive signal magnitude is set using a level setting input and is used for operating both phase shifters, which may have similar characteristics due to co-location and co-manufacture. A device state control signal selects which of the phase shifters receives the drive signal. One or more switches may be used to route the drive signal to the selected phase shifter. Separate level control circuits and state control circuits operating at different speeds may be employed. When the phase shifters are asymmetrically conducting (e.g. carrier injection) phase shifters, a bi-polar drive circuit can be employed. In this case, the phase shifters can be connected in reverse-parallel, and the drive signal polarity can be switchably reversed in order to drive a selected one of the phase shifters.

Abstract: An embodiment pulse-width modulation (PWM) modulator circuit comprises a first half-bridge stage having a first output node and a second half-bridge stage having a second output node. The first output node and the second output node are configured to have an electrical load coupled therebetween to apply thereto a PWM-modulated output signal. The circuit comprises a differential stage having input nodes configured to receive an input signal applied between the input nodes and produce a differential control signal for the first half-bridge stage and the second half-bridge stage. A current comparator is arranged intermediate the differential stage and the first and second half-bridge stages. The current comparator is configured to produce a PWM-modulated drive signal to drive the half-bridge stages as a function of the input signal applied between the input nodes in the differential stage.

Abstract: This application is generally related to methods and systems for improving amplifier performance. For example, the system includes two or more gain and phase modulators. The system also includes two or more component amplifiers operably coupled to, and downstream of, the power splitter, where each of the two or more component amplifiers is operably coupled to a respective one of the two or more gain and phase modulators. The system further includes a power combiner operably coupled to, and downstream of, the two or more component amplifiers, configured to output a power signal. The system even further includes a Walsh generator configured to generate and transmit first and second Walsh codes to each of the two or more gain and phase modulators. The first Walsh code is orthogonal to the second Walsh code. A first set of the first and second Walsh codes is inverted with respect to a second set of the first and second Walsh codes.

Abstract: An improved method of providing high burst power to audio amplifiers from limited power sources, using parallel power paths to increase system efficiency without need for a power path controller, thus utilizing a simplified circuit operation and maximizing average power available for both the amplifier and supporting circuitry.

Abstract: A class-D amplifier with low pop-click noise is shown. A loop filter, a control signal generator, a first power driver, and a first feedback circuit are provided within the class-D amplifier to establish a first loop for signal amplification. The class-D amplifier further has a settling circuit and a pre-charging circuit. The settling circuit is configured to be combined with the loop filer and the control signal generator to establish a second loop to settle the loop filter and the control signal generator before the first loop is enabled. The pre-charging circuit is configured to pre-charge a positive output terminal and a negative output terminal of the first power driver.

Abstract: One embodiment provides a system comprising a single DC voltage source and a Class-D amplifier comprising at least one DC/DC converter operated by the single DC voltage source. The amplifier is configured to receive an input signal for power amplification, and generate, via the at least one DC/DC converter, a DC output voltage that approaches or exceeds a DC supply voltage from the single DC voltage source. A gain of the amplifier is a ratio of the output voltage level to the input signal. A steady-state operating point of the at least one DC/DC converter is zero output.

Abstract: This invention provides compact Power Amplifiers with improved efficiency of the circuitry and improved heat dissipation, together achieved much smaller enclosure size for use in modern installations requiring reduced height such as between the thin flat TV and wall, under the table or on the projector pole or in ceiling box and the like.

Abstract: An amplifier includes an input circuit configured to receive an analog input signal and a feedback signal, and output an analog error signal based on the analog input signal and the feedback signal. An ADC is configured to convert the analog error signal into a digital signal in a phase domain. A digital control circuit is configured to generate a digital control signal based on the digital signal in the phase domain. An output circuit is configured to generate an amplified output signal based on the digital control signal, and a feedback circuit is configured generate the feedback signal based on the amplified output signal.

Abstract: Amplifier architecture that allows low-cost class-D audio amplifiers to be compatible with ultrasonic signals, as well as loads presented by thin-film ultrasonic transducers. The amplifier architecture replaces the traditional capacitor used as an output filter in the class-D amplifier with the natural capacitance of the ultrasonic transducer load, and employs relative impedance magnitudes to create an under-damped low-pass filter that boosts voltage in the ultrasonic frequency band of interest. The amplifier architecture includes a secondary feedback loop to ensure that correct output voltage levels are provided.

Abstract: An amplifier, such as a Class D amplifier, having one or more feedback loops comprising a path from the input to the primary amplifier input, where the paths comprise a low pass filter and a compensator which is disabled when the primary amplifier clips.

Abstract: A semiconductor device includes: a first buffer at which a predetermined signal is input and that outputs a first output signal; a second buffer at which an inverted signal of the predetermined signal is input and that outputs a second output signal; and a short circuit detection circuit that, in accordance with a potential difference between the first output signal and the second output signal, outputs a short circuit evaluation signal evaluating whether or not there is a ground fault in at least one of a first terminal at an output side of the first buffer or a second terminal at an output side of the second buffer or evaluating whether or not there is a short circuit between the first terminal and the second terminal.

Abstract: This application relates to amplifier circuitry, in particular class-D amplifiers, operable in open-loop and closed-loop modes. An amplifier (300) has a forward signal path for receiving an input signal (SIN) and outputting an output signal (SOUT) and a feedback path operable to provide a feedback signal (SFB) from the output. A feedforward path provide a feedforward signal (SFF) from the input and a combiner (105) is operable to determine an error signal (?) based on a difference between the feedback signal and the feedforward signal. The feedforward comprises a compensation module (201) configured to apply a controlled transfer function to the feedforward signal in the closed-loop mode of operation, such that an overall transfer function for the amplifier is substantially the same in the closed-loop mode of operation and the open-loop mode of operation.

Abstract: A transmitter that reduces 3rd order harmonic (HD3) and inter modulation distortion (IMD3) for a gm stage of a mixer while reducing flicker noise is disclosed. The transmitter may include a balanced mixer, a transconductance stage connected to the mixer, and a bias circuit. The bias circuit may include a programmable current source configured to provide a reference current. Further, the bias circuit may include a replica circuit configured to replicate a DC signal of the transconductance stage. The bias circuit may also include a bias transistor configured to level shift a bias signal obtained from a signal source based on the reference current and the DC signal of the transconductance stage as determined from the replica circuit.

Abstract: An audio driver circuit includes a modulator circuit configured to receive an audio input signal and produce a first modulated digital pulse signal. The first modulated digital pulse signal has a magnitude that switches between a supply power voltage and a supply ground voltage. The audio driver circuit also includes a switched driver circuit coupled to the modulator circuit to receive the first modulated digital pulse signal and configured to provide a second modulated digital pulse signal for driving an MOS (metal oxide semiconductor) output transistor. The second modulated digital pulse signal has a same timing pattern as the first modulated digital pulse signal and has a magnitude that tracks linearly with the magnitude of the audio input signal.

Abstract: According to an aspect, there is provided a method for power-amplification of a transmission signal, comprising: obtaining the transmission signal with phase and amplitude modulation; generating a power-amplified polar signal for approximating a power-amplified transmission signal by power-amplifying a first constant-envelope signal with one of two or more first amplification factors based on the transmission signal; generating an outphasing pair of a first power-amplified outphasing signal and a second power-amplified outphasing signal based on the transmission signal; and combining the power-amplified polar signal, the first power-amplified outphasing signal and the second power-amplified outphasing signal to provide the power-amplified transmission signal.

Abstract: Class-D amplifiers and modulators therefor provide control of the DC operating point of the outputs of the amplifiers. The modulators generate a sum and difference signal using combiners and introduce the sum signal to a reference input of the quantizer, while the quantization input of the quantizer receives the difference signal. A difference mode loop filter circuit may filter the difference signal and a common mode loop filter may filter the sum signal. Outputs of the quantizer operate a pair of switching circuits to provide either a differential output with the sum signal set to a constant voltage and the difference signal provided by the signal to be reproduced, or a pair of single-ended outputs with the individual input signals used to generate the sum and difference signal, and selection of a differential or dual single-ended operating mode may be performed by a control circuit that reconfigures the combiners.

Abstract: Differential control circuitry configured to control the operation of a power converter. The control circuitry of this disclosure is configured to receive two differential feedback signals from a fully differential amplifier. The amplifier receives an output voltage (Vout) from the switched mode power supply as well as a reference voltage (Vref). When Vout is less than Vref, the control circuitry may output a pulse width modulation (PWM) control signal to the switched mode power supply with a duty cycle of the PWM control signal based on a relative difference between a positive difference voltage and a negative difference voltage. When Vout is greater than Vref, the control circuitry may output a pulse frequency modulation (PFM) control signal to the switched mode power supply with a switching time of the PFM control signal based on a relative difference between the positive difference voltage and the negative difference voltage.

Abstract: A class-D amplifier configured to adjust at least one input signal to at least one output signal. The class-D amplifier comprises: a loop filter, configured to receive the input signal; a PWM circuit, configured to generate at least one PWM signal; a summing circuit, coupled between an output of the loop filter and an input of the PWM circuit; an output circuit operating at a supply voltage, configured to generate the output signal responding to the PWM signal; and a supply voltage filter, configured to monitor the supply voltage to generate a filtered signal to the summing circuit. The summing circuit is configured to sum the output of the loop filter and the filtered signal to adjust a common-mode level of the input of the PWM circuit.

Abstract: A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.

Abstract: A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.

Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated.